IET Power Electronics

Research Article

ISSN 1755-4535
Comprehensive analysis of a novel three- Received on 28th August 2015
Revised on 17th December 2015
phase multilevel inverter with minimum Accepted on 11th February 2016
doi: 10.1049/iet-pel.2015.0682
number of switches www.ietdl.org

Ravi Raushan ✉, Bidyut Mahato, Kartick Chandra Jana

Department of Electrical Engineering, Indian School of Mines, Dhanbad 826004, Jharkhand, India
✉ E-mail: ravi.roshan.b15@gmail.com

Abstract: A novel and generalised three-phase multilevel inverter (MLI) with a minimum number of switches have been
proposed. The number of voltage levels can be increased to a significant value by incorporating few switches and the
DC voltage sources. In the proposed three-phase MLI, the number of phase-voltage levels can be increased twice as
the number of switches increased. The detailed analysis of the proposed MLI, mathematical modelling of the inverter
voltage and the switching loss calculation have been done for a seven-level inverter. Modelling and simulations of the
proposed generalised three-phase inverter are carried out using MATLAB/SIMULINK. The simulation results of the
proposed multilevel configuration corresponding to the different voltage levels as well as at different modulation index
are presented. A laboratory prototype of the proposed five-level inverter has been developed and tested for the speed
control of an induction motor. The experimental results for the different modulation indexes are presented, that verifies
the simulation results. A detailed comparison of the proposed MLI with the other popular multilevel configuration is
presented to reflect the merits of the proposed structure for the reduced component count.

1 Introduction [17], which becomes significant for configuring a minimum switch

Multilevel inverters (MLIs) have been emerged as a promising power
converter topology for various applications in the medium and high
power industries, industrial motor drives including drives in electric
and hybrid-electric vehicle, renewable-energy sources interconnected
to the grid, high-voltage direct current, flexible AC transmission
systems system etc. This is due to, by virtue of numerous advantages
of the MLI, such as reduced dv/dt stress, lesser EMI interference,
staircase voltage waveform, lower harmonics etc.
Numerous MLIs topologies with abundant switching strategy has
been reported in the recent literature [1–4]. Among the MLIs, neutral
point clamped (NPC) or diode clamped, flying capacitor (FC) or
capacitor clamped and the cascaded H-bridge (CHB) [5–8] are the
classic MLI topology. The unequal voltage balancing among the
DC link capacitors that leads to an increase in clamping diodes as
the voltage level increases, can be considered as the limitation of
the NPC at a higher level. The FC MLI equipped with FCs as
clamping devices. Redundancy in phase voltage can allow the
switching stresses to be equally distributed between
semiconductor-switches, hence balances the voltage across the
capacitors [9, 10]. The FC MLI circuit becomes complex as a
large number of capacitors are required at higher voltage levels.
The cascaded MLI topology can be an acceptable option for high
voltage applications from the perspective of modularity. A large
number of isolated DC voltage sources for each of the modules
can again limit its future expansion capability. To improve the
total harmonic distortion (THD) of the above MLIs, either the
switching frequency or the number of voltage levels have to be
increased further. High switching frequency increases the
switching loss, and higher voltage levels require more switching
components that increase the conduction loss and reduce the
reliability of the inverter.
The above mentioned limitations, advance the research towards
the recent developments of MLIs with the minimum number of
switches [11–18]. The main objective of this work is to increase
the voltage levels by minimising the number of switching devices.
For the MLI, the ratio of the number of voltage levels and the
number of switches, is termed as the level to switch ratio (LSR)
MLI. The number of switches can be selected based upon the
value of LSR, cost as well as the level of the MLI. In this paper, a
new minimum switch three-phase general MLI has been proposed,
which can further increase two voltage levels of each phase by
incorporating one additional bidirectional switch per phase along
with a DC source for the entire three-phase inverter. Thus, the
proposed inverter topology can reduce the number of switches
significantly than the classical three-phase MLI topologies [5–8].
Some reduced switch MLIs with single DC source having other DC
sources substituted with capacitors and control algorithms are
introduced [19–25]. Single DC source CHB (SDC-CHB) with
control technique such as one-dimensional feedforward space-vector
modulation technique (1DFF-SVM) and phase shift modulation is
introduced [20, 23]. A novel PWM less three-phase asymmetric MLI
[21] using single DC source is introduced having three-leg inverter
cascaded with asymmetrical H-Bridges with capacitors at two legs.
Selection of capacitor-voltage and control algorithm with complex
controllers or non-linear controller is required to regulate voltage
level with proper charging and discharging.
Numerous modulation techniques reported throughout the
literature for the modulation of MLI [26–37]. Among them, the
high-frequency pulse width modulation (PWM) such as, carrier
phase-shifted and level-shifted PWM [19, 26], multi-reference
PWM [27] and space vector modulation techniques have been
used [28–31]. Moreover, selective harmonic elimination [32],
active harmonic elimination [33], nearest level control [34, 35] and
synchronous optimal PWM [36, 37] methods are reported as
low-switching-frequency modulation technique.
2 Proposed generalised three-phase MLI topology
with reduced switches
In this section, a new three-phase generalised MLI is proposed using
the minimum number of switching devices. The operation of
proposed three-phase MLI can be explained by dividing the whole
circuit in two parts as stage-I and stage-II converter and explained
their functionality separately. The stage-I converter is a hybrid

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1600 & The Institution of Engineering and Technology 2016
structure comprise two insulated gate bipolar junction transistors
(IGBTs) with anti-parallel diode forming the leg of the converter
and a few auxiliary bi-directional switches in each phase. The
auxiliary switch {(SAj ) j=1,2,3,…,3(m−1)} consists four diodes and an
IGBT illustrated in Fig. 1, by the dotted circle. For m number of
equal DC voltage sources in the stage-I converter, (m − 1) number
of auxiliary switches per phase are required along with two IGBTs
in each leg of the inverter to obtain (m + 1) number of voltage
levels across the stage-I converter with the magnitude of 0, VDC,
2VDC,…, mVDC.
The stage-II converter can be called as the voltage doubling
circuit, which consists of three identical half-bridge for each phase,
each comprises two switches {(SDP1 & SDP2)P=1,2 or 3} and one
DC voltage source of magnitude mVDC. The stage-II converter
produces two voltage levels of magnitude 0 and −mVDC. By
selecting proper switching signal for the entire inverter, the phase
voltage levels can be made twice the number of voltage levels of
the stage-I converter. Hence, for the proposed MLI with m number
of DC sources in stage-I, the number of phase voltage level
becomes (2m + 1) with the magnitude of –mVDC, –(m − 1) VDC,….
0,… (m − 1) VDC, mVDC.
For a three-phase seven-level inverter, each phase of the stage-I
converter should consist of four switches (including two auxiliary
switches), that generate four voltage levels with the magnitude of
0, VDC, 2VDC and 3VDC while the stage-II converter consists only
two switches per phase and generates 0 and −3VDC. Thus, with a
proper switching signal, each phase of the proposed seven-level
inverter have the voltage levels of −3VDC, −2VDC, −VDC, 0, VDC,
2VDC and 3VDC. For further higher voltage levels, one auxiliary
switching device per phase is required for two additional voltage
levels.
The proposed configuration of a three-phase seven-level inverter
with a minimum number of switches is shown in Fig. 2. The
switching status of any phase and the corresponding voltage levels
of the proposed inverter under different modes of operation are
given in Table 1.
The operation of each phase of the proposed three-phase inverter
is identical. Therefore, the operation of the proposed three-phase
MLI phase-A is explained under different mode as shown in
Fig. 3. The proposed seven-level inverter has eight modes of
operation, in which the stage-I converter can generate the voltage
levels of magnitude 3VDC, 2VDC, VDC and Zero under various
Fig. 1 Proposed generalised three-phase M-level inverter with reduced
switch
IET Power Electron., 2016, Vol. 9, Iss. 8, pp. 1600–1607
& The Institution of Engineering and Technology 2016
modes of operation as specified in Table 1. The details of the per
phase circuit operation of stage-I and stage-II converter for
generating the different voltages under the specified mode is
depicted in Fig. 3. In the first four modes, switch SD11 of stage-II
converter continuously remains ON (V2 = 0) and the switches of
the stage-I converter (S1, S2, SA1, SA4) operates in such a manner
that, it can generate the voltage V1 of magnitude 3VDC, 2VDC, VDC
and Zero under Mode-1, Mode-2, Mode-3 and Mode-4,
respectively. In the remaining four modes, the switch SD12 of
stage-II converter remains on constantly and generate the voltage
V2 of the magnitude −3VDC and the stage-I converter generates a
voltage V1 of magnitude 3VDC, 2VDC, VDC and Zero in Mode-5,
Mode-6, Mode-7 and Mode-8, respectively, by operating the
switches S1, S2, SA1 and SA4 in the same way as under the
previous four modes. Hence, by combining stage-I and stage-II
converter, the whole inverter will operate in eight different modes
and can generate the phase voltages of magnitude 3VDC, 2VDC,
VDC, 0, −VDC, −2VDC and −3VDC.
It is required to mention that, to obtain all the positive phase
voltage levels and one ‘zero’ level under first four modes of
operation, the switch SD11 remain ON, whereas, for obtaining all
the negative voltage levels and a ‘zero’ level, the switch SD12
should conduct continuously in the last four modes. Therefore, the
switches SD12 and SD12 can be operated at the fundamental
switching frequency to obtain the seven-level voltage across the
output of the inverter.
3 Mathematical formulation of phase voltage of
the proposed MLI
The phase voltage of a MLI can be modelled by the switching
functions having different switching patterns or the switching
frequency. In the proposed generalised MLI as shown in Fig. 1,
the switching function (1 = ON, 0 = OFF) for the upper switches
(S1, S3, S5) and the lower switches (S2, S4, S6) of the three legs
can be expressed as SU and SL. In addition to this, the switching
function of the auxiliary switches (SAj ) and the switches of the
voltage doubler circuit (SDP1, SDP2) can be expressed as SA[3(k−1)+p]
and (SDU, SDL), respectively. Thus, the proposed MLI with m
Fig. 2 Proposed three-phase seven-level inverter with a minimum number
of switches
1601
Table 1 Per phase switching status of the proposed seven-level inverter and the corresponding voltage levels obtained under different modes of
operation

Modes Switching status 1 = ON; 0 = OFF Converter voltage Phase voltage

S1 S2 SA1 SA4 SD11 SD12 Stage-I (V1) Stage-II (V2) VAn = V1 + V2

1 1 0 0 0 1 0 3VDC 0 3VDC
2 0 0 1 0 1 0 2VDC 0 2VDC
3 0 0 0 1 1 0 VDC 0 VDC
4 0 1 0 0 1 0 0 0 0
5 1 0 0 0 0 1 3VDC −3VDC 0
6 0 0 1 0 0 1 2VDC −3VDC −VDC
7 0 0 0 1 0 1 VDC −3VDC −2VDC
8 0 1 0 0 0 1 0 −3VDC −3VDC

number of DC voltage sources of each magnitude VDC in the stage-I can be expressed as
converter and one voltage source of magnitude mVDC in stage-II
converter, the phase voltage of the inverter can be expressed as  


m

m−1

m
V 1(t) = SU VDCi + VDCi SA[3(k−1)+P] + SL V0 ; (2)
i=1 k=1 i=k+1
VPh = V 1(t ) + V 2(t ); (1)
V 2(t) = m(V0 SDU − VDC SDL ) (3)

where, voltage V1 (t) and V2 (t) of the stage-I and stage-II converter where, V0 is the zero as no voltage source is active.

Fig. 3 Operation of phase-A inverter of the proposed three-phase seven-level inverter under different modes

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Fig. 4 Level shifted PWM
a Comparison of carriers with references and corresponding switching states of seven-level inverter
b Corresponding PWM implementation technique for phase-A

The above mathematical modelling of the inverter phase voltage

can be verified for the proposed seven-level inverter phase-A with
three equal voltage sources VDC,1, VDC,2, VDC,3 of magnitude VDC
in the stage-I converter and 3VDC in the stage-II converter. In
Mode-3 operation as given in Fig. 3, the auxiliary switch SA4 is
ON, thus the value of switching function for SA4 can be assumed
as 1 (1 = ON). Similarly the switching function for switch S1 and
S2 becomes 0 (i.e. SU = 0 and SL = 0) as both of the switches S1
and S2 are remain OFF. Similarly, the switching function of the
stage-II converter switches can be assumed as SDU = 1 (SD11 =
ON) and SDL = 0 (SD12 = OFF). Hence, from (2)–(3), the value of
V1(t) and V2(t) can be obtained as VDC (V1(t) = VDC,3 = VDC) and
0 (V2(t) = 0). Therefore, the phase voltage at the Mode-3 has been
obtained by VDC (Vph = VDC + 0 = VDC).

4 Modulation and control of the proposed MLI

In the present work, a multi-carrier based level-shifted PWM scheme

[26] has been adopted for the proposed generalised three-phase MLI.
A sinusoidal reference waveform of the fundamental frequency is
compared with six high frequency triangular carrier waveforms
Vcr3−, Vcr2−, Vcr1−, Vcr1+, Vcr2+ and Vcr3+ for generating the PWM
switching signal of the seven-level inverter as shown in Fig. 4a.
The switching signals can be further decoded to obtain the gate
pulses of the proposed inverter as per the switching Table 2. The
above PWM implementation technique for the seven-level inverter
is further shown in Fig. 4b. The switching pulse pattern
corresponding to the switches of phase-A is depicted in Fig. 5.
The pattern indicates that switches of the stage-II converter (SD11
and SD12) are operating at the fundamental frequency and switches
in the stage-I converter (S1, SA1, SA4 and S2) are having nearly
same switching frequency.
Table 2 Switching table corresponding to the switching states
Switching state [SP] Mode of On-state
(P = A, B, C phase) operation switches
4 1 S1, SD11
3 2 SA1, SD11
2 3 SA4, SD11
1 4 S2, SD11
0 5 S1, SD12
−1 6 SA1, SD12
−2 7 SA4, SD12
−3 8 S2, SD12
Fig. 5 Switching pulse pattern for phase-A of proposed seven-level inverter
at switching frequency 1 kHz
5 Calculation of losses in proposed topology
An IGBT has three types of losses, such as (i) Conduction loss,
(ii) Switching loss and (iii) Blocking state loss. However, the losses
during the blocking state can be neglected, as it is very small in
magnitude compared with other losses. Switches in the inverter
should be differently rated due to the asymmetry in the configuration.
Switches of the stage-II converter having blocking voltage of
Output phase magnitude mVDC have higher voltage rating than switches of the
voltages stage-I converter. As high-voltage rated switches are operating at low
frequency will cause more conduction loss and low-voltage rated
3VDC switches operating at high frequency will cause more switching loss.
2VDC
VDC
0
5.1 Calculation of conduction losses
−VDC
−2VDC
−3VDC
The conduction loss occurs during the ON period of one switch.
Therefore, the power dissipation in conduction mode can be

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& The Institution of Engineering and Technology 2016 1603
calculated by multiplying the on-state voltage drop Von (t) with the
magnitude of current I (t) that flows through the device [38] after
turn-on period, can be determined as

pC (t) = Von (t) · I(t) (4)

The saturation voltage of the bidirectional switch as used in Fig. 1, is

the sum of the saturation voltage of two diodes and an IGBT,
approximated by a linear function as expressed as
Fig. 6 Current and voltage waveform during turn-off and turn-on period
Von,bi = Von,IGBT + 2Von,Diode
(5)
= (VT + RT · I b ) + 2(VD + RD · I) ton
Eon = V (t) · I (t ) dt
where, VT and VD are the on-state voltage drops of the IGBT and 0
diode, whereas RT and RD are their on-state resistances and β is a ton


VIGBT,j I VIGBT,j Iton
constant governed by the IGBT characteristics. If the inverter = VIGBT,j − t t dt = (10)
operates at a higher voltage level, the output currents can be 0 ton toff 6
considered as near sinusoidal. The instantaneous conduction losses
( pC,bi (t)) due to the load current of I = ILsin (ωt) in a bidirectional The stage-I converter having m number of DC voltage sources and m
switch can be derived as +1 number of switches (including auxiliary switches) with the
operating frequency of jth switch is assumed as fsI,j and blocking
voltage VSI,j. Similarly, the stage-II converter having one DC
pC,bi (t) = (VT + 2VD )IL sin (vt) + 2RD · IL2 sin2 (vt) voltage source of magnitude mVDC and two switches that operates
(6) at the fundamental frequency ( f0) and blocking voltage VSII,j. The
+ RT · ILb+1 sinb+1 (vt); switching loss of the stage-I converter (PswI) and stage-II converter
(PswII) is the summation if turn-on loss and turn-off loss of the
In each phase, there are m−1 number of auxiliary switches are respective converter switches.
present accompanied by four IGBT switch with anti-parallel diode. Thus, the total switching loss per phase of the proposed MLI
Conduction losses in the above four switches (two in stage-I and (stage-I and stage-II converter) can be derived as
two in stage-II) depends upon the power-factor also. Hence, the
instantaneous conduction losses per phase ( pC,SW(t)) of the m+1 



1
inverter switches such as IGBT/diode can be determined as Psw = PswI + PswII = VSI,j I ton + toff fsI,j
j=1
6
(11)
pC,SW (t) = (nT (t) VT + nD(t) VD )IL sin (vt) + nD(t) RD · IL2 sin2 (vt) 2 



1
+ VSII,j I ton + toff f0
+ nT (t) RT · ILb+1 sinb+1 (vt). (7) j=1
6

Here, nT(t) and nD(t) is the number of conducting IGBT and diode at Let, C = (1/6)I ton + toff will be a constant for a specific load
any instant in a phase of the inverter. Considering pCk ,bi (t) as current and switching frequency. Hence, the above switching loss
instantaneous conduction losses in kth auxiliary switch, the average expression can be simplified as
value of conduction losses for all the switches of each phase
including auxiliary can be written as m+1 


2  
Psw = C VSI,j fsI,j + VSII,j f0 (12)
m−1 p   p j=1 j=1
1
1 
PC,avg = pCk ,bi (t) dwt + pC,SW (t) dwt (8)
p k=1 0 p 0 For a seven-level inverter, there are four switches in the stage-I
converter, including two auxiliary switches and two switches in
the stage-II converter as depicted in Fig. 2. The switching
5.2 Calculation of switching losses frequency of the stage-I and stage-II converter switches can be
assumed as fsI and fo with their blocking voltage of magnitude
To calculate the switching losses in the switching device, the linear VDC and 3VDC, respectively. Therefore, the per-phase switching
approximation of the current and voltage of a typical switch such as loss of the proposed seven-level inverter can be determined from
an IGBT during the turn-off and turn-on periods are used [16, 39]. (12) as
The switching losses or the power dissipation during the transition  
of the state of a switch can be determined as the integration of the Psw = C 4(VDC ) fsI + 2(3VDC ) f0 = 2CVDC 2 fsI + 3 f0 (13)
product of the voltage and the current waveforms during the
switching transition period (ton and toff ). Since switching frequency fsI (same as carrier frequency) is very
The approximate voltage and current characteristics of an IGBT large as compared with the fundamental frequency ( f0), the
during the turn-on (ton) and turn-off period (toff ) is shown in switching loss per phase of proposed seven-level inverter can be
Fig. 6. An IGBT that carries a constant current of magnitude I further approximated as
after ton period with a blocking voltage VIGBTj after toff, the energy
losses of the IGBT Eon and Eoff during ton and toff period can be Psw ≃ 4CVDC fsI . (14)
expressed [33] as
toff toff

 The seven-level symmetrical CHB consists of twelve switches each
VIGBT,j I having blocking voltages of magnitude VDC. The corresponding
Eoff = V (t ) · I (t ) dt = t I− t dt switching loss for the seven-level symmetrical CHB can be
0 0 toff toff
approximated as [40]
VIGBT,j Itoff
= (9)
6 Psw = 12CVDC fsI . (15)

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1604 & The Institution of Engineering and Technology 2016
Fig. 7 Simulation result of line voltage Vab (V) and corresponding THD of proposed
a Eleven-level inverter with VDC = 35 V
b Seven-level inverter with VDC = 55 V with switching frequency, Fs = 3.0 kHz and modulation index, Mi = 1.0
Therefore, from the above discussion, it is observed that the
switching loss in the proposed MLI is approximately one third
compared with the symmetrical CHB operated under same
condition.
6 Simulation and experimental results
Modelling and simulation of the proposed generalised three-phase
MLI is carried out using MATLAB/SIMULINK to validate the
performance and the results corresponding to the eleven-level,
seven-level and five-level is presented. The magnitude of DC
voltage sources (VDC) in stage-I and for the eleven-level and
seven-level inverter is considered as 35 and 55 V. Similarly for the
stage-II converter the DC link voltage across the voltage doubler
circuit of the eleven- and seven-level inverter is considered as and
175 and 165 V, respectively, for matching the voltage required by
the load. An induction motor of rating 1.5 HP, 200 V, 50 Hz is
chosen for the simulation purposes as well as for experimental
verification. The switching frequency of the inverter (Fs) is chosen
as 3 KHz for both simulation and experimental purposes to
improve harmonics profile and shrink filter size. The simulation
results of inverter voltage and the harmonic spectrum
corresponding to the eleven- and seven-level is shown in Fig. 7.
From Fig. 7, it is observed that the THD in the line voltage
waveform of the proposed eleven-level and seven-level inverters
are 6.45% and 10.77%, respectively.
For the purpose of hardware verification of the theoretical results,
a laboratory prototype of five-level inverter of the proposed
multilevel configuration is developed. The isolated DC voltages
are obtained from the AC sources using transformer-rectifier and
capacitor arrangements. The proposed three-phase five-level
inverter comprises 12 IGBT switches (SD11, SD12, SD21, SD22, SD31,
SD32, S1, S2, S3, S4, S5 and S6), three auxiliary or bi-directionally
Fig. 8 Simulation result of line voltage and stator current at
a Mi = 1
b Mi = 0.6
c Mi = 0.3
IET Power Electron., 2016, Vol. 9, Iss. 8, pp. 1600–1607
& The Institution of Engineering and Technology 2016
controlled switches (SA1, SA2 and SA3) and five DC voltage sources
(two in stage-I converter and three in stage-II converter) as
indicated by an arrow in the left-hand side of the Fig. 1. The gate
pulses of the switches are generated using the level-shifted PWM
technique.
To control the speed of the induction motor, a constant V/f
technique has been implemented using the DS1103 based digital
controller, due to its availability in the laboratory. The simulation
and experiments are conducted with the identical parameters for
better comparison of the results. To verify the performance of the
proposed inverter, the induction motor can be operated at different
modulation indexes (0 < Mi < 1) with a constant V/f mode.
Simulation as well as experimental results of line to line voltage
and stator current of the proposed five-level inverter at different
modulation indexes (0.3, 0.6 and 1.0) are presented as shown in
Figs. 8 and 9. From Figs. 8 and 9, it is clearly observed that, the
number of voltage level changes with the Mi. It is also observed
that the stator current of the induction motor at different Mi are
near sinusoidal.
A comparative study of the proposed generalised MLI with some
of the popular MLI topology has been done in terms of number of
components as well as voltage sources used. The important
features of the MLI configuration and their limitations are also
analysed and presented in Table 3. From the table, it is observed
that, the proposed MLI is better than most of the MLI in terms of
number of switching devices except the MLI given in [17].
However, the MLI configuration demonstrated in [17] may apply
for few odd numbers of voltage levels.
To analyse the effectiveness of the proposed multilevel
configuration compared with the other multilevel configuration, the
number of phase voltage level to switch ratio (LSR) corresponding
to 13-level inverters have been calculated based on the Table 3.
The results corresponding to LSR of all MLIs, except the
configuration illustrated in [17] (it is applicable for few even
1605
Fig. 9 Experimental results of line voltage and stator current of the proposed five-level inverter at Fs = 3.0 kHz, VDC = 70 V, [current scale: 5 A/Div., time scale:
10 ms/Div.] for
a Mi = 1.0 [voltage scale: 200 V/Div.]
b Mi = 0.6 [voltage scale: 150 V/Div.]
c Mi = 0.3 [voltage scale: 150 V/Div.]

Table 3 Components requirement for M-level three-phase inverters

Component/Inverter Number Number of Number of separate Remarks
type of IGBTS/ bidirectional DC Supply and DC
MOSFETS controlled switches link capacitor

NPC [5] 6 (M−1) 0 M−1 1. A large number of diodes are required to increase the level.
FC [6] 6 (M−1) 0 M−1 1. A large number of capacitors are required with increase in
level.
cascaded H-bridge 6 (M−1) 0 1.5 (M−1) 1. The separate DC sources are required.
MLI [7] 2. Complex controller is required for voltage balancing, if the
capacitors replace the DC source.
3. Asymmetric (binary and tertiary) configuration is possible.
T-type MLI [11] 6 3 (M−2) M−1 1. Required non-isolated DC supply
2. Both unidirectional and bidirectional switches are required.
3. Asymmetric configuration is not possible.
SSPS MLI [12] 1.5 (3M−1) 0 1.5 (M−1) 1. Asymmetric (binary) configuration is possible.
SCSS MLI [13] 3 (M+3) 0 1.5 (M−1) 1. Power switches have different voltage rating
MLDCL [14] 3 (M+3) 0 1.5 (M−1) 1. Requires Isolated DC supply.
2. Asymmetrical (binary) configuration is possible.
CBSC MLI [15] 0 3 (M+1) 1.5 (M−1) 1. Power switches have different voltage rating.
2. Asymmetrical configuration is not possible.
3. Only bidirectional switches are used.
MLM [16] 12 1.5 (M+1) 1.5 (M−1) 1. Both unidirectional and bidirectional switches are required.
2. Required Isolated DC supply.
√ √ 3. Asymmetrical configuration is not possible.
MLI [17] 3( 4M − 7+1) 0 1.5( 4M − 7−1)+1 1. Applicable for few even numbers of voltage levels.
2. Requires Isolated DC supply.
MLI [18] 3 (M+1) 0 0.25 (3M+1) 1. All odd numbers of voltage levels can’t be achieved.
√ √ 2. Required Isolated DC supply.
PUC5 [19] 6( M − 1+1) 0 3+[3( M − 1−1)]a 1. Self-balancing property without any sensors.
2. Able to produce voltage levels such as 5, 10, 17, 26….
MLI [41] 6 (M−1) 0 1.5 (M−1) 1 Asymmetric (binary and Tertiary) configuration is possible.
MLI [42] 6 (M−2) 3 M−1 1. Both unidirectional and bidirectional switches are required.
2. Asymmetric configuration is not possible
modified FCMC [24] 6 (M+2K−1) 0 3K+[3(M−K−1)]a 1. Modular structure.
(K = number of 2. Large number of capacitors is required.
modules in each
phase)
hybrid MLI [25] 6 (M−2) 0 1+[0.5 (3M−5)]a 1. Large number of capacitors is required. 2. Asymmetric (binary)
configuration is possible.
proposed MLI 12 1.5 (M−3) 0.5 (M−1)+3 1. The addition of one more switch can generate two extra
voltage levels per phase.
2. Non-isolated DC supply.
3. The High voltage switches operate at the fundamental
switching frequency.

a
DC link capacitor.

numbers of voltage levels) are depicted in Fig. 10. From the Fig. 10,
it is observed that, the magnitude of LSR of the proposed inverter
corresponding to 13-level inverter is 1.44, which is much better
than the other multilevel configurations reported in this paper.

7 Conclusion

The paper demonstrated a new generalised three-phase MLI

configuration with reduced number of switches and the isolated
Fig. 10 Comparison of the proposed inverter with the different MLIs in DC sources. By incorporating one extra switch per phase and by
terms of phase voltage LSR for 13-level adding one additional DC source for the three-phase inverter, two

IET Power Electron., 2016, Vol. 9, Iss. 8, pp. 1600–1607

1606 & The Institution of Engineering and Technology 2016
additional voltage levels obtained in each phase. To analyse the
effectiveness of the proposed multilevel configuration with lower
number of switches, the magnitude of voltage LSR of the different
MLI have been calculated and the results are compared with the
results of the proposed MLI configuration. It has been observed
that, the proposed MLI configuration is better than the other MLI
reported in this paper in terms of LSR values. The mathematical
modelling of the proposed MLI phase voltage has been done using
the switching function. The detailed analysis of inverter losses due
to conduction as well as switching is also conducted and the
results are compared with the CHB MLI. It has been observed
that, the proposed MLI configuration has a lesser amount of power
losses than the other inverter configuration due to the lesser
number of switches and DC voltage sources. The proposed MLI
configuration corresponding to thirteen-, seven- and five-level have
been simulated using MATLAB/Simulink platform and the results
are presented. Experiments have been conducted on a laboratory
prototype of proposed five-level inverter for the speed control of
the induction motor. The experimental results corresponding to the
different modulation indexes are also presented that verified the
respective simulation results.
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