358 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 14, NO.

2, MARCH 2015

A Compact Analytical Model for the Drain Current

of Gate-All-Around Nanowire Tunnel FET Accurate
From Sub-Threshold to ON-State
Rajat Vishnoi, Graduate Student Member, IEEE, and Mamidala Jagadesh Kumar, Senior Member, IEEE

Abstract—We present a compact analytical model for the drain

current of a gate-all-around nanowire tunneling field effect tran-
sistor. The model takes into account the effect of oxide thickness,
body doping, drain voltage, and gate metal work function. The
model uses a tangent line approximation method to integrate the
tunneling generation rate in the source-body depletion region. The
accuracy of the model is tested against three dimensional numer-
ical simulations calibrated using experimental results. The model
predicts the drain current accurately in both the on-state (strong
inversion), as well as in the sub-threshold region.
Index Terms—Nanowire, off-state current, on-state current, sub-
threshold slope (SS), three dimensional (3-D) modeling, Tunneling
field effect transistor (TFET). Fig. 1. Schematic view of the p-channel GAA nanowire TFET.

I. INTRODUCTION
FETS have been widely studied as an alternative to the
T MOSFETs in the sub-100 nm regime [1]–[6] as they pro-
vide a better immunity to short channel effects (SCEs) and
a lower sub-threshold swing (SS) [7]. The OFF-state leakage
current in TFETs is low making them desirable in low power
applications. A gate-all-around (GAA) structure, due to an en-
hanced electrostatic control of the gate over the channel, further
improves SCEs and SS [8], [9]. Besides, the device geometry
provides a higher ON-state current (ION ) per unit area than pla-
Fig. 2. Band diagram of the GAA nanowire TFET at VG S = −1.5 V and
nar devices. Hence, developing accurate models for the drain VD S = −0.5 V showing the tunneling region R1.
current of a GAA TFET becomes important.
A few analytical models have been developed for GAA
then use the tangent line approximation method to integrate the
TFETs [10], [11]. However, these models have limited accu-
tunneling generation rate along the channel, giving us the drain
racy in the sub-threshold region as they consider constant elec-
current.
tric field (either peak or average value) in the entire tunneling
The validity of the model is tested against 3-D numerical
region. Hence, it becomes important to develop a compact ana-
simulations [14] calibrated against previously published exper-
lytical model for the drain current of a GAA TFET accurate in
imental results [11].
the entire range of operating voltages.
In this work, we develop a compact analytical model for the
II. MODEL DERIVATION
drain current of a GAA nanowire TFET. Using the surface po-
tential model from [12] to find the electric field in the tunneling Fig. 1 shows the schematic view of the p-channel GAA
region, we estimate the tunneling generation rate in the channel nanowire TFET. It has the following parameters: channel length
using the Kane’s model for band-to-band tunneling [13]. We (L) = 50 nm, body doping (NS ) = 1015 /cm3 , source/drain
doping = 1021 /cm3 , length of source/drain regions = 50 nm,
Manuscript received October 26, 2014; revised January 16, 2015; accepted oxide thickness (Tox ) = 2 nm, radius of the nanowire (TS i ) =
January 20, 2015. Date of publication January 22, 2015; date of current version 10 nm and gate work-function (Φ) = 5.0 eV. [11]
March 6, 2015. The review of this paper was arranged by Associate Editor E. The band diagram of the GAA TFET is shown in Fig. 2. We
Tutuc.
The authors are with the Department of Electrical Engineering, Indian can observe that due to the thinning of the barrier between the
Institute of Technology Delhi, New Delhi 110 016, India (e-mail: vish- valence and the conduction band, the carriers (holes in this case)
noir@gmail.com; mamidala@ee.iitd.ac.in). can tunnel from the conduction band in the source to the valence
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. band in the drain giving rise to the drain current (depicted by
Digital Object Identifier 10.1109/TNANO.2015.2395879 solid arrow). The tunneling generation rate (Gbtb ) of carriers for
1536-125X © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
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VISHNOI AND KUMAR: COMPACT ANALYTICAL MODEL FOR THE DRAIN CURRENT OF GATE-ALL-AROUND NANOWIRE TUNNEL 359

band-to-band tunneling is given by the Kane’s model [13]:

 
3/2
|E γ | Eg
Gbtb = A  exp −B (1)
Eg |E|
where A and B are tunneling parameters, E is the electric field
and Eg is the band gap of the material. We need to find the elec-
tric field E to estimate Gbtb . The factor γ is the pre-exponential
factor which is 2 for direct band-gap tunneling and 2.5 for in-
direct band-gap tunneling [13]. Since, our device material is
silicon, which is an indirect band gap material, we have taken
γ = 2.5.
The surface potential in region R1 for a GAA TFET, derived
in our previous work [12], can be written as:
 
z − Lt qNS L2d
ψS (z) = C cosh + ψG − (2a)
Ld εS i
 
qNS L2d
C = ψC − ψ G + /2 (2b)
εS i
  
2 Tox
Ld = TS i ln 1 + εS i /(2εox ) (2c)
TS i
where NS is the body doping and ψG is the electrostatic potential
of the gate which is equal to VG S − VF B . Here VF B is the flat-
band voltage of the TFET. Ld is the characteristic length, Lt is
the length of the tunneling region (i.e., region R1) and ψC is
the surface potential in region R2 and can be evaluated as given
in [12]. By differentiating the surface potential (2), the electric
field can be written as:
∂ψS (z)
E(z) = − (3a)
∂z
 
C z − Lt
E(z) = − sinh . (3b)
Ld Ld
In the tunneling region (i.e., region R1), the electric field
along the r- direction is small compared to the electric field
along the z- direction. Hence, the band-to-band tunneling along
the r-direction can be neglected and we can substitute the electric
field along the z-direction obtained in equation (3b) into equation
(1) to find the tunneling generation rate Gbtb .
The drain current can be calculated by numerically integrating
Gbtb over the entire tunneling volume:

ID = q Gbtb dV . (4)

However, numerical integration of tunneling rate to find the

drain current is computationally tedious and will make circuit
simulations inefficient and time consuming. To develop a model
which is computationally efficient the drain current has to be
expressed in the form of a single closed form equation. To do
this, we need to approximate the integration of equation (4)
without significantly losing the accuracy. This can be realized
by using the tangent line approximation method as described
below.
Fig. 3(a) and (b) show the tunneling generation rate Gbtb (x) Fig. 3. Tunneling generation rate (G b t b ) for the GAA nanowire TFET along
the channel (red curve) starting at the source-body junction for VG S = −1.5 V
at the surface along the channel given by using equation (3) and VD S = −0.5 V. The shaded areas in (a)–(e) give G1 , G2 , G3 , G1 d and,
in equation (1). To find the drain current, we have to integrate G2 d , respectively.

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360
Gbtb (x) along the channel length. Since equation (1) does not
have a closed form integration, we need to approximate this
integration as follows. We assume x = 0 as the source channel
interface. At x = 0, we draw a tangent l1 to the Gbtb (x) curve
and extend it to its x intercept L1 (see Fig. 3(a)):
L1 = Gbtb (0)/Gbtb (0).
We can now find the area G1 under this line l1 (Fig. 3(a)):
G1 = 0.5Gbtb (0)L1 2 .
Next, at x = L1 , we draw a tangent l2 to the Gbtb (x) curve
and extend it from its x intercept (L1 + L2 ) to the point where
it intersects the previous line l1 (see Fig. 3(b)).
L2 = Gbtb (L1 )/Gbtb (L1 )
L1d = Gbtb (0)L2 /[Gbtb (0) − Gbtb (L1 )].
Now find the area G2 (see Fig. 3(b)) under the line l2 and the
area G1d (see Fig. 3(d)) common between lines l1 and l2 :
G2 = 0.5Gbtb (L1 )L1d 2
G1d = 0.5Gbtb (0)(L1d − L2 )2 .
The same process is repeated another time. At x = L1 + L2 ,
draw a tangent l3 to the Gbtb (x) curve and extend it from its
x intercept (L1 + L2 + L3 ) to the point where it intersects the
line l2 (see Fig. 3(c)):
L3 = Gbtb (L1 + L2 )/Gbtb (L1 + L2 )
Gbtb (L1 )L3
L2d = . (12)
[Gbtb (L1 ) − Gbtb (L1 + L2 )]
Now find the area G3 (see Fig. 3(c)) under the line l3 and the
area G2d (see Fig. 3(e)) common between lines l2 and l3 :
G3 = 0.5Gbtb (L1 + L2 )L2d 2
G2d = 0.5Gbtb (L1 )(L2d − L3 ) .2
The same tangent line approximation process can be repeated
n number of times to improve the accuracy of the integration.
The following equations apply for the nth step:
Gbtb (L1 + L2 + L3 + · · · + Ln −1 )
Ln =
Gbtb (L1 + L2 + L3 + · · · + Ln −1 )
Ln −1d =
Gbtb (L1 +L2 + · · · + Ln −2 )Ln
[Gbtb (L1 +L2 + · · · + Ln −2 )−Gbtb (L1 + L2 + · · · + Ln −1 )]
Gn = 0.5Gbtb (L1 + L2 + · · · + Ln −1 )Ln −1d 2
Gn −1d = 0.5Gbtb (L1 + L2 + · · · + Ln −2 )(Ln −1d − Ln )2 .(18)
The total tunneling generation rate (GT ) after n repetition
steps is given by:
GT = G1 + G2 + ... + Gn − G1d − G2d − .... − Gn −1d .
(19)
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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 14, NO. 2, MARCH 2015
TABLE I
ACCURACY OF TANGENT LINE APPROXIMATION
Number of repetition steps ACCURACY
1 53%
2 80%
(5) 3 89%
4 92%
5 93%
6 93.6%
7 93.7%
(6)
Table I shows the accuracy of the tangent line approximation
with the number of repetition steps. The accuracy is evaluated
by dividing GT after n steps with the numerical integration of
(7) the Gbtb (x) curve. The accuracy settles at around 93% after the
fourth step and hence in our model we use four steps of tangent
(8)
line approximation.
The total tunneling generation rate in our model is thus given
by:
(9) GT = G1 + G2 + G3 + G4 − G1d − G2d − G3d . (20)
(10) Equation (20) gives an analytical result of the total generation
rate which is a close approximation of the numerical integration
of Gbtb (x) along the channel length.
The drain current ID is given by:
ID = qAK GT (21)
(11) where AK is a constant which incorporates the thickness of
the tunneling region in the r-direction (which is typically equal
to the thickness of the inversion layer). The proposed model is
analytical and gives a closed form equation for the drain current,
which makes circuit simulations computationally efficient. Also,
the model is not piece-wise and is continuous and therefore,
differentiable at all the points. The model can be differentiated
(13) infinitely, a property needed for analog circuit simulations.
(14)
III. EXTENSION OF MODEL TO A DOUBLE GATE (DG)
STRUCTURE
The model can be extended to a DG structure by making
a change in equation (2c) for the characteristic length Ld as
follows:
(15)
TS i Tox εS i
Ld = . (22)
2εox
Rest of the model remains unchanged for a DG TFET.
(16) IV. MODEL VALIDATION
(17) The validity of the proposed model is tested by comparing the
surface potential and the drain current against 3D numerical sim-
ulations [14]. In the simulations, models for concentration de-
pendent mobility, electric field dependent mobility, SRH recom-
bination, auger recombination, band gap narrowing and Kane’s
band to band tunneling have been used. The tunneling parame-
ters of Silvaco ATLAS [14], AK an e ( = 4 × 1019 eV1/2 /cm·s·V2 )
and BK an e ( = 41 MV/cm·eV3/2 ), are extracted by accurately
VISHNOI AND KUMAR: COMPACT ANALYTICAL MODEL FOR THE DRAIN CURRENT OF GATE-ALL-AROUND NANOWIRE TUNNEL
Fig. 4. Comparison of Surface potential curves given by the model (solid
lines) and by simulation (dashed lines).
Fig. 5. ID versus VG S curves for the GAA nanowire TFET given by the model
(lines) and by simulation (dots) for VD S = −50 mV and VD S = −0.5 V.
reproducing the experimental results for a SOI TFET [11] as
done in our previous work [12]. These tunnelling parameters
are material properties and depend on the band structure of the
material [13]. Hence, the values of the tunnelling parameters
calibrated against a SOI TFET in [12] also hold for a silicon
based GAA Nanowire TFET, unless the dimensions are in the
quantum confinement range (i.e. radius < 5 nm), in which case
the band structure of a material may change.
Fig. 4 shows the surface potential along the channel given by
equation (2) and compares it with the simulation results. The
model results match well with the simulations. Fig. 5 compares
the ID –VGS curves for different VDS given by the model with
the simulation results. The model predicts the drain current
accurately for the entire range of gate voltages. Hence, the model
can also be used to find the sub-threshold slope. Fig. 6 shows
the ID -VGS curves for a DG TFET with a silicon film thickness
of 10 nm and other parameters similar to the GAA TFET. The
model results match well with the simulations confirming that
our model is extendable to a DG TFET.
The model developed in this work has been validated to work
for a channel length of 50 nm. The derived model is independent
of gate or channel length as the surface potential in region R2
of the channel is almost constant (as can be seen in Fig. 2 and
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361
Fig. 6. ID versus VG S curves for DG TFET given by the model (lines) and
by simulation (dots) for VD S = −50 mV and VD S = −0.5 V.
Fig. 4) and hence a variation in the channel or gate length does
not change the drain current. The model however, is dependent
on the gate work function and channel doping as can be observed
from equation (2a).
V. CONCLUSION
In this work, we have developed a compact analytical model
for the drain current of a GAA nanowire TFET. Using the sur-
face potential model [12], we find the electric field from which
we calculate the tunneling generation rate in the channel. We
then use the tangent line approximation method to calculate the
integral of the tunneling generation along the channel, which
gives us the drain current. We also extend our model to a DG
structure. The proposed model is verified against 3-D numeri-
cal simulations and is demonstrated to be accurate in both the
on-state (strong inversion) as well as in the sub-threshold region.
REFERENCES
[1] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for be-
yond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec.
2010.
[2] S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, “Performance
comparison between p-i-n tunneling transistors and conventional MOS-
FETs,” IEEE Trans. Electron. Devices, vol. 56, no. 3, pp. 456–465, Mar.
2009.
[3] E.-H. Toh, G. H. Wang, G. Samudra, and Y. C. Yeo, “Device physics
and design of germanium tunneling field-effect transistor with source and
drain engineering for low power and high performance applications,” J.
Appl. Phys., vol. 103, no. 10, pp. 104504-1–104504-5, 2008.
[4] M. J. Kumar and S. Janardhanan, “Doping-less tunnel field effect tran-
sistor: Design and investigation,” IEEE Trans. Electron. Devices, vol. 60,
no. 10, pp. 3285–3290, Oct. 2013.
[5] S. Saurabh and M. J. Kumar, “Estimation and compensation of process
induced variations in nanoscale tunnel field effect transistors (TFETs)
for improved reliability,” IEEE Trans. Device Mater. Rel., vol. 10, no. 3,
pp. 390–395, Sep. 2010.
[6] S. Saurabh and M. J. Kumar, “Impact of strain on drain current and
threshold voltage of nanoscale double gate tunnel field effect transis-
tor (TFET): Theoretical investigation and analysis,” Jpn. J. Appl. Phys.,
vol. 48, paper no. 064503, Jun. 2009.
[7] E.-H. Toh, G. H. Wang, G. Samudra, and Y. C. Yeo, “Device physics
and design of double-gate tunneling field-effect transistor by silicon film
thickness optimization,” Appl. Phys. Lett., vol. 90, pp. 263507-1– 263507-
3, 2007.
362 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 14, NO. 2, MARCH 2015

[8] Q. Shao, C. Zhao, C. Wu, J. Zhang, L. Zhang, and Z. Yu, “Compact model Rajat Vishnoi (S’10–GS’14) received the B.Tech.
and projection of silicon nanowire tunneling transistors (NW-tFETs),” in degree in electrical engineering from Indian Insti-
Proc. Int. Conf. Electr. Devices. Solid-State Circuits, 2013, pp. 1–2. tute of Technology Kanpur, Kanpur, India, in 2012.
[9] A. S. Verhulst, B. Sorée, D. Leonelli, W. G. Vandenberghe, and G. Groe- He is currently working toward the Ph.D. degree in
seneken, “Modeling the single-gate, double-gate, and gate-all-around tun- electrical engineering at the Indian Institute of Tech-
nel field-effect transistor,” J. Appl. Phys., vol. 107, pp. 024518-1–024518- nology Delhi, Delhi, India. His research interests in-
6, Jan. 2010. clude semiconductor device modeling, design, and
[10] M. Lee and W. Choi, “Analytical model of single-gate silicon-on-insulator fabrication.
tunneling field-effect transistors,” Solid State Electron., vol. 63, no. 1,
pp. 110–114, 2011.
[11] J. Wan, C. L. Royer, A. Zaslavsky, and S. Cristoloveanu, “A tunneling
field effect transistor model combining interband tunneling with channel
transport,” J. Appl. Phys., vol. 110, no. 10, pp. 104503-1–104503-7, 2011.
[12] R. Vishnoi and M. J. Kumar, “Compact analytical drain current model of Mamidala Jagadesh Kumar (M’95–SM’99) is cur-
gate-all-around nanowire tunneling FET,” IEEE Trans. Electron. Devices, rently the NXP (Philips) Chair Professor established
vol. 61, no. 7, pp. 2599–2603, Jul. 2014. at IIT Delhi by Philips Semiconductors, The Nether-
[13] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 32, pp. 83–91, lands. He is also a Principal Investigator of the Nano-
1961. scale Research Facility at Indian Institute of Technol-
[14] ATLAS Device Simulation Software, Santa Clara, CA, USA: Silvaco Int., ogy Delhi, Delhi, India. He is an Editor of the IEEE
2014. TRANSACTIONS ON ELECTRON DEVICES.

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