Superlattices and Microstructures 161 (2022) 107101

Contents lists available at ScienceDirect

Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Comprehensive review on electrical noise analysis of

TFET structures
Sweta Chander, Sanjeet Kumar Sinha *, Rekha Chaudhary
School of Electronics & Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

A R T I C L E I N F O A B S T R A C T

Keywords: Tunnel Filed Effect Transistors (TFETs) have appeared as an alternative for conventional CMOS
Tunneling due to their advantages like very low leakage current and steep sub-threshold slope. In semi­
Flicker noise conductor devices, noise is considered an undesired signal that can deteriorate the desired signal.
Shot noise
In TFET structures different noise sources affect the performance at different frequency ranges.
Thermal noise
Random telegraph noise
This paper presents a comprehensive review of impact of electrical noise on the performance of
various TFET structures. The impact of both low-frequency noise sources and high-frequency
sources have been discussed thoroughly. The study of different types of electrical noises occur
in simple TFET device and different structures of TFET is presented.

1. Introduction

Scaling down the device dimensions of metal–oxide–semiconductor field-effect transistor (MOSFET) has been very challenging due
to the short channel effects like high subthreshold slope, high leakage current, and threshold voltage roll-off, etc. [1,2].
Tunneling-field-effect-transistor (TFET) has appeared as a potential substitute to replace already existing MOSFET because of small
leakage current and steep Subthreshold Swing (SS) [3,4]. TFETs are a new class of devices in which the conduction mechanism is based
on Band-to-band tunneling (BTBT) [5–7]. The performance of miniaturized devices operating on low voltages are highly affected by
the electrical noise [8,9]. The low-frequency noises like flicker noise and burst noise become more vigorous as we scale down the
device dimensions, which degrades the performance of semiconductor memories [10–12] and analog circuits [13,14]. Also,
high-frequency noise sources like shot noise and thermal noise are detrimental toanalog/Radio-frequency (RF) applications [15].
The impact of noise on TFETs is less frequently reported than other electrical parameters. It is very necessary and challenging as
well, to understand the behaviour of TFET in the presence of noise. A very few works related to the modeling of the impact of low-
frequency noise and high-frequency noise on the performance of TFETs have been reported [16,17]. But extensive study of noise
effect on different TFET structures is yet to be done.
This paper provides a comprehensive review of effect of low-frequency and high-frequency noise on different types of TFET
structures, material engineering and bandgap engineering. In section 2, TFET’s basic operating principle is discussed. Section 3 deals
with the discussion of different types of electrical noise acting in TFET. The work related to the effect of noise on TFET device per­
formance is categorised based on the material used, is reported in section 4. Finally, the paper is concluded in the last section.

* Corresponding author.
E-mail address: sanjeetksinha@gmail.com (S.K. Sinha).

https://doi.org/10.1016/j.spmi.2021.107101
Received 14 September 2021; Accepted 27 November 2021
Available online 2 December 2021
0749-6036/© 2021 Elsevier Ltd. All rights reserved.
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

2. Tunnel field effect transistors

TFET works on the principle of quantum tunneling which states that if a particle does not have sufficient energy to cross a potential
barrier but still it tunnels through the barrier. This tunneling happens due to the wave nature of the particle. The compatibility of Si
with the complementary metal–oxide–semiconductor field-effect transistor (CMOS) fabrication processes makes it an easy choice for
TFET and a high-quality interface can be achieved between Si-channel and high-κ gate dielectric [18–20].
Fig. 1 shows the cross-sectional view of TFET, in which p-type silicon substrate of length Lch is taken. The source and drain regions
have lengths of Ls and Ld with heavily doped p-type and n-type materials. Also, gate oxide of thickness Tox is deposited over a p-type
silicon substrate. The source-channel and drain-channel junctions get reversed biased as a positive voltage is applied at the drain
terminal. When no voltage is applied at the gate terminal, no current flows through the channel. In TFETs, the off-current/leakage
current is very small that makes it an energy-efficient device. When a positive bias is applied at the gate terminal, it pushes the
conduction band down in the channel region. Thus, a tunneling path is formed between the source band and channel conduction
bands. In TFETs, the current flow due to the movement of valence electrons of the source into the channel region. These valence
electrons carry lower energy. So, the TFETs are thermally cooled systems [7].
The tunneling probability depends upon the height, width, shape of the potential barrier, and tunneling mass of charge carriers.
Kane’s approach and Wentzel-Kramers-Brillouin’s approach (WKB) approaches can be used to calculate the rate of BTB tunneling [21].
The rate of tunneling is given in Eq. (1) [22]:
−√4̅̅̅̅
̅
2mr Eg1.5 − E
(1)
┴
T = exp 3qħ exp E

where q = electron charge, F = average junction field, E┴=transverse component of total carrier energy, E = the impact of the
transverse-energy-state carriers on the tunneling magnitude.
qħF
E = √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (2)
2mr EBeff

Here mris the tunneling effect mass. A high electric field, small effective mass, and narrow bandgap reduce the effect on the
tunneling phenomena by the transverse states. The transmission probability can be increased by reducing the bandgap and in turn, it
improves the performance of TFET in the ON state. It is evident from the literature that smaller band-gap materials increase the drain
current but it also increases the leakage current. The energy band diagram of homojunction and heterojunction TFET is shown in Fig. 2.
In heterojunction TFET (HTFET), high ON current and low leakage current can be achieved. Low bandgap materials (Ge and InAs) are
used in source region to form a heterojunction with Si channel [23,24]. Using low bandgap material reduces the tunneling width and
improves the drain current. On the other hand, the III-V materials based staggered heterojunction TFET are suitable for low voltage
operation but under the trade-off between power consumption and performance [25].

Fig. 1. Cross-sectional view of TFET.

2
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

Fig. 2. Energy band diagram of homojunction and heterojunction TFETs [25,26].

3. Different types of noises in tunnel FETs

In semiconductor devices, a spontaneous fluctuation in current or in voltage is known as noise. The intensity of fluctuation depends
upon different factors like manufacturing process, type of device, and operating conditions, etc. [27,28]. Such fluctuations imitate the
presence of the many microscopic processes and influence the macroscopic quantities like voltages or currents. So, it is essential to
control the sources of the noise level in the electronic devices/circuits. Different types of noise from low-frequency to high-frequency
must be considered. Fig. 3 shows different types of electrical noise present in TFET device. Low-frequency noise can be further
classified into random telegraph noise (RTN)/burst noise and flicker noise, while high-frequency noise can be further classified into
shot noise and thermal noise.

3.1. Low-frequency noise sources

1. RTN and Flicker noise are the two types of noise sources that degrade the device’s performance operating at low-frequency. RTN is
also known as burst noise/popcorn noise/impulse noise/bi-stable noise. Flicker noise is also known as pink noise. The detailed
explanation of low-frequency noise sources is given in subsequent section.

3.1.1. Random telegraph noise

RTNalso known as burst noise, is a low-frequency noise that mainly occurs due to the presence of impurities in semiconductors and
thin gate-oxide films. The trapping and de-trapping of carriers in the channel are the source of RTN [29]. If the trap is located on the
source-channel interface, RTN is more pronounced. Because the trapped charge can change the junction electric field which in turn
affects BTBT. It has a power spectral density of 1/f2. RTN noise exists in the devices having a few carriers in which one trap center
captures one electron [30]. It is also present in the devices fabricated on the defected crystal lattice. RTN noise is a function of
temperature, radiation, and induced mechanical stress. In audio amplifiers, the burst noise sounds as random shots, which are similar
to the sound associated with making popcorn. The noise spectral density is given by RTN is given by Eq. (3) [24],:

4.(ΔI)2
SRTN (f ) = C (3)
1 + (2nf /fRTN )2

where,
1
C= 2
(4)
(τl + τh ).fRTN

Fig. 3. Different type of electrical noise.

3
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

1 1 1 τl + τh
fRTN = = + = (5)
τ τl τh τ l .τ h
fRTN is RTN noise corner frequency. τl andτh are the average time of low and high pulses respectively. The intensity of RTN noise
depends upon the site at which the trap center is located concerning the Fermi level and the center area of the Fermi level is responsible
for the generation of RTN noise.

3.1.2. Flicker noise

Flicker noise is a low-frequency noise that arises from the trapping and de-trapping of charge carriers in the trap states in the gate
oxide around the quasi-fermi level. It has the power spectral density of 1/f and it is also known as pink noise. This noise occurs in
semiconductor devices under biasing conditions. The magnitude of the noise decreases with frequency. It is mostly generated at the
interface of Si-substrate and gate oxide. At the interface of Si substrate, there exist dangling bonds. These dangling bonds give rise to
extra energy states. The charge carriers that move across these energy states, get trapped in these sites. Later on, these carriers are
released randomly, generating flicker noise. Flicker noise is generally related to material failures or fabrication imperfection.
Surface model/McWhorter model [31] and Bulk model/Hooge model [32] are the two models of flicker noise. In the basic concept
of surface model, it was assumed that:

• On the Si–SiO2 interface, there exist uniformly distributed trap centers due to the presence of dangling bonds on Si surface.
• The probability of penetration of carriers to trap centers decreases exponentially on moving away from the surface.
• The time constants of trap centers rise on moving away from the surface.

The noise spectral density is given by surface model is given by Eq. (6) [27],:
∫τ2
1 4τ 1
S1/f ∝ (ΔN)2 .dτ = (ΔN)2 . (6)
τ 1 + ωτ2 f
τ1

1 1
<< ω <<
τ2 τ1
The noise spectral density for surface model remains constant up to f2= 2πτ1 2 .
For the carrier transport, bulk model uses two scattering mechanisms of carriers. The first is; scattering on the silicon lattice and the
other is scattering on impurities. The source of flicker noise is scattering on the crystal lattice while scattering on the impurities does
not affect the noise level. All imperfections of the crystal lattice lead to large flicker noise.
The noise spectral density is given by bulk model is given by Eq. (7):
αH .I α
S1/f = (7)
f γ .N
Here, αH is the Hooge constant and α, γ are material constant [16].

3.2. High-frequency noise sources

Thermal noise and shot noise are the two types of noise sources that degrade the device’s performance operating at high-frequency.
For the analysis of thermal noise effect on TFET structure, the thermal noise model of MOSFET in ON-state is used, when the applied
drain-source voltage is zero [33]. Though, shot noise is the dominant form of high-frequency noise in heterojunction TFET [27]. The
modeling of shot noise can be done in the same way as it is done in tunnel diodes [34].

3.2.1. Shot noise

In electronic devices, the noise that arises due to the unavoidable random fluctuations of electric current when the charge carriers
travel a gap is known as shot noise [35]. When the electrons moving in a direction crosses a barrier, all the electrons may have different
arrival times. These discrete arrival times appear as shot noise. Shot noise exhibits since the current is not a continuous flow but it is the
sum of discrete pulses in time where each pulse corresponds to the transfer of electron through a conductor. Shot noise is caused by the
thermal motion of electrons and occurs in any conductor having resistance R. The noise spectral density of shot noise does not depend
on temperature and can be written as Eq. (8) [27],:
Sshot = 2qId (8)

where q is the electron charge and I is the forward junction current.

Shot noise can be modeled as given in Eq. (9) [27]:

i2shot = 2qId Γ (9)

In equation (9), Γ is Fano factor that indicates the deviation in the magnitude of shot noise from the nominal value ID . Fano factor

4
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

value depends upon applied voltage and it is frequency independent. A simple theoretical model was used to analyze the effect of high-
frequency noises in tunnel diode. It was assumed that current flowing one both directions were not correlated with each other and
current flowing in both directions is responsible for shot noise [35]. The noise analysis multiwalled carbon nano tube (MWCNT) TFET
states that the electrical properties of MWCNT TFET do not change up to 800 MHz [36].

3.2.2. Thermal noise

In electronic devices, the noise generated inside a conductor at equilibrium due to the thermal agitation of charge carriers is known
as thermal noise [15]. In 1928, Johnson experimentally verified the theory of the fluctuating movement of charges in thermal
equilibrium that was initially proposed by Einstein in 1905. The magnitude of random motion of free electrons and resistance of
elements increases with an increase in temperature. Due to this thermal motion of charge carriers, a fluctuating voltage is created at the
terminals of the conductor. Thermal noise is also described as Gaussian white noise because the power over the frequency spectrum is
uniform. The noise spectral density (Sth) of thermal noise is given by Eq. (10) [37],:
Sth = 4kTB (10)
Here, k = Boltzmann’s constant, T = Temperature, and B= Bandwidth of the frequency spectrum.
In HTFET, thermal noise model of on-state MOS is used, which is proportional to the channel conductance at zero drain-source bias
[16].

4. Noise in tunnel FETs devices

Initially, LF noise was studied for Si-based homojunction and heterojunction TFETs [24,38]. Later on, the analysis of noise was
carried out for III-V materials implementing different TFET structures [23,39]. Also, the electrical noise analysis especially the
low-frequency noise analysis of TFET structures has been done by many researchers from universities and electronic companies. But
the high-frequency analysis of TFET is yet to be explored a lot. In the past a few years, the research of various TFET structures has been
accelerated [40–42]. The brief review of impact of noise on various TFET structures using different materials is presented in this
section. Section A discuss the literature related to TFET structures using Si/Ge materials and TFET structures using III-V materials are
reported in section B. In section C, the different TFET structures are discussed while in section D, TFET based circuit and memory
design are reported.

4.1. Noise in Si/Ge tunnel FETs

At nanoscale, the low-frequency noise i.e. flicker noise becomes very problematic in case of fabricated device because flicker noise
increases the reducing the device dimensions. The measure of device quality and reliability can be done by checking the level of flicker
noise. In TFETs, the low-frequency noise obeys 1/f frequency dependence, in large channel TFETs the RTN is dominated and char­
acterised by slope of 1/f2 [43].
Huang et al. reported the experimental study of low-frequency noise effect on TFETs using different source junction designs. Due to
non-local BTBT mechanism in TFET, it is observed that those active traps are responsible for the noise which are located in the area
where the BTBT is generating electron-hole pair. The traps that located in the place where junction electric field is maximum, have
comparatively weak impact on the TFET noise [44].
Das et al. presented the analysis of low-frequency flicker noise on dual dielectric pocket having three different gate-source underlap
lengths and thicknesses. The proposed device exhibits a super steep slope and high current ratio. The study specifies that the ON
current of the reported HTFET structure is not affected by presence of interface traps as compared to the OFF current [45].

Fig. 4. (a)Fabricated TFET device (b)Steps followed for fabrication (c) ON current dependence on temperature [47].

5
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

The investigation of impact of high-frequency noise with single acceptor-type and donor-type interface trap induced RTN on TFET
was reported by Fan et al. Based on the results, it has been observed that near tunneling junction, RTN impact occurs for the acceptor-
type trap but the donor-type trap, the region is comparatively larger. It occurs between the tunneling junction and the middle of the
channel region. Also, the subthreshold characteristics can be improved by taking a larger channel length [46].
Chen et al. reported the amplitude of RTN on the characteristics of TFET experimentally. The study reveals that nonuniform
distribution of BTBT generation rate along device width direction is responsible for high-amplitude of RTN. As the device width
shrinks, it reduces the number of critical paths which results in higher amplitude RTN. Fig. 4 shows the fabricated TFET device and the
steps followed for fabrication. Also, the dependence of measured current on temperature and the results fits well with the theoretical
BTBT model. It has been analysed that high source doping concentration fluctuates the BTBT generation rate and reduces the RTN
amplitudes [47].
J. wan et al. reported modelling of low-frequency noise of TFET by taking HfO2 as gate dielectric material. Based on the noise
analysis, it has been found that unlike conventional MOS devices, TFET shows 1/f2 frequency dependence even for large gates. This
happens because the tunneling junction area determine the current is much smaller than physical gate lengths [48].
The analog performance parameters of SiGe nanowire with different source compositions were studied by Paula et al. The low-
frequency noise analysis for Si source and changing the mole fraction values of SiGe were performed. For Si source, the lowest
value of noise spectral density was obtained but Ge source leads to higher noise power spectral density. The noise spectral density
increases with temperature because of the thermal noise of the parasitic series resistance [49].
Vandooren et al. presented the electrical performance of vertical Si homo-junction and SiGe source hetero-junction TFETs.The
analysis of trap-assisted tunneling through simulations and characterization has been performed. The trap-assisted tunneling worsens
the onset characteristics and SS of the TFET. The simulation results of Ge TFET are in agreement with experimental data up to some
extent. The results demonstrated that SiGe TFET exhibits improved performance than Si TFET because of the lower bandgap [50].
Ghosh et al. presented the low-frequency noise analysis of flicker noise of TFET structure. A selective buried oxide (SELBOX) SiGe
layer has been used at the source channel junction in the presence of trap concentrations as shown in Fig. 5 (a). In the buried oxide
layer, a gap of 2 nm was considered to minimise the OFF current and various electrical parameters were investigated. For the gap
location near the source, least OFF current was obtained. Also, the current and voltage noise spectral density were considered to
observe the impact of uniform and Gaussian trap concentrations on the performance of TFET. It is clear from the analysis that on
increasing the gaussian trap concentration the device degradation is more as compared to uniform trap. SS increases with increase in
the trap concentration. As shown in Fig. 5 (b), it is clear that the presence of trap degrades both ON-OFF current ratio and SS. Thus, it
degrades the overall performance of the device. The proposed structure delivers low OFF current thus it can be used for low power
applications [51].
Goswami et al. proposed a new architecture of TFET with a circular gate. The electrical noise analysis was performed for both
structures; (a) proposed structure (circular gate), (b) HTFET as shown in Fig. 6. A comparative analysis for both the structures was done
also. The uniform and gaussian trap distributions were simulated and based on the simulation results it can be concluded that structure
‘a’ shows the lesser impact of noise than structure ‘b’. Flicker noise shows an intense effect at low-frequency and mid-frequency range.
While at high-frequency, diffusion noise effects. Nonetheless, the drain current in structure ‘a’ is more prone to traps than the drain
current in structure ‘b’. The cut-off frequency of structure can be improved by using gate-drain underlap and it is well-suited for digital
applications [52].

Fig. 5. (a)Proposed SELBOX structure (b) Effect of change in trap concentrations on ON-OFF current ratio and SS [51].

6
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

Fig. 6. 2-D structure of novel Circular gate TFET and HTFET [52].

4.2. Noise in III-V tunnel FETs

1. In the TFET device, during ON state, very low drive current/ON current flows from source to drain. The drive current can be
improved by using low bandgap materials like InGaAs, InAs. Fig. 7 shows the schematic diagram of homojunction and hetero­
junction TFET using III-V materials.

Bu et al. developed an analytical model to determine the variation of the electrostatic potential because of the presence of charged
trap in the gate oxide of the TFET device. A noise model based on the flow of current through tunneling of carriers in the channel has
been proposed. The power spectral density of the TFET device is presented that shows dependency on the frequency and applied gate
voltage. It is evident from the analysis that because of the tunneling the noise power spectral density is more affected by voltage
applied at gate terminal than the movement of traps through the channel. The noise observed in the channel is due to the variation in
the mobility of traps [53].
Pandey et al. reported RTN study analysis of HTFET using III-V materials with 20 nm long and 40 nm wide channels. The electrical
noise analysis of both low-frequency noise and high-frequency noise for HTFET was realized in a differential amplifier with a
capacitive load circuit as shown in Fig. 8. The impact of RTN noise based on the different locations of traps, gate and drain bias was
studied. RTN due to the presence of a single charge trap has been modeled by placing the trap charges to pre-defined coordinated mesh.
RTN has the maximum effect when trap is located inside the channel as it alters the electric field. As the drain voltage is increased, the
carrier concentration near the traps decreases and the RTN amplitude increases. On increasing the gate voltage, the relative RTN
amplitude reduces to 10–40% than Si-FinFET. At high-frequency, the normalised drain current noise reduces two times than Si-FinFET
due to dominance of shot noise [16].
Bijesh et al. presented low-frequency noise analysis of GaAsSb/InGaAs heterojunction TFET using III-V materials. In this work, a
high ON current has been achieved at the low drain to source voltage. The effect of flicker noise on drive current is lower in the case of
heterojunction TFET than in homojunction TFET structure. An analytical model to analyze the flicker noise characteristics for both the
TFET structure has been developed [54].
The high-frequency noise analysis was performed to improve the benchmarking parameters in the Junction less FET (JLFET) by
performing channel doping engineering. A shell-doped channel JLFET using In0.3Ga0.7As/GaAs material was proposed and to
improve the parameters, sub-gate doped layer and channel impurity concentration were added additionally. In the proposed structure,
the impurity concentration in the sub-gate layer, source, and drain region is the same. In the channel region, the electron mobility gets
enhanced because of the shell doping and hence increases the transconductance. Such a structure can be used for low noise amplifiers
[55].
The analysis of low-frequency noise of vertical III-V nanowire TFET as shown in Fig. 9, was analysed. The analysis states that
despite of different tunneling mechanisms both MOSFET and TFET show same noise formalism. For the proposed work, the gate oxide
was found dominant source of noise in TFET. Further, the device dimensions were carefully optimized so that the device performance
doesn’t get effected [56].
Elvedin et al. reported highly scaled vertical nanowire TFET using InAs/InxGa1-xAsySb1-y/GaSb materials. TCAD simulations were

Fig. 7. Homojunction and Heterojunction TFET using III-V materials.

7
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

Fig. 8. Representation of noise model implemented at transistor level [16].

Fig. 9. Schematic illustration of InGaAsSb TFET [56].

used to perform the noise analysis and effect of different types of defects were studied. The study reveals that bulk defects have large
impact on performance. Also, it has been found that trapping and de-trapping of electron in gate oxide decreases or increases the
current. The current in TFET is very sensitive to potential fluctuations [57].

4.3. Noise in different architecture

Neves et al. reported the effect of low-frequency noise on the behavior of vertical TFETs experimentally. Different compositions of
source with different thickness of gate-stack were considered. In the source, the presence of Ge leads to more oxide traps which in turn
increases the noise. Also, the thinner HfO2 of the gate-stack introduces fewer oxide traps. Based on the analysis results of various
parameters like transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, it can be
concluded that TFETs are promising candidates for analog applications. The noise behavior of both MOSFET and TFET were analysed
and compared. Also, the effect of temperature on the noise behavior of TFET was studied [58]. The proposed device structure is shown
in Fig. 10.
D. Das et al. presented the electrical noise analysis of a pocket doped hetero-stacked L-shaped gate silicon-on insulator (SOI) tunnel

8
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

Fig. 10. Schematic diagram of Ge heterojunction vertical TFET [58].

FET. As shown in Fig. 11, a hetero-stacked source with upper layer of Si and lower layer of Ge was used. The Ge layer provide enhanced
ON current and steeper slope. At high-frequency, diffusion noise dominates while at low-frequency generation-recombination noise
dominates [59].
The electrical noise analysis of different TFET structures like L-shaped, T-shaped and U-shaped has not been explored much.

4.4. TFET based circuit and memory design

In the processors, SRAM memory cell have been broadly used as data caches and these memory cells are the most significant digital
building blocks. Fan et al. widely reviewed the effect of single-trap-induced RTN on TFET. The effect of noise on BTBT dominated
current conduction in TFET and thermionic based current conduction has been presented in both device and circuit level. The trap
location has an intensive effect and that effect varies with applied bias variation and type of trap. The worst-case analysis of different
parameters for RTN noise has been investigated for TFET based 6T/8T SRAM cells [60]. For different trap locations A, B, C, A′ , B’ the
analysis of TFET device has been performed. Fig. 12 demonstrates the diagram of reverse-biased TFET with a single charge trap and
having asymmetric source and drain dopant concentrations.
Seyed et al. presented a new low-power TFET 8T-SRAM cell with an improved noise margin. The stability of the 8T-SRAM cell was
improved by using supply feedback. The proposed structure exhibits 33% in reading noise margin and 26% in write margin as
compared to conventional 6T SRAM cell for the supply voltage of 0.3 V. The area of the proposed SRAM is larger than the existing one
but the features like stability and high performance at very low voltage supply make it useful. The use of the TFET device has limited
the working of SRAM cells as it is a unidirectional device but this issue has been resolved by using transistors (n-type and p-type) placed
parallelly and the use of one bit-line [61].
Fan et al. investigated of the effect of RTN noise present in TFET-based 8T SRAM cell. To account the effect of negatively charged
trap, the atomistic 3D TCAD simulations were performed for the analysis of TFET-based SRAM. From the analysis, it has been observed
that if the trap is present near the tunneling junction, fluctuation in drain current has been observed. The RTN causes 16% additional
variation for 8T SRAM circuit configuration [62]. The electron current density profile for gate voltage values of 0V and 0.2 V has been
shown in Fig. 13. An increase in gate voltage increases the electron current density.
Luong et al. fabricated half SRAM (HSRAM) cells to examine the capability of TFETs for 6T-SRAM for the first time. This reported
structure has been strained with Si nanowire. The proposed TFET structure does not work up to the mark even when the ambipolar
behavior has not been included. Also, analysis of the proposed structure has restricted the static figure of merit [63].
Pandey et al. investigated the effect of a single charge trap RTN in HTFET-based SRAM. This study focused on the analysis of
Schmitt trigger mechanism-based variation tolerant 10T SRAM. It has been clear from the analysis that HTFET based SRAM cells show
very good performance even in the presence of RTN. For the applied voltage of 0.2 V, the proposed structure offers 15% more
improvement as compared to Si-FinFET [11,12].
The performance of MOSFET devices degrades on scaling down the dimensions. All the issues can be solved using TFET structures
as TFET devices offer low leakage current and steeper SS. Nonetheless, TFETs are ambipolar and produce low ON current. However,
this behavior can be overcome by using increasing the doping concentration. The main challenges in TFETs are to achieve high ON
current, low OFF current, and low average SS. By choosing an accurate predictive model, proper choice of materials, and dimensions of

9
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

Fig. 11. Hetero-stacked LTFET [59].

Fig. 12. Potential Contour by charge trap [60].

Fig. 13. TFET electron density profile for two different voltages [62].

the device, these challenges can be overcome.

5. Conclusion

In this paper, detailed review of impact of noise on TFET device performance has been presented. The authors have tried to present

10
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

the comprehensive review in manner where noise in Si/Ge, III-V materials, different shapes of TFET, and circuit and memory-based
designs are discussed. The review related to impact of high-frequency noise on simple TFET and different structures of TFET have not
been reported and can be explored in future.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to
influence the work reported in this paper.

Acknowledgements

This work is supported by DST-SERB, CRG grant, Govt. of India, CRG/2020/006229, dated: April 05, 2021.

References

[1] R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge, Near-threshold computing: reclaiming Moore’s law through energy efficient integrated
circuits, Proc. IEEE 98 (2) (2010) 253–266.
[2] S. Chander, P. Singh, S. Baishya, Optimization of direct tunneling gate leakage current in ultrathin gate oxide FET with High-K dielectrics, International Journal
of Recent Development in Engineering and Technology 1 (1) (2013) 24–30.
[3] S.O. Koswatta, M.S. Lundstrom, D.E. Nikonov, Performance comparison between p–i–n tunneling transistors and conventional MOSFETs, IEEE Trans. Electron.
Dev. 56 (2009) 456–465.
[4] W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron. Device
Lett. 28 (2007) 743–745.
[5] S. Banerjee, W. Richardson, J. Coleman, A. Chatterjee, A new three-terminal tunnel device, IEEE Electron. Device Lett. 8 (1987) 347–349.
[6] K.K. Bhuwalka, J. Schulze, I. Eisele, Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering, IEEE Trans. Electron.
Dev. 52 (2005) 909–917.
[7] S. Chander, B. Bhowmick, S. Baishya, Heterojunction fully depleted SOI-TFET with oxide/source overlap, Superlattice. Microst. 86 (2015) 43–50.
[8] G. Ghibaudo, T. Boutchacha, Electrical noise and RTS fluctuations in advanced CMOS devices, Microelectron. Reliab. 42 (4) (2002) 573–582.
[9] M.J. Knitel, P.H. Woerlee, A.J. Scholten, A. Zegers-Van Duijnhoven, Impact of process scaling on 1/f noise in advanced CMOS technologies, IEDM Tech. Dig.
(2000) 463–466.
[10] M. Agostinelli, J. Hicks, J. Xu, B. Woolery, K. Mistry, K. Zhang, et al., Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node, IEDM
Tech. Dig. (2005) 655–658.
[11] R. Pandey, V. Saripalli, J.P. Kulkarni, V. Narayanan, S. Datta, Impact of single trap random telegraph noise on heterojunction TFET SRAM stability, IEEE
Electron. Device Lett. 35 (3) (2014) 393–395.
[12] Z. Lin, L. Li, X. Wu, C. Peng, W. Lu, Q. Zhao, Half-select disturb-free 10T tunnel FET SRAM cell with improved noise margin and low power consumption, in:
IEEE Transactions on Circuits and Systems II, Express Briefs, 2021.
[13] K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, A physics-based MOSFET noise model for circuit simulators, IEEE Trans. Electron. Dev. 37 (5) (1990) 1323–1333.
[14] S. Datta, H. Liu, V. Narayanan, Tunnel FET technology: a reliability perspective, Microelectron. Reliab. 54 (2014) 861–874.
[15] H.F. Teng, S.L. Jang, M.H. Juang, A unified model for highfrequency current noise of MOSFETs, Solid State Electron. 47 (11) (2003) 2043–2048.
[16] R. Pandey, B. Rajamohanan, H. Liu, V. Narayanan, S. Datta, Electrical noise in heterojunction interband tunnel FETs, IEEE Trans. Electron. Dev. 61 (2014)
52–560.
[17] R. Bijesh, D.K. Mohata, H. Liu, S. Datta, Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs, Device Res. Conf.
Dig. (2012) 203–204.
[18] S. Chander, S.K. Sinha, S. Kumar, P.K. Singh, K. Baral, K. Singh, S. Jit, Temperature analysis of Ge/Si heterojunction SOI-tunnel FET, Superlattice. Microst. 110
(2017) 162–170.
[19] K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron. Dev. 54 (7) (2007) 1725–1733.
[20] L. Zhang, M. Chan, SPICE modeling of double-gate tunnel-FETs including channel transports, IEEE Trans. Electron. Dev. 61 (2) (2014) 300–307.
[21] E.O. Kane, Theory of tunneling, J. Appl. Phys. 32 (1) (1961) 83–91.
[22] A.C. Seabaugh, Q. Zhang, Low-voltage tunnel transistors for beyond CMOS logic, Proc. IEEE 98 (12) (2010) 2095–2110.
[23] S.G. Hu, Y. Liu, T.P. Chen, Z. Liu, M. Yang, Q. Yu, S. Fung, Effect of heat diffusion during state transitions in resistive switching memory device based on nickel-
rich nickel oxide film, IEEE Trans. Electron. Dev. 59 (5) (2012) 1558–1562.
[24] R. Dutta, T.D. Subash, N. Paitya, DC performance analysis of III–V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon FET
circuits with quantum mechanical effects, J. Comput. Electron. 20 (2) (2021) 855–863.
[25] T. Gonzalez, Introduction to special issue on noise modelling, J. Comput. Electron. 14 (1) (2015) 1–3.
[26] M.R. Tripathy, A.K. Singh, A. Samad, S. Chander, K. Baral, P.K. Singh, S. Jit, Device and circuit-level assessment of GaSb/Si Heterojunction vertical tunnel-FET
for low-power applications, IEEE Trans. Electron. Dev. 67 (3) (2020) 1285–1292.
[27] A. Konczakowska, B.M. Wilamowski, Noise in Semiconductor Devices, Fundamentals of Industrial ElectronicsCRC Press, 2018, 11-1.
[28] K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, Random telegraph noise of deep-submicrometer MOSFETs, IEEE Electron. Device Lett. 11 (2) (1990) 90–92.
[29] T.G.M. Kleinpenning, 1/f noise and random telegraph noise in very small electronic devices, Physica B 164 (1990) 331–334.
[30] A.L. McWhorter, in: R.H. Kingdton (Ed.), “1/f Noise and Germanium Surface Prosperities”, Semiconductor Surface Physics, University of Pennsylvania Press,
Philadelphia, PA, 1957, pp. 207–228.
[31] F.N. Hooge, 1/f noise is no surface effect, Phys. Lett. 29 (3) (1969) 139–140.
[32] R.P. Jindal, Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS, IEEE J. Solid State Circ. 22 (4) (1987) 512–521.
[33] J. Tiemann, Shot noise in tunnel diode amplifiers, Proc. IRE 48 (8) (1960) 1418–1423.
[34] B.E. Turner, Noise in the tunnel diode, Ph.D. dissertation, in: Dept. Electr. Current Rectifiers, Diodes, Electron., Univ. British Columbia, Vancouver, BC, Canada,
1962.
[35] N.V. Alkeev, S.V. Averin, A.A. Dorofeev, N.B. Gladysheva, M.Y. Torgashin, Shot noise of a high-speed resonance-tunneling diode based on the GaAs/AlAs
heterosystem, J. Commun. Technol. Electron. 57 (6) (2012) 634–641.
[36] F. Wu, T. Tsuneta, R. Tarkiainen, D. Gunnarsson, T.H. Wang, P.J. Hakonen, Shot noise of a multiwalled carbon nanotube field effect transistor, Phys. Rev. B 75
(12) (2007) 125419.
[37] N.E. Flowers-Jacobs, A. Pollarolo, K.J. Coakley, A.E. Fox, H. Rogalla, W.L. Tew, S.P. Benz, A Boltzmann constant determination based on Johnson noise
thermometry, Metrologia 54 (5) (2017) 730.
[38] V.K. Sharma, M. Pattanaik, B. Raj, PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits, Microelectron. Reliab. 54 (1) (2014) 90–99.
[39] C.Y. Chen, H. Ilatikhameneh, J.Z. Huang, G. Klimeck, M. Povolotskyi, Impact of body thickness and scattering on III–V triple heterojunction TFET modeled with
atomistic mode-space approximation, IEEE Trans. Electron. Dev. 67 (8) (2020) 3478–3485.

11
S. Chander et al. Superlattices and Microstructures 161 (2022) 107101

[40] V.P.H. Hu, H.H. Lin, Y.K. Lin, C. Hu, Optimization of negative-capacitance vertical-tunnel FET (NCVT-FET), IEEE Trans. Electron. Dev. 67 (6) (2020)
2593–2599.
[41] T. Joshi, Y. Singh, B. Singh, Extended-source double-gate tunnel FET with improved DC and analog/RF performance, IEEE Trans. Electron. Dev. 67 (4) (2020)
1873–1879.
[42] V.D. Wangkheirakpam, B. Bhowmick, P.D. Pukhrambam, Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the
presence of true noises, Appl. Phys. A 126 (10) (2020) 1–10.
[43] J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu, Low-frequency noise behavior of tunneling field effect transistors, Appl. Phys. Lett. 97 (24) (2010) 243503.
[44] Q. Huang, R. Huang, C. Chen, C. Wu, J. Wang, C. Wang, Y. Wang, Deep insights into low frequency noise behavior of tunnel FETs with source junction
engineering, in: Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, IEEE, 2014, pp. 1–2.
[45] D. Das, U. Chakraborty, A study on dual dielectric pocket heterojunction SOI tunnel FET performance and flicker noise analysis in presence of interface traps,
Siliconindia 13 (3) (2021) 1–12.
[46] M.L. Fan, V.P.H. Hu, Y.N. Chen, P. Su, C.T. Chuang, Analysis of single-trap-induced random telegraph noise and its interaction with work function variation for
tunnel FET, IEEE Trans. Electron. Dev. 60 (6) (2013) 2038–2044.
[47] C. Chen, Q. Huang, J. Zhu, Y. Zhao, L. Guo, R. Huang, New understanding of random telegraph noise amplitude in tunnel FETs, IEEE Trans. Electron. Dev. 64 (8)
(2017) 3324–3330.
[48] J. Wan, C. Le Royer, A. Zaslavsky, S.J.S.S.E. Cristoloveanu, Tunneling FETs on SOI: suppression of ambipolar leakage, low-frequency noise behavior, and
modelling, Solid State Electron. 65 (2011) 226–233.
[49] P.G. Agopian, M.D. Martino, S.D. Dos Santos, F.S. Neves, J.A. Martino, R. Rooyackers, A. Vandooren, E. Simoen, A.V. Thean, C. Claeys, Influence of the source
composition on the analog performance parameters of vertical nanowire-TFETs, IEEE Trans. Electron. Dev. 62 (1) (2014) 16–22.
[50] A. Vandooren, D. Leonelli, R. Rooyackers, A. Hikavyy, K. Devriendt, M. Demand, R. Loo, G. Groeseneken, C. Huyghebaert, Analysis of trap-assisted tunneling in
vertical Si homo-junction and SiGe hetero-junction tunnel-FETs, Solid State Electron. 83 (2013) 50–55.
[51] P. Ghosh, B. Bhowmick, Low-frequency noise analysis of heterojunction SELBOX TFET, Appl. Phys. A 124 (12) (2018) 1–9.
[52] R. Goswami, B. Bhowmick, S. Baishya, Electrical noise in circular gate tunnel FET in presence of interface traps, Superlattice. Microst. 86 (2015) 342–354.
[53] S.T. Bu, D.M. Huang, G.F. Jiao, H.Y. Yu, M.F. Li, Low frequency noise in tunneling field effect transistors, Solid State Electron. 137 (2017) 95–101.
[54] R. Bijesh, D.K. Mohata, H. Liu, S. Datta, Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs, Device Research
Conference IEEE (2012) 203–204.
[55] M. Fallahnejad, M. Vadizadeh, A. Salehi, A. Kashaniniya, F. Razaghian, Impact of channel doping engineering on the high-frequency noise performance of
junctionless In0.3Ga0.7As/GaAs FET: a numerical simulation study, Phys. E Low-dimens. Syst. Nanostruct. 115 (2020) 113715.
[56] M. Hellenbrand, E. Memišević, M. Berg, O.P. Kilpi, J. Svensson, L.E. Wernersson, Low-frequency noise in III–V nanowire TFETs and MOSFETs, IEEE Electron.
Device Lett. 38 (11) (2017) 1520–1523.
[57] E. Memisevic, M. Hellenbrand, E. Lind, A.R. Persson, S. Sant, A. Schenk, J. Svensson, R. Wallenberg, L.E. Wernersson, Individual defects in InAs/InGaAsSb/GaSb
nanowire tunnel field-effect transistors operating below 60 mV/decade, Nano Lett. 17 (7) (2017) 4373–4380.
[58] F.S. Neves, P.G. Agopian, J.A. Martino, B. Cretu, R. Rooyackers, A. Vandooren, E. Simoen, A.V.Y. Thean, C. Claeys, Low-frequency noise analysis and modeling
in vertical tunnel FETs with Ge source, IEEE Trans. Electron. Dev. 63 (4) (2016) 1658–1665.
[59] D. Das, S. Baishya, U. Chakraborty, Impact of temperature on RF characteristics and electrical noise analysis of an L-shaped gate tunnel FET with hetero-stacked
source configuration, Int. J. RF Microw. Computer-Aided Eng. 30 (9) (2020) e22310.
[60] M.L. Fan, S.Y. Yang, V.P.H. Hu, Y.N. Chen, P. Su, C.T. Chuang, Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM
and logic circuits, Microelectron. Reliab. 54 (4) (2014) 698–711.
[61] S.H. Fani, A. Peiravi, H. Farkhani, F. Moradi, A novel TFET 8T-SRAM cell with improved noise margin and stability, IEEE 21st International Symposium on
Design and Diagnostics of Electronic Circuits & Systems (2018) 39–44.
[62] M.L. Fan, V.P.H. Hu, Y.N. Chen, P. Su, C.T. Chuang, Investigation of single-trap-induced random telegraph noise for tunnel FET based devices, 8T SRAM cell,
and sense amplifiers, IEEE International Reliability Physics Symposium (2013) CR.1.1–CR.1.5, https://doi.org/10.1109/IRPS.2013.6532068.
[63] G.V. Luong, S. Strangio, A.T. Tiedemann, P. Bernardy, S. Trellenkamp, P. Palestri, S. Mantl, Q.T. Zhao, Experimental Characterization of the Static Noise
Margins of Strained Silicon Complementary Tunnel-FET SRAM, European Solid-State Device Research Conference IEEE, 2017, pp. 42–45.

12