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Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet - Volume 2 of 2
Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet - Volume 2 of 2
Celeron® Processors
Datasheet - Volume 2 of 2
February 2018
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2 Datasheet Volume 2 of 2
Contents
1 Introduction .......................................................................................................... 142
2 Host Bridge/DRAM Registers ................................................................................. 143
2.1 Device ID and Vendor ID Register (DEVICE_ID_VENDOR_ID_0_0_0_PCI) — Offset 0h ...
143
2.2 PCI Status and PCI Command Register (PCI_STATUS_COMMAND_0_0_0_PCI) — Offset
4h ................................................................................................................. 143
2.3 PCI Revision ID and PCI Class Code Register (REVISION_ID_CLASS_CODE_0_0_0_PCI)
— Offset 8h .................................................................................................... 144
2.4 Master Latency Timer and Header Type Register (MASTER_LATENCY_TIME_0_0_0_PCI)
— Offset Ch.................................................................................................... 144
2.5 System Agent Memory Mapped Range Base Address Register (SABAR) — Offset 10h 145
2.6 PCI Subsystem Vendor ID and PCI Subsystem ID (SVID_SID_0_0_0_PCI) — Offset 2Ch.
145
2.7 Capability Register Pointer (CAPPTR_0_0_0_PCI) — Offset 34h ............................. 145
2.8 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_LO_0_0_0_PCI) — Offset 48h............ 146
2.9 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_HI_0_0_0_PCI) — Offset 4Ch ............ 146
2.10 B-Unit Shadow of GGC (B_CR_GGC_0_0_0_PCI) — Offset 50h .............................. 147
2.11 B-Unit Shadow of the DEVEN Register (B_CR_DEVEN_0_0_0_PCI) — Offset 54h...... 148
2.12 Protected Audio Video Path Control (PAVPC_0_0_0_PCI) — Offset 58h ................... 148
2.13 B-Unit PCI Express Enhanced Configuration Range Base Address Low (B_CR_PCIEX-
BAR_LO_0_0_0_PCI) — Offset 60h .................................................................... 150
2.14 B-Unit PCI Express Enhanced Configuration Range Base Address High (B_CR_PCIEX-
BAR_HI_0_0_0_PCI) — Offset 64h .................................................................... 150
2.15 Message Signaled Interrupts Capability Identifier and Message Control (MSI_CAPID) —
Offset 90h ...................................................................................................... 151
2.16 Message Address (MA) — Offset 94h .................................................................. 151
2.17 Message Data (MD) — Offset 98h ...................................................................... 151
2.18 Error Status Register (ERRSTS) — Offset A0h...................................................... 152
2.19 Error Command Register (ERRCMD) — Offset A4h ............................................... 152
2.20 Top of Upper Usable DRAM Low (B_CR_TOUUD_LO_0_0_0_PCI) — Offset A8h ........ 152
2.21 Top of Upper Usable DRAM High (B_CR_TOUUD_HI_0_0_0_PCI) — Offset ACh ........ 153
2.22 Base of Data Stolen Memory (BDSM_0_0_0_PCI) — Offset B0h ............................. 153
2.23 Base of Graphics Stolen Memory (B_CR_BGSM_0_0_0_PCI) — Offset B4h .............. 154
2.24 B-Unit Copy of the TSEG Memory Base (B_CR_TSEGMB_0_0_0_PCI) — Offset B8h .. 154
2.25 Top of Lower Usable DRAM (B_CR_TOLUD_0_0_0_PCI) — Offset BCh .................... 155
2.26 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_LO_SHADOW_0_0_0_PCI) — Offset D0h...
155
2.27 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_HI_SHADOW_0_0_0_PCI) — Offset D4h ...
156
2.28 Message Data Register (MCRX) — Offset D8h...................................................... 156
2.29 Scratchpad (SKPD_0_0_0_PCI) — Offset DCh ..................................................... 157
2.30 Capability ID0 Capability Control (CAPID0_CAPCTRL0_0_0_0_PCI) — Offset E0h ..... 157
2.31 Capability ID0 A (B_CR_CAPID0_A_0_0_0_PCI) — Offset E4h ............................... 157
2.32 Capability ID0 B (B_CR_CAPID0_B_0_0_0_PCI) — Offset E8h ............................... 159
2.33 Design and Engineering Backup Register 0 (DEBUP0_0_0_0_PCI) — Offset F4h ....... 159
2.34 Design and Engineering Backup Register 1 (DEBUP1_0_0_0_PCI) — Offset FCh ....... 160
3 Host Memory Mapped Configuration Space (MCHBAR) Registers ........................... 161
3.1 DRAM Rank Population 0 (D_CR_DRP0) — Offset 1000h ....................................... 161
3.2 DRAM Timing Register 9A (D_CR_DTR9A) — Offset 1004h .................................... 163
3.3 DRAM Timing Register 0A (D_CR_DTR0A) — Offset 1008h .................................... 163
Datasheet Volume 2 of 2 3
3.4 DRAM Timing Register 1A (D_CR_DTR1A) — Offset 100Ch .................................... 164
3.5 DRAM Timing Register 2A (D_CR_DTR2A) — Offset 1010h..................................... 165
3.6 DRAM Timing Register 3A (D_CR_DTR3A) — Offset 1014h..................................... 165
3.7 DRAM Timing Register 4A (D_CR_DTR4A) — Offset 1018h..................................... 166
3.8 DRAM Timing Register 5A (D_CR_DTR5A) — Offset 101Ch .................................... 167
3.9 DRAM Timing Register 6A (D_CR_DTR6A) — Offset 1020h..................................... 168
3.10 DRAM Timing Register 7A (D_CR_DTR7A) — Offset 1024h..................................... 168
3.11 DRAM Timing Register 8A (D_CR_DTR8A) — Offset 1028h..................................... 169
3.12 D-Unit ODT Control Register A (D_CR_DOCRA) — Offset 102Ch ............................. 170
3.13 D-Unit Power Management Control 0 (D_CR_DPMC0) — Offset 1030h..................... 171
3.14 D-Unit Power Management Control 1 (D_CR_DPMC1) — Offset 1034h..................... 171
3.15 DRAM Refresh Control (D_CR_DRFC) — Offset 1038h ........................................... 173
3.16 D-Unit Scheduler Control (D_CR_DSCH) — Offset 103Ch....................................... 174
3.17 DRAM Calibration Control (D_CR_DCAL) — Offset 1040h ....................................... 176
3.18 DRAM Mode Registers Shadow Copy (D_CR_MR_SHADOW) — Offset 1048h ............ 176
3.19 VNN Scaling Timer Control (D_CR_VNNTIMER) — Offset 104Ch.............................. 177
3.20 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL) — Offset 1050h ..... 177
3.21 Temperature Offset Control (D_CR_TQOFFSET) — Offset 1054h............................. 178
3.22 D-Unit Control Operations (D_CR_DCO) — Offset 1058h ....................................... 179
3.23 Data Scrambler (D_CR_SCRAMCTRL) — Offset 10A4h........................................... 180
3.24 Error Injection Address Register (D_CR_ERR_INJ) — Offset 10ACh ......................... 180
3.25 Error Injection Control Register (D_CR_ERR_INJ_CTL) — Offset 10B0h ................... 181
3.26 Error Log Register (D_CR_ERR_ECC_LOG) — Offset 10B4h.................................... 181
3.27 D-Unit Fuse Status (D_CR_DFUSESTAT) — Offset 10BCh ...................................... 182
3.28 Major Mode Control (D_CR_MMC) — Offset 1124h................................................ 183
3.29 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB) — Offset 1128h.... 183
3.30 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD) — Offset 112Ch ... 184
3.31 Access Class Initial Priority (D_CR_ACCIP) — Offset 1130h.................................... 184
3.32 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0) — Offset 1134h......... 185
3.33 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1) — Offset 1138h......... 186
3.34 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2) — Offset 113Ch......... 186
3.35 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3) — Offset 1140h......... 187
3.36 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4) — Offset 1144h......... 187
3.37 Deadline Threshold (D_CR_DL_THRS) — Offset 1148h .......................................... 188
3.38 Major Mode Blocking Rules Control (D_CR_MM_BLK) — Offset 114Ch ..................... 188
3.39 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD) — Offset 1154h .................. 190
3.40 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL) — Offset 1180h................. 190
3.41 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE) — Offset 1184h ........................ 191
3.42 DRAM Rank Population 0 (D_CR_DRP0) — Offset 1200h........................................ 192
3.43 DRAM Timing Register 9A (D_CR_DTR9A) — Offset 1204h..................................... 194
3.44 DRAM Timing Register 0A (D_CR_DTR0A) — Offset 1208h..................................... 194
3.45 DRAM Timing Register 1A (D_CR_DTR1A) — Offset 120Ch .................................... 195
3.46 DRAM Timing Register 2A (D_CR_DTR2A) — Offset 1210h..................................... 196
3.47 DRAM Timing Register 3A (D_CR_DTR3A) — Offset 1214h..................................... 196
3.48 DRAM Timing Register 4A (D_CR_DTR4A) — Offset 1218h..................................... 197
3.49 DRAM Timing Register 5A (D_CR_DTR5A) — Offset 121Ch .................................... 198
3.50 DRAM Timing Register 6A (D_CR_DTR6A) — Offset 1220h..................................... 199
3.51 DRAM Timing Register 7A (D_CR_DTR7A) — Offset 1224h..................................... 199
3.52 DRAM Timing Register 8A (D_CR_DTR8A) — Offset 1228h..................................... 200
3.53 D-Unit ODT Control Register A (D_CR_DOCRA) — Offset 122Ch ............................. 201
3.54 D-Unit Power Management Control 0 (D_CR_DPMC0) — Offset 1230h..................... 202
3.55 D-Unit Power Management Control 1 (D_CR_DPMC1) — Offset 1234h..................... 202
3.56 DRAM Refresh Control (D_CR_DRFC) — Offset 1238h ........................................... 204
3.57 D-Unit Scheduler Control (D_CR_DSCH) — Offset 123Ch....................................... 205
3.58 DRAM Calibration Control (D_CR_DCAL) — Offset 1240h ....................................... 207
4 Datasheet Volume 2 of 2
3.59 DRAM Mode Registers Shadow Copy (D_CR_MR_SHADOW) — Offset 1248h ............ 207
3.60 VNN Scaling Timer Control (D_CR_VNNTIMER) — Offset 124Ch ............................. 208
3.61 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL) — Offset 1250h ..... 208
3.62 Temperature Offset Control (D_CR_TQOFFSET) — Offset 1254h ............................ 209
3.63 D-Unit Control Operations (D_CR_DCO) — Offset 1258h....................................... 210
3.64 Data Scrambler (D_CR_SCRAMCTRL) — Offset 12A4h .......................................... 211
3.65 Error Injection Address Register (D_CR_ERR_INJ) — Offset 12ACh ........................ 211
3.66 Error Injection Control Register (D_CR_ERR_INJ_CTL) — Offset 12B0h................... 212
3.67 Error Log Register (D_CR_ERR_ECC_LOG) — Offset 12B4h ................................... 212
3.68 D-Unit Fuse Status (D_CR_DFUSESTAT) — Offset 12BCh ...................................... 213
3.69 Major Mode Control (D_CR_MMC) — Offset 1324h ............................................... 214
3.70 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB) — Offset 1328h ... 214
3.71 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD) — Offset 132Ch... 215
3.72 Access Class Initial Priority (D_CR_ACCIP) — Offset 1330h ................................... 215
3.73 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0) — Offset 1334h ........ 216
3.74 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1) — Offset 1338h ........ 217
3.75 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2) — Offset 133Ch ........ 217
3.76 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3) — Offset 1340h ........ 218
3.77 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4) — Offset 1344h ........ 218
3.78 Deadline Threshold (D_CR_DL_THRS) — Offset 1348h ......................................... 219
3.79 Major Mode Blocking Rules Control (D_CR_MM_BLK) — Offset 134Ch ..................... 219
3.80 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD) — Offset 1354h .................. 221
3.81 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL) — Offset 1380h ................ 221
3.82 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE) — Offset 1384h ....................... 222
3.83 DRAM Rank Population 0 (D_CR_DRP0) — Offset 1400h ....................................... 223
3.84 DRAM Timing Register 9A (D_CR_DTR9A) — Offset 1404h .................................... 225
3.85 DRAM Timing Register 0A (D_CR_DTR0A) — Offset 1408h .................................... 225
3.86 DRAM Timing Register 1A (D_CR_DTR1A) — Offset 140Ch .................................... 226
3.87 DRAM Timing Register 2A (D_CR_DTR2A) — Offset 1410h .................................... 227
3.88 DRAM Timing Register 3A (D_CR_DTR3A) — Offset 1414h .................................... 227
3.89 DRAM Timing Register 4A (D_CR_DTR4A) — Offset 1418h .................................... 228
3.90 DRAM Timing Register 5A (D_CR_DTR5A) — Offset 141Ch .................................... 229
3.91 DRAM Timing Register 6A (D_CR_DTR6A) — Offset 1420h .................................... 230
3.92 DRAM Timing Register 7A (D_CR_DTR7A) — Offset 1424h .................................... 230
3.93 DRAM Timing Register 8A (D_CR_DTR8A) — Offset 1428h .................................... 231
3.94 D-Unit ODT Control Register A (D_CR_DOCRA) — Offset 142Ch............................. 232
3.95 D-Unit Power Management Control 0 (D_CR_DPMC0) — Offset 1430h .................... 233
3.96 D-Unit Power Management Control 1 (D_CR_DPMC1) — Offset 1434h .................... 233
3.97 DRAM Refresh Control (D_CR_DRFC) — Offset 1438h........................................... 235
3.98 D-Unit Scheduler Control (D_CR_DSCH) — Offset 143Ch ...................................... 236
3.99 DRAM Calibration Control (D_CR_DCAL) — Offset 1440h ...................................... 238
3.100 DRAM Mode Registers Shadow Copy (D_CR_MR_SHADOW) — Offset 1448h ............ 238
3.101 VNN Scaling Timer Control (D_CR_VNNTIMER) — Offset 144Ch ............................. 239
3.102 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL) — Offset 1450h ..... 239
3.103 Temperature Offset Control (D_CR_TQOFFSET) — Offset 1454h ............................ 240
3.104 D-Unit Control Operations (D_CR_DCO) — Offset 1458h....................................... 241
3.105 Data Scrambler (D_CR_SCRAMCTRL) — Offset 14A4h .......................................... 242
3.106 Error Injection Address Register (D_CR_ERR_INJ) — Offset 14ACh ........................ 242
3.107 Error Injection Control Register (D_CR_ERR_INJ_CTL) — Offset 14B0h................... 243
3.108 Error Log Register (D_CR_ERR_ECC_LOG) — Offset 14B4h ................................... 243
3.109 D-Unit Fuse Status (D_CR_DFUSESTAT) — Offset 14BCh ...................................... 244
3.110 Major Mode Control (D_CR_MMC) — Offset 1524h ............................................... 245
3.111 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB) — Offset 1528h ... 245
3.112 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD) — Offset 152Ch... 246
3.113 Access Class Initial Priority (D_CR_ACCIP) — Offset 1530h ................................... 246
Datasheet Volume 2 of 2 5
3.114 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0) — Offset 1534h......... 247
3.115 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1) — Offset 1538h......... 248
3.116 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2) — Offset 153Ch......... 248
3.117 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3) — Offset 1540h......... 249
3.118 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4) — Offset 1544h......... 249
3.119 Deadline Threshold (D_CR_DL_THRS) — Offset 1548h .......................................... 250
3.120 Major Mode Blocking Rules Control (D_CR_MM_BLK) — Offset 154Ch ..................... 250
3.121 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD) — Offset 1554h .................. 252
3.122 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL) — Offset 1580h................. 252
3.123 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE) — Offset 1584h ........................ 253
3.124 DRAM Rank Population 0 (D_CR_DRP0) — Offset 1600h........................................ 254
3.125 DRAM Timing Register 9A (D_CR_DTR9A) — Offset 1604h..................................... 256
3.126 DRAM Timing Register 0A (D_CR_DTR0A) — Offset 1608h..................................... 256
3.127 DRAM Timing Register 1A (D_CR_DTR1A) — Offset 160Ch .................................... 257
3.128 DRAM Timing Register 2A (D_CR_DTR2A) — Offset 1610h..................................... 258
3.129 DRAM Timing Register 3A (D_CR_DTR3A) — Offset 1614h..................................... 258
3.130 DRAM Timing Register 4A (D_CR_DTR4A) — Offset 1618h..................................... 259
3.131 DRAM Timing Register 5A (D_CR_DTR5A) — Offset 161Ch .................................... 260
3.132 DRAM Timing Register 6A (D_CR_DTR6A) — Offset 1620h..................................... 261
3.133 DRAM Timing Register 7A (D_CR_DTR7A) — Offset 1624h..................................... 261
3.134 DRAM Timing Register 8A (D_CR_DTR8A) — Offset 1628h..................................... 262
3.135 D-Unit ODT Control Register A (D_CR_DOCRA) — Offset 162Ch ............................. 263
3.136 D-Unit Power Management Control 0 (D_CR_DPMC0) — Offset 1630h..................... 264
3.137 D-Unit Power Management Control 1 (D_CR_DPMC1) — Offset 1634h..................... 264
3.138 DRAM Refresh Control (D_CR_DRFC) — Offset 1638h ........................................... 266
3.139 D-Unit Scheduler Control (D_CR_DSCH) — Offset 163Ch....................................... 267
3.140 DRAM Calibration Control (D_CR_DCAL) — Offset 1640h ....................................... 269
3.141 DRAM Mode Registers Shadow Copy (D_CR_MR_SHADOW) — Offset 1648h ............ 269
3.142 VNN Scaling Timer Control (D_CR_VNNTIMER) — Offset 164Ch.............................. 270
3.143 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL) — Offset 1650h ..... 270
3.144 Temperature Offset Control (D_CR_TQOFFSET) — Offset 1654h............................. 271
3.145 D-Unit Control Operations (D_CR_DCO) — Offset 1658h ....................................... 272
3.146 Data Scrambler (D_CR_SCRAMCTRL) — Offset 16A4h........................................... 273
3.147 Error Injection Address Register (D_CR_ERR_INJ) — Offset 16ACh ......................... 273
3.148 Error Injection Control Register (D_CR_ERR_INJ_CTL) — Offset 16B0h ................... 274
3.149 Error Log Register (D_CR_ERR_ECC_LOG) — Offset 16B4h.................................... 274
3.150 D-Unit Fuse Status (D_CR_DFUSESTAT) — Offset 16BCh ...................................... 275
3.151 Major Mode Control (D_CR_MMC) — Offset 1724h................................................ 276
3.152 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB) — Offset 1728h.... 276
3.153 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD) — Offset 172Ch ... 277
3.154 Access Class Initial Priority (D_CR_ACCIP) — Offset 1730h.................................... 277
3.155 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0) — Offset 1734h......... 278
3.156 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1) — Offset 1738h......... 279
3.157 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2) — Offset 173Ch......... 279
3.158 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3) — Offset 1740h......... 280
3.159 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4) — Offset 1744h......... 280
3.160 Deadline Threshold (D_CR_DL_THRS) — Offset 1748h .......................................... 281
3.161 Major Mode Blocking Rules Control (D_CR_MM_BLK) — Offset 174Ch ..................... 281
3.162 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD) — Offset 1754h .................. 283
3.163 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL) — Offset 1780h................. 283
3.164 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE) — Offset 1784h ........................ 284
3.165 DRAM Rank Population 0 (D_CR_DRP0) — Offset 1A00h ....................................... 285
3.166 DRAM Timing Register 9A (D_CR_DTR9A) — Offset 1A04h .................................... 287
3.167 DRAM Timing Register 0A (D_CR_DTR0A) — Offset 1A08h .................................... 287
3.168 DRAM Timing Register 1A (D_CR_DTR1A) — Offset 1A0Ch .................................... 288
6 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 7
set 6058h ....................................................................................................... 320
3.217 BIOS/PMC WR Write Access Control (C_CR_BIOS_PMC_WR_WAC_0_0_0_MCHBAR) —
Offset 6060h ................................................................................................... 320
3.218 P_U_PMC_CODEWR_ALLRD Control Policy (C_CR_P_U_PMC_CODEWR_ALL-
RD_CP_0_0_0_MCHBAR) — Offset 6070h ........................................................... 320
3.219 P_U_PMC_CODEWR_ALLRD Read Access Control Policy (C_CR_P_U_PMC_CODEWR_ALL-
RD_RAC_0_0_0_MCHBAR) — Offset 6078h ......................................................... 321
3.220 P_U_PMC_CODEWR_ALLRD Write Access Control Policy (C_CR_P_U_PMC_CODEWR_ALL-
RD_WAC_0_0_0_MCHBAR) — Offset 6080h ........................................................ 321
3.221 Upstream Device Arbiter Grant Count A2T (A_CR_UPARB_GCNT_DEV_A2T_MCHBAR) —
Offset 6400h ................................................................................................... 321
3.222 Upstream A2B Arbiter Channel 0 Grant Count (A_CR_UPARB_GCNT_A2B_0_MCHBAR) —
Offset 6404h ................................................................................................... 322
3.223 Upstream A2B Arbiter Channel 1 Grant Count (A_CR_UPARB_GCNT_A2B_1_MCHBAR) —
Offset 6408h ................................................................................................... 323
3.224 Upstream A2B Arbiter Channel 2 Grant Count (A_CR_UPARB_GCNT_A2B_2_MCHBAR) —
Offset 640Ch................................................................................................... 323
3.225 Upstream A2B Arbiter Channel 3 Grant Count (A_CR_UPARB_GCNT_A2B_3_MCHBAR) —
Offset 6410h ................................................................................................... 324
3.226 Upstream A2B Arbiter Channel 4 Grant Count (A_CR_UPARB_GCNT_A2B_4_MCHBAR) —
Offset 6414h ................................................................................................... 325
3.227 Upstream A2B Arbiter Channel 5 Grant Count (A_CR_UPARB_GCNT_A2B_5_MCHBAR) —
Offset 6418h ................................................................................................... 325
3.228 Upstream A2B Arbiter Channel 6 Grant Count (A_CR_UPARB_GCNT_A2B_6_MCHBAR) —
Offset 641Ch................................................................................................... 326
3.229 Upstream A2B Arbiter Channel 7 Grant Count (A_CR_UPARB_GCNT_A2B_7_MCHBAR) —
Offset 6420h ................................................................................................... 326
3.230 Upstream A2T Arbiter Channel 0 Grant Count (A_CR_UPARB_GCNT_A2T_0_MCHBAR) —
Offset 6424h ................................................................................................... 327
3.231 Upstream P2P Arbiter Channel 0 Grant Count (A_CR_UPARB_GCNT_P2P_0_MCHBAR) —
Offset 6428h ................................................................................................... 328
3.232 Upstream P2P Arbiter Channel 1 Grant Count (A_CR_UPARB_GCNT_P2P_1_MCHBAR) —
Offset 642Ch................................................................................................... 328
3.233 Upstream Private Credit Return Grant Count Posted 0 (A_CR_CRDAR-
B_PRIV_GCNT_DEV_P_0_MCHBAR) — Offset 6430h ............................................. 329
3.234 Upstream Private Credit Return Grant Count Posted 1 (A_CR_CRDAR-
B_PRIV_GCNT_DEV_P_1_MCHBAR) — Offset 6434h ............................................. 329
3.235 Upstream Private Credit Return Grant Count Non-posted 0 (A_CR_CRDAR-
B_PRIV_GCNT_DEV_N_0_MCHBAR) — Offset 6438h............................................. 330
3.236 Upstream Private Credit Return Grant Count Posted 1 (A_CR_CRDAR-
B_PRIV_GCNT_DEV_N_1_MCHBAR) — Offset 643Ch ............................................ 331
3.237 Upstream Private Credit Return Grant Count Completion (A_CR_CRDAR-
B_PRIV_GCNT_DEV_C_0_MCHBAR) — Offset 6440h............................................. 331
3.238 Upstream Shared Credit Return Grant Count Posted 0 (A_CR_CRDAR-
B_SHRD_GCNT_DEV_P_0_MCHBAR) — Offset 6444h............................................ 332
3.239 Upstream Shared Credit Return Grant Count Posted 1 (A_CR_CRDAR-
B_SHRD_GCNT_DEV_P_1_MCHBAR) — Offset 6448h............................................ 333
3.240 Upstream Shared Credit Return Grant Count Non-posted 0 (A_CR_CRDAR-
B_SHRD_GCNT_DEV_N_0_MCHBAR) — Offset 644Ch ........................................... 333
3.241 Upstream Shared Credit Return Grant Count Posted 1 (A_CR_CRDAR-
B_SHRD_GCNT_DEV_N_1_MCHBAR) — Offset 6450h ........................................... 334
3.242 Upstream Shared Credit Return Grant Count Completion (A_CR_CRDAR-
B_SHRD_GCNT_DEV_C_0_MCHBAR) — Offset 6454h ........................................... 334
3.243 Upstream Credit Arbiter Private Credit Return Class Arbiter Grant Count (A_CR_CRDAR-
B_PRIV_GCNT_CLS_MCHBAR) — Offset 6458h .................................................... 335
3.244 Upstream Credit Arbiter Shared Cedit Return Class Arbiter Grant Count (A_CR_CRDAR-
B_SHRD_GCNT_CLS_MCHBAR) — Offset 645Ch ................................................... 336
8 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 9
353
3.277 Slice and Channel Hash (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR) — Offset
65C0h ............................................................................................................ 354
3.278 Mirror Range Register (A_CR_MIRROR_RANGE_0_0_0_MCHBAR) — Offset 65C8h .... 356
3.279 ASYM MEM REGION 0 CONFIGURATION WITH NO INTERLEAVING (A_CR_ASYM_MEM_RE-
GION0_0_0_0_MCHBAR) — Offset 65D0h ........................................................... 357
3.280 ASYM MEM REGION 1 CONFIGURATION WITH NO INTERLEAVING (A_CR_ASYM_MEM_RE-
GION1_0_0_0_MCHBAR) — Offset 65D4h ........................................................... 357
3.281 Two-Way Asymmetric Memory Region Configuration (A_CR_ASYM_2WAY_MEM_RE-
GION_0_0_0_MCHBAR) — Offset 65D8h ............................................................. 358
3.282 B-Unit Miscellaneous Configuration (B_CR_BMISC_0_0_0_MCHBAR) — Offset 6800h 359
3.283 Security Control Policy (B_CR_SECURITY_CP_0_0_0_MCHBAR) — Offset 6808h ....... 359
3.284 Security Group Read Access Policy (B_CR_SECURITY_RAC_0_0_0_MCHBAR) — Offset
6810h ............................................................................................................ 363
3.285 Security Group Write Access Policy (B_CR_SECURITY_WAC_0_0_0_MCHBAR) — Offset
6818h ............................................................................................................ 367
3.286 Slice 0 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE0) — Offset 6868h ...
371
3.287 Slice 1 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE1) — Offset 686Ch ...
371
3.288 IMR0 Base (B_CR_BIMR0BASE_0_0_0_MCHBAR) — Offset 6870h .......................... 371
3.289 IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR) — Offset 6874h ......................... 372
3.290 IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR) — Offset 6878h.................. 372
3.291 IMR0 Read Access Policy (B_CR_BIMR0RAC_0_0_0_MCHBAR) — Offset 6880h ........ 376
3.292 IMR0 Write Access Policy (B_CR_BIMR0WAC_0_0_0_MCHBAR) — Offset 6888h ....... 380
3.293 IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR) — Offset 6890h .......................... 384
3.294 IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR) — Offset 6894h ......................... 384
3.295 IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR) — Offset 6898h.................. 385
3.296 IMR1 Read Access Policy (B_CR_BIMR1RAC_0_0_0_MCHBAR) — Offset 68A0h ........ 389
3.297 IMR1 Write Access Policy (B_CR_BIMR1WAC_0_0_0_MCHBAR) — Offset 68A8h ....... 392
3.298 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR) — Offset 68B0h .......................... 396
3.299 IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR) — Offset 68B4h ......................... 397
3.300 IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR) — Offset 68B8h.................. 397
3.301 IMR2 Read Access Policy (B_CR_BIMR2RAC_0_0_0_MCHBAR) — Offset 68C0h ........ 401
3.302 IMR2 Write Access Policy (B_CR_BIMR2WAC_0_0_0_MCHBAR) — Offset 68C8h ....... 405
3.303 IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR) — Offset 68D0h .......................... 408
3.304 IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR) — Offset 68D4h ......................... 409
3.305 IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR) — Offset 68D8h ................. 410
3.306 IMR3 Read Access Policy (B_CR_BIMR3RAC_0_0_0_MCHBAR) — Offset 68E0h......... 413
3.307 IMR3 Write Access Policy (B_CR_BIMR3WAC_0_0_0_MCHBAR) — Offset 68E8h ....... 417
3.308 IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR) — Offset 68F0h .......................... 421
3.309 IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR) — Offset 68F4h ......................... 421
3.310 IMR4 Control Policy (B_CR_BIMR4CP_0_0_0_MCHBAR) — Offset 68F8h .................. 422
3.311 IMR4 Read Access Policy (B_CR_BIMR4RAC_0_0_0_MCHBAR) — Offset 6900h ........ 426
3.312 IMR4 Write Access Policy (B_CR_BIMR4WAC_0_0_0_MCHBAR) — Offset 6908h ....... 430
3.313 IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR) — Offset 6910h .......................... 433
3.314 IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR) — Offset 6914h ......................... 434
3.315 IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR) — Offset 6918h.................. 435
3.316 IMR5 Read Access Policy (B_CR_BIMR5RAC_0_0_0_MCHBAR) — Offset 6920h ........ 438
3.317 IMR5 Write Access Policy (B_CR_BIMR5WAC_0_0_0_MCHBAR) — Offset 6928h ....... 442
3.318 IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR) — Offset 6930h .......................... 446
3.319 IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR) — Offset 6934h ......................... 446
3.320 IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR) — Offset 6938h.................. 447
3.321 IMR6 Read Access Policy (B_CR_BIMR6RAC_0_0_0_MCHBAR) — Offset 6940h ........ 451
3.322 IMR6 Write Access Policy (B_CR_BIMR6WAC_0_0_0_MCHBAR) — Offset 6948h ....... 455
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Datasheet Volume 2 of 2 11
3.378 IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR) — Offset 6AB0h ...................... 596
3.379 IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR) — Offset 6AB4h ..................... 596
3.380 IMR18 Control Policy (B_CR_BIMR18CP_0_0_0_MCHBAR) — Offset 6AB8h .............. 597
3.381 IMR18 Read Access Policy (B_CR_BIMR18RAC_0_0_0_MCHBAR) — Offset 6AC0h..... 601
3.382 IMR18 Write Access Policy (B_CR_BIMR18WAC_0_0_0_MCHBAR) — Offset 6AC8h ... 605
3.383 IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR) — Offset 6AD0h ...................... 608
3.384 IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR) — Offset 6AD4h ..................... 609
3.385 IMR19 Control Policy (B_CR_BIMR19CP_0_0_0_MCHBAR) — Offset 6AD8h.............. 610
3.386 IMR19 Read Access Policy (B_CR_BIMR19RAC_0_0_0_MCHBAR) — Offset 6AE0h ..... 613
3.387 IMR19 Write Access Policy (B_CR_BIMR19WAC_0_0_0_MCHBAR) — Offset 6AE8h.... 617
3.388 MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR) — Offset 6AF0h............... 621
3.389 MOT Out Mask (B_CR_MOT_OUT_MASK_0_0_0_MCHBAR) — Offset 6AF4h.............. 621
3.390 MOT Buffer Control Policy (B_CR_BMOT_BUF_CP_0_0_0_MCHBAR) — Offset 6AF8h . 622
3.391 MOT Buffer Read Access Policy (B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR) — Offset 6B00h
626
3.392 MOT Buffer Write Access Policy (B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR) — Offset
6B08h ............................................................................................................ 630
3.393 IMR Global BM Control Policy (B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR) — Offset
6B10h ............................................................................................................ 633
3.394 IMR Global BM Read Access Control (B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR) —
Offset 6B18h................................................................................................... 637
3.395 IMR Global BM Write Access Policy (B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR) —
Offset 6B20h................................................................................................... 637
3.396 Graphics Stolen Memory Control Policy (B_CR_BGSMCP_0_0_0_MCHBAR) — Offset
6B28h ............................................................................................................ 641
3.397 GSM Read Access Policy (B_CR_BGSMRAC_0_0_0_MCHBAR) — Offset 6B30h .......... 645
3.398 GSM Write Access Policy (B_CR_BGSMWAC_0_0_0_MCHBAR) — Offset 6B38h......... 649
3.399 TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR) — Offset 6B40h..................... 652
3.400 TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR) — Offset 6B48h ................... 656
3.401 BGSM Control Register (B_CR_BGSM_CTRL_0_0_0_MCHBAR) — Offset 6B50h......... 656
3.402 SMM Control Register (B_CR_BSMR_CTRL_0_0_0_MCHBAR) — Offset 6B54h........... 657
3.403 Default VTd Control Register (B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR) — Offset
6B58h ............................................................................................................ 658
3.404 MOT Trigger Trace Control (B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR) — Offset
6B7Ch............................................................................................................ 658
3.405 MOT Slice 0 Memory Pointer (B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR) — Offset
6B80h ............................................................................................................ 660
3.406 MOT Slice 1 Memory Pointer (B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR) — Offset
6B88h ............................................................................................................ 660
3.407 MOT Slice 0 Record ID (B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR) — Offset
6B90h ............................................................................................................ 661
3.408 MOT Slice 1 Record ID (B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR) — Offset
6B94h ............................................................................................................ 661
3.409 MOT Filter Match 0 (B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR) — Offset 6BA0h 662
3.410 MOT Filter Mask (B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR) — Offset 6BA8h ...... 662
3.411 MOT Filter Match 1 (B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR) — Offset 6BB0h 663
3.412 MOT Filter Mask 1 (B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR) — Offset 6BB8h ... 663
3.413 MOT Filter Misc 0 (B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR) — Offset 6BC0h ..... 664
3.414 MOT Filter Misc 1 (B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR) — Offset 6BC8h ..... 664
3.415 MOT Trigger Match 0 (B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR) — Offset 6BD0h
665
3.416 MOT Trigger Mask 0 (B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR) — Offset 6BD8h ..
665
3.417 MOT Trigger Match 1 (B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR) — Offset 6BE0h
666
3.418 MOT Trigger Mask 1 (B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR) — Offset 6BE8h ..
12 Datasheet Volume 2 of 2
666
3.419 MOT Trigger Misc 0 (B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR) — Offset 6BF0h667
3.420 MOT Trigger Misc 1 (B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR) — Offset 6BF8h667
3.421 MOT PSMI Sync (B_CR_MOT_PSMI_SYNC_0_0_0_MCHBAR) — Offset 6C00h........... 668
3.422 B_CR_BIOSWR_CP (B_CR_BIOSWR_CP_0_0_0_MCHBAR) — Offset 6C08h ............. 668
3.423 BIOSWR Read Access Policy (B_CR_BIOSWR_RAC_0_0_0_MCHBAR) — Offset 6C10h672
3.424 B_CR_BIOSWR_WAC (B_CR_BIOSWR_WAC_0_0_0_MCHBAR) — Offset 6C18h........ 675
3.425 Destination Override for BIOS1 region (B_CR_BIOS1_DECODE_OVERRIDE_0_0_0_MCH-
BAR) — Offset 6C20h....................................................................................... 678
3.426 TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR) — Offset 6C24h ................. 679
3.427 B-Unit Pcode/Ucode Write, All Read Control Policy Register (B_CR_P_U_CODEWR_ALL-
RD_CP_0_0_0_MCHBAR) — Offset 6C28h........................................................... 679
3.428 B-Unit Pcode/Ucode Read Access Policy (B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCH-
BAR) — Offset 6C30h....................................................................................... 684
3.429 B-Unit Pcode/Ucode Write Access Policy (B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_M-
CHBAR) — Offset 6C38h................................................................................... 688
3.430 Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR) — Offset 6C80h ................. 693
3.431 Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR) — Offset 6C88h ...................... 694
3.432 B-Unit Lites Group 0 Control (B_CR_LITES0_CTL_0_0_0_MCHBAR) — Offset 6C90h . 694
3.433 B-Unit Lites Group 0 Opcode Match Filter (B_CR_LITES0_OPCODE_MATCH_0_0_0_MCH-
BAR) — Offset 6C94h....................................................................................... 696
3.434 B-Unit Lites Group 0 Agent Match Filter (B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)
— Offset 6C98h .............................................................................................. 697
3.435 B-Unit Lites Group 0 U2C IntData Match Filter (B_CR_LITES0_U2CINTDATA_-
MATCH_0_0_0_MCHBAR) — Offset 6C9Ch .......................................................... 698
3.436 B-Unit Lites Group 0 Address Match Filter LITES0_ADDR_MATCH (B_CR_LITES0_ADDR_-
MATCH_0_0_0_MCHBAR) — Offset 6CA0h .......................................................... 698
3.437 B-Unit Lites Group 0 Address Mask Filter LITES0_ADDR_MASK (B_CR_LITES0_AD-
DR_MASK_0_0_0_MCHBAR) — Offset 6CA8h ...................................................... 698
3.438 B-Unit Lites Group 0 Data Match Filter LITES0_DATA_MATCH (B_CR_LITES0_DATA_-
MATCH_0_0_0_MCHBAR) — Offset 6CB0h .......................................................... 699
3.439 B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK (B_CR_LITES0_-
DATA_MASK_0_0_0_MCHBAR) — Offset 6CB4h................................................... 700
3.440 B-Unit Lites Group 1 Control (B_CR_LITES1_CTL_0_0_0_MCHBAR) — Offset 6CC0h. 700
3.441 B-Unit Lites Group 1 Opcode Match Filter (B_CR_LITES1_OPCODE_MATCH_0_0_0_MCH-
BAR) — Offset 6CC4h ...................................................................................... 702
3.442 B-Unit Lites Group 1 Agent Match Filter (B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)
— Offset 6CC8h .............................................................................................. 703
3.443 B-Unit Lites Group 1 U2C IntData Match Filter (B_CR_LITES1_U2CINTDATA_-
MATCH_0_0_0_MCHBAR) — Offset 6CCCh .......................................................... 704
3.444 B-Unit Lites Group 1 Address Match Filter LITES1_ADDR_MATCH (B_CR_LITES1_ADDR_-
MATCH_0_0_0_MCHBAR) — Offset 6CD0h .......................................................... 704
3.445 B-Unit Lites Group 1 Address Mask Filter LITES1_ADDR_MASK (B_CR_LITES1_AD-
DR_MASK_0_0_0_MCHBAR) — Offset 6CD8h ...................................................... 704
3.446 B-Unit Lites Group 1 Data Match Filter LITES1_DATA_MATCH (B_CR_LITES1_DATA_-
MATCH_0_0_0_MCHBAR) — Offset 6CE0h .......................................................... 705
3.447 B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK (B_CR_LITES1_-
DATA_MASK_0_0_0_MCHBAR) — Offset 6CE4h ................................................... 706
3.448 B-Unit Lites Group 2 Control (B_CR_LITES2_CTL_0_0_0_MCHBAR) — Offset 6CF0h . 706
3.449 B-Unit Lites Group 2 Opcode Match Filter (B_CR_LITES2_OPCODE_MATCH_0_0_0_MCH-
BAR) — Offset 6CF4h ....................................................................................... 708
3.450 B-Unit Lites Group 2 Agent Match Filter (B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)
— Offset 6CF8h............................................................................................... 709
3.451 B-Unit Lites Group 2 U2C IntData Match Filter (B_CR_LITES2_U2CINTDATA_-
MATCH_0_0_0_MCHBAR) — Offset 6CFCh .......................................................... 710
3.452 B-Unit Lites Group 2 Address Match Filter LITES2_ADDR_MATCH (B_CR_LITES2_ADDR_-
MATCH_0_0_0_MCHBAR) — Offset 6D00h .......................................................... 710
Datasheet Volume 2 of 2 13
3.453 B-Unit Lites Group 2 Address Mask Filter LITES2_ADDR_MASK (B_CR_LITES2_AD-
DR_MASK_0_0_0_MCHBAR) — Offset 6D08h....................................................... 710
3.454 B-Unit Lites Group 2 Data Match Filter LITES2_DATA_MATCH (B_CR_LITES2_DATA_-
MATCH_0_0_0_MCHBAR) — Offset 6D10h .......................................................... 711
3.455 B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK (B_CR_LITES2_-
DATA_MASK_0_0_0_MCHBAR) — Offset 6D14h ................................................... 712
3.456 B-Unit Lites Group 3 Control (B_CR_LITES3_CTL_0_0_0_MCHBAR) — Offset 6D20h . 712
3.457 B-Unit Lites Group 3 Opcode Match Filter (B_CR_LITES3_OPCODE_MATCH_0_0_0_MCH-
BAR) — Offset 6D24h ....................................................................................... 714
3.458 B-Unit Lites Group 3 Agent Match Filter (B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)
— Offset 6D28h............................................................................................... 715
3.459 B-Unit Lites Group 3 U2C IntData Match Filter (B_CR_LITES3_U2CINTDATA_-
MATCH_0_0_0_MCHBAR) — Offset 6D2Ch .......................................................... 716
3.460 B-Unit Lites Group 3 Address Match Filter LITES3_ADDR_MATCH (B_CR_LITES3_ADDR_-
MATCH_0_0_0_MCHBAR) — Offset 6D30h .......................................................... 716
3.461 B-Unit Lites Group 3 Address Mask Filter LITES3_ADDR_MASK (B_CR_LITES3_AD-
DR_MASK_0_0_0_MCHBAR) — Offset 6D38h....................................................... 716
3.462 B-Unit Lites Group 3 Data Match Filter LITES3_DATA_MATCH (B_CR_LITES3_DATA_-
MATCH_0_0_0_MCHBAR) — Offset 6D40h .......................................................... 717
3.463 B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK (B_CR_LITES3_-
DATA_MASK_0_0_0_MCHBAR) — Offset 6D44h ................................................... 718
3.464 B-Unit Lites and Emon Master Control LITESEMONCTL (B_CR_LITESEMON_CT-
L_0_0_0_MCHBAR) — Offset 6D48h ................................................................... 718
3.465 B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0) — Offset 6D4Ch ................. 719
3.466 B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1) — Offset 6D50h ................. 720
3.467 B-Unit Scheduler Control (B_CR_BSCHWT0) — Offset 6D54h ................................. 721
3.468 B-Unit Scheduler Control (B_CR_BSCHWT1) — Offset 6D58h ................................. 721
3.469 B-Unit Scheduler Control (B_CR_BSCHWT2) — Offset 6D5Ch................................. 722
3.470 B-Unit Scheduler Control (B_CR_BSCHWT3) — Offset 6D60h ................................. 723
3.471 B-Unit Flush Control (B_CR_BWFLUSH) — Offset 6D64h........................................ 723
3.472 B-Unit Flush Weights (B_CR_BFLWT) — Offset 6D68h........................................... 724
3.473 Weighted Scheduling Control of High Priority ISOC and Other Requests (B_CR_BISOCWT)
— Offset 6D6Ch............................................................................................... 724
3.474 B-Unit Control (B_CR_BCTRL2) — Offset 6D70h................................................... 725
3.475 Asset Classification Bits (B_CR_AC_RS0_0_0_0_MCHBAR) — Offset 6D74h ............. 726
3.476 IDI Real-Time Feature Configuration Bits (B_CR_RT_EN_0_0_0_MCHBAR) — Offset
6D78h............................................................................................................ 727
3.477 B-Unit Control Register 3 (B_CR_BCTRL3) — Offset 6D7Ch.................................... 727
3.478 Asymmetric Memory Region 0 (B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR) — Offset
6E40h ............................................................................................................ 728
3.479 Asymmetric Memory Region 1 (B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR) — Offset
6E44h ............................................................................................................ 728
3.480 B-Unit Machine Check Mode Low (B_CR_BMCMODE_LOW) — Offset 6E48h .............. 729
3.481 B-Unit Machine Check Mode High (B_CR_BMCMODE_HIGH) — Offset 6E4Ch ............ 729
3.482 Two-Way Asymmetric Memory Region Configuration (B_CR_ASYM_2WAY_MEM_RE-
GION_0_0_0_MCHBAR) — Offset 6E50h ............................................................. 729
3.483 SGX Status (B_CR_SGX_STATUS_0_0_0_MCHBAR) — Offset 6E54h ....................... 730
3.484 Thermal Device Mailbox Data0 (P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR) —
Offset 7000h ................................................................................................... 731
3.485 Thermal Device Mailbox Data1 (P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR) —
Offset 7004h ................................................................................................... 731
3.486 Thermal Device Mailbox Interface (P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCH-
BAR) — Offset 7008h ....................................................................................... 731
3.487 Thermal Device IRQ and Lock Configuration (P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCH-
BAR) — Offset 700Ch ....................................................................................... 732
3.488 Package Thermal Interrupt Control (P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR) —
Offset 7010h ................................................................................................... 733
14 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 15
Offset 70C4h................................................................................................... 754
3.519 I-unit Processing System C0 Residency Counter (P_CR_TELEM_IUNIT_C0_RESIDEN-
CY_0_0_0_MCHBAR) — Offset 70C8h ................................................................. 755
3.520 TELEM_IA_FREQ_ACCUMULATOR (P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCH-
BAR) — Offset 70CCh ....................................................................................... 755
3.521 Graphics C0 Residency Counter (P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCH-
BAR) — Offset 70D0h ....................................................................................... 755
3.522 I-unit Processing System C0 Residency Counter (P_CR_TELEM_IUNIT_FREQ_ACCUMULA-
TOR_0_0_0_MCHBAR) — Offset 70D4h............................................................... 756
3.523 Memory Active Residency (P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR) — Off-
set 70E8h ....................................................................................................... 756
3.524 Package Temperatures (P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR) — Offset
70F4h ............................................................................................................ 757
3.525 Package Thermal Limit Control (P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR) —
Offset 7104h ................................................................................................... 757
3.526 Memory Subsystem Frequency Capabilities (P_CR_MEMSS_FREQUENCY_CAPABILI-
TIES_0_0_0_MCHBAR) — Offset 7108h .............................................................. 758
3.527 Memory Controller (MC) BIOS Reset Request and Status
(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR) — Offset 7114h ...................................... 758
3.528 P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR — Offset 7118h ......... 761
3.529 PP1_C0_CORE_CLOCK_0_0_0_MCHBAR (P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)
— Offset 7160h ............................................................................................... 761
3.530 Core Exists Vector (P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR) — Offset 7164h 762
3.531 Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR) — Offset
7168h ............................................................................................................ 762
3.532 PL3 and PL4 Control (P_CR_PL3_CONTROL_0_0_0_MCHBAR) — Offset 71F0h.......... 763
3.533 Graphics Superqueue Active Clocks (P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCH-
BAR) — Offset 7244h ....................................................................................... 764
3.534 LPDDR DRAM Thermal (MR4) Status of Channel 00 (P_CR_MEM_MR4_TEMPERA-
TURE_DEV3_0_0_0_MCHBAR) — Offset 7248h .................................................... 765
3.535 LPDDR DRAM Thermal (MR4) Status of Channel 11 (P_CR_MEM_MR4_TEMPERA-
TURE_DEV4_0_0_0_MCHBAR) — Offset 724Ch .................................................... 765
3.536 Interrupt Redirection Control (INTR_REDIR_CTL_MCHBAR) — Offset 7800h ............. 765
3.537 X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR) — Offset 7804h .............................. 766
3.538 Clock Gating Control (CLKGATE_CTL_MCHBAR) — Offset 7808h ............................. 767
3.539 Miscellaneous Controls (MISC_CTL_MCHBAR) — Offset 780Ch ............................... 769
3.540 Control (CTL_MCHBAR) — Offset 7810h .............................................................. 770
3.541 PSMI Control (PSMI_CTL_MCHBAR) — Offset 7814h ............................................. 772
3.542 Miscellaneous T2A selector (T2A_SELECTOR_MISC_MCHBAR) — Offset 7818h ......... 773
3.543 VC Read Ordering CFG (VC_READ_ORDERING_CFG_MCHBAR) — Offset 781Ch ........ 774
3.544 VC Write Ordering CFG (VC_WRITE_ORDERING_CFG_MCHBAR) — Offset 7820h ...... 775
3.545 IDI0 C2U Credit Control (IDI0_C2U_CREDIT_CTRL_MCHBAR) — Offset 7824h ......... 777
3.546 IDI1 C2U Credit Control (IDI1_C2U_CREDIT_CTRL_MCHBAR) — Offset 7828h ......... 777
3.547 IDI2 C2U Credit Control (IDI2_C2U_CREDIT_CTRL_MCHBAR) — Offset 782Ch ......... 778
3.548 IDI3 C2U Credit Control (IDI3_C2U_CREDIT_CTRL_MCHBAR) — Offset 7830h ......... 779
3.549 IDI4 C2U Credit Control (IDI4_C2U_CREDIT_CTRL_MCHBAR) — Offset 7834h ......... 780
3.550 IDI5 C2U Credit Control (IDI5_C2U_CREDIT_CTRL_MCHBAR) — Offset 7838h ......... 780
3.551 IDI6 C2U Credit Control (IDI6_C2U_CREDIT_CTRL_MCHBAR) — Offset 783Ch ......... 781
3.552 IDI7 C2U Credit Control (IDI7_C2U_CREDIT_CTRL_MCHBAR) — Offset 7840h ......... 782
3.553 PII2 A2T Credit Control (PII2_A2T_CREDIT_CTRL_MCHBAR) — Offset 7844h ........... 782
3.554 BIOSWR Control Policy (T_CR_BIOSWR_CP_0_0_0_MCHBAR) — Offset 7848h ......... 783
3.555 BIOSWR Read Access Control (T_CR_BIOSWR_RAC_0_0_0_MCHBAR) — Offset 7850h...
783
3.556 BIOSWR Write Access Control (T_CR_BIOSWR_WAC_0_0_0_MCHBAR) — Offset 7858h .
784
3.557 Tunit Pcode/Ucode Write, All Read Control Policy Register (T_CR_P_U_CODEWR_ALL-
16 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 17
5.22 B-Unit Copy of Default VTd BAR PHM Base Register (B_CR_PHM-
BASE_REG_0_0_0_DEFVTDBAR)—Offset 70h ...................................................... 813
5.23 B-Unit Copy of Default VTd BAR PHM Limit Register (B_CR_PHMLIM-
IT_REG_0_0_0_DEFVTDBAR)—Offset 78h ........................................................... 813
6 Gaussian Mixture Model (GMM) Registers ..............................................................815
6.1 ID — Offset 0h ................................................................................................ 815
6.2 Device Control (DCTRL) — Offset 4h................................................................... 815
6.3 Device Status (DSTS) — Offset 6h ..................................................................... 816
6.4 RID: Revision ID DLCO: Class Code (RID_DLCO) — Offset 8h ................................ 817
6.5 Cache Line Size (CLS) — Offset Ch..................................................................... 817
6.6 Header Type (HTYPE) — Offset Eh...................................................................... 818
6.7 Built-in Self Test (BIST) — Offset Fh................................................................... 818
6.8 GNA Base Address Low (GNABAL) — Offset 10h ................................................... 818
6.9 GNA Base Address High (GNABAH) — Offset 14h ................................................. 819
6.10 Sub System Vendor Identifiers (SSVI) — Offset 2Ch ............................................. 819
6.11 Sub System Identifiers (SSI) — Offset 2Eh.......................................................... 820
6.12 Capabilities Pointers (CAPP) — Offset 34h ........................................................... 820
6.13 Interrupt Line (INTL) — Offset 3Ch .................................................................... 820
6.14 Interrupt Pin Register (INTP) — Offset 3Dh ......................................................... 821
6.15 Min Grant And Min Latency Register (MINGNTLAT) — Offset 3Eh ............................ 821
6.16 Override Configuration Control (OVRCFGCTL) — Offset 40h ................................... 821
6.17 Message Signaled Interrupt Capability ID (MSICAPID) — Offset 90h ....................... 823
6.18 Message Signaled Interrupt Message Control (MC) — Offset 92h ............................ 823
6.19 Message Signaled Interrupt Message Address (MA) — Offset 94h ........................... 824
6.20 Message Signaled Interrupt Message Data (MD) — Offset 98h ............................... 824
6.21 D0i3 Capability ID (D0I3CAPID) — Offset A0h ..................................................... 824
6.22 D0i3 Capability (D0I3CAP) — Offset A2h ............................................................. 825
6.23 D0i3 Vendor Extended Capability Register (D0I3VSEC) — Offset A4h ...................... 825
6.24 D0i3 SW LTR Pointer Register (D0I3SWLTRPTR) — Offset A8h ............................... 826
6.25 D0i3 DevIdle Pointer Register (D0I3DEVIDLEPTR) — Offset ACh............................. 826
6.26 D0i3 DevIdle Power On Latency (D0I3DEVIDLEPOL) — Offset B0h .......................... 826
6.27 D0i3 Power Control Enables Register (PCE) — Offset B2h ...................................... 827
6.28 Power Management Capability ID (PMCAPID) — Offset DCh ................................... 827
6.29 Power Management Capability (PMCAP) — Offset DEh........................................... 828
6.30 Power Management Control Status (PMCS) — Offset E0h ...................................... 828
6.31 FLR Capability ID (FLRCAPID) — Offset F0h......................................................... 829
6.32 FLR Capability Length And Version (FLRMISC) — Offset F2h................................... 829
6.33 FLR Control Register (FLRCTL) — Offset F4h ........................................................ 830
6.34 FLR Status Register (FLRSTS) — Offset F5h......................................................... 830
6.35 GMM Status Register (GNASTS)—Offset 80h........................................................ 830
6.36 GMM Control Register (GNACTRL)—Offset 84h ..................................................... 832
6.37 GMM Management And Control Register (GNAMCTL)—Offset 88h ........................... 834
6.38 GMM Performance Total Cycle (GNAPTC)—Offset 8Ch ........................................... 834
6.39 GMM Performance Stall Cycles (GNAPSC)—Offset 90h........................................... 835
6.40 GMM Internal State Index (GNAISI)—Offset 94h .................................................. 835
6.41 GMM Internal State Value Low (GNAPISVL)—Offset 98h ........................................ 836
6.42 GMM Internal State Value High (GNAPISVH)—Offset 9Ch ...................................... 836
6.43 GMM Break Point Setup Low (GNABPL)—Offset A0h .............................................. 836
6.44 GMM Break Point Setup High (GNABPH)—Offset A4h............................................. 837
6.45 GMM Internal State Value (GNAD0i3C)—Offset A8h .............................................. 837
6.46 GNA Descriptor Base Address Register (GNADESBASE)—Offset B0h ........................ 838
6.47 GNA Information Register (GNAIBUFFS)—Offset B4h ............................................ 839
6.48 GNASAI1L (GNASAI1L)—Offset 100h .................................................................. 839
6.49 GNASAI1H (GNASAI1H)—Offset 104h ................................................................. 839
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7.49 LEGACY_ELIM Register (LE)—Offset 10h ............................................................. 869
7.50 Reserved_2 (RSV_2)—Offset 11h....................................................................... 869
7.51 TCO_TMR Register (TTMR)—Offset 12h............................................................... 870
7.52 Reserved_3 (RSV_3)—Offset 14h....................................................................... 870
7.53 Reserved_4 (RSV_4)—Offset 1Ch....................................................................... 870
8 LPC Registers .........................................................................................................872
8.1 ID — Offset 0h ................................................................................................ 872
8.2 Device Command (CMD) — Offset 4h ................................................................. 872
8.3 Status (STS) — Offset 6h.................................................................................. 873
8.4 Revision ID (RID) — Offset 8h ........................................................................... 874
8.5 Class Code (CC) — Offset 9h ............................................................................. 874
8.6 Primary Latency Timer (PLT) — Offset Dh ........................................................... 874
8.7 Header Type (HTYPE) — Offset Eh...................................................................... 875
8.8 Sub System Identifiers (SS) — Offset 2Ch........................................................... 875
8.9 Capability List Pointer (CAPP) — Offset 34h ......................................................... 875
8.10 Serial IRQ Control (SCNT) — Offset 64h.............................................................. 876
8.11 B-Unit Copy of the I/O Decode Ranges Register for LPC (B_CR_IOD_IOE_LPC) — Offset
80h................................................................................................................ 876
8.12 I/O Enables (IOE) — Offset 82h ......................................................................... 878
8.13 B_LGIR1_LPC (B_CR_LGIR1_LPC) — Offset 84h................................................... 878
8.14 B_LGIR2_LPC (B_CR_LGIR2_LPC) — Offset 88h................................................... 879
8.15 B_LGIR3_LPC (B_CR_LGIR3_LPC) — Offset 8Ch................................................... 879
8.16 B_LGIR4_LPC (B_CR_LGIR4_LPC) — Offset 90h................................................... 880
8.17 USB Legacy Keyboard/Mouse Control (ULKMC) — Offset 94h ................................. 881
8.18 B-Unit Copy of the LPC Generic Memory Range Register for LPC (B_CR_LGMR_LPC) — Off-
set 98h .......................................................................................................... 882
8.19 Reserved (RSVD) — Offset 9Ch ......................................................................... 882
8.20 B-Unit Copy of the eSPI CS1# Generic I/O Range #1 (B_CR_PCCS1GIR1_ESPI) — Offset
A4h ............................................................................................................... 882
8.21 B-Unit Copy of the eSPI CS1# Generic Memory Range #1 Register (B_CR_P-
CCS1GMR1_ESPI) — Offset A8h......................................................................... 883
8.22 FWH ID Select #1 (FS1) — Offset D0h................................................................ 883
8.23 FWH ID Select #2 (FS2) — Offset D4h................................................................ 884
8.24 B-Unit Copy of the BIOS Decode Enable Register for LPC (B_CR_BDE_LPC) — Offset D8h
884
8.25 BIOS Control (BC) — Offset DCh ........................................................................ 885
8.26 RBR (RBR)—Offset 0h ...................................................................................... 886
8.27 THR (THR)—Offset 0h....................................................................................... 886
8.28 DLL (DLL)—Offset 0h ....................................................................................... 887
8.29 IER (IER)—Offset 4h ........................................................................................ 887
8.30 DLH (DLH)—Offset 4h ...................................................................................... 888
8.31 IIR (IIR)—Offset 8h ......................................................................................... 888
8.32 FCR (FCR)—Offset 8h ....................................................................................... 888
8.33 LCR (LCR)—Offset Ch ....................................................................................... 889
8.34 MCR (MCR)—Offset 10h .................................................................................... 890
8.35 LSR (LSR)—Offset 14h ..................................................................................... 892
8.36 MSR (MSR)—Offset 18h .................................................................................... 894
8.37 SCR (SCR)—Offset 1Ch..................................................................................... 895
8.38 SRBR_STHR0 (SRBR_STHR0)—Offset 30h ........................................................... 895
8.39 SRBR_STHR1 (SRBR_STHR1)—Offset 34h ........................................................... 896
8.40 SRBR_STHR2 (SRBR_STHR2)—Offset 38h ........................................................... 896
8.41 SRBR_STHR3 (SRBR_STHR3)—Offset 3Ch........................................................... 897
8.42 SRBR_STHR4 (SRBR_STHR4)—Offset 40h ........................................................... 898
8.43 SRBR_STHR5 (SRBR_STHR5)—Offset 44h ........................................................... 898
8.44 SRBR_STHR6 (SRBR_STHR6)—Offset 48h ........................................................... 899
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8.100 PCI Clock Control (PCCTL)—Offset E0h ............................................................... 933
8.101 Manufacturer's ID (MANID)—Offset F8h .............................................................. 935
9 eSPI Registers........................................................................................................936
9.1 Identifiers (ESPI_DID_VID) — Offset 0h ............................................................. 936
9.2 Device Status and Command (ESPI_STS_CMD) — Offset 4h .................................. 936
9.3 Class Code and Revision ID (ESPI_CC_RID) — Offset 8h ....................................... 937
9.4 Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT) — Offset Ch .
938
9.5 CSXE BAR0 MMIO (CSXE_ESPI_MBAR) — Offset 10h ............................................ 938
9.6 Sub System Identifiers (ESPI_SS) — Offset 2Ch .................................................. 939
9.7 Capability List Pointer (ESPI_CAPP) — Offset 34h ................................................. 939
9.8 Capabilities List Pointer (CSXE_ESPI_CAPP) — Offset 40h...................................... 939
9.9 MSI Message Control, Next Pointer and Capability ID (CSXE_ESPI_MSIMC_MSINP_MSI-
CID) — Offset 44h ........................................................................................... 940
9.10 MSI Message Address (CSXE_ESPI_MSIMA) — Offset 48h ..................................... 940
9.11 MSI Message Data (CSXE_ESPI_MSIMD) — Offset 4Ch ......................................... 941
9.12 PCI Power Management Capability (CSXE_ESPI_PMCAP_PMNP_PMCID) — Offset 50h 941
9.13 PCI Power Management Control and Status (CSXE_ESPI_PMD_PMCSRBSE_PMCSR) —
Offset 54h ...................................................................................................... 942
9.14 Peripheral Channel Serial IRQ Control (ESPI_PCSERIRQC) — Offset 64h .................. 943
9.15 I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE) — Offset 80h........................ 943
9.16 LPC Generic I/O Range #1 (ESPI_LGIR1) — Offset 84h ......................................... 944
9.17 LPC Generic I/O Range #2 (ESPI_LGIR2) — Offset 88h ......................................... 945
9.18 LPC Generic I/O Range #3 (ESPI_LGIR3) — Offset 8Ch......................................... 945
9.19 LPC Generic I/O Range #4 (ESPI_LGIR4) — Offset 90h ......................................... 946
9.20 USB Legacy Keyboard/Mouse Control (ESPI_ULKMC) — Offset 94h ......................... 946
9.21 LPC Generic Memory Range (ESPI_LGMR) — Offset 98h ........................................ 947
9.22 eSPI CS1# I/O Routing Enables (ESPI_CS1IORE) — Offset A0h.............................. 948
9.23 eSPI CS1# Generic I/O Range #1 (ESPI_CS1GIR1) — Offset A4h........................... 949
9.24 eSPI CS1# Generic Memory Range #1 (ESPI_CS1GMR1) — Offset A8h ................... 949
9.25 FWH ID Select #1 (ESPI_PCFS1) — Offset D0h .................................................... 950
9.26 FWH ID Select #2 (ESPI_PCFS2) — Offset D4h .................................................... 950
9.27 BIOS Decode Enable (ESPI_BDE) — Offset D8h ................................................... 950
9.28 BIOS Control (ESPI_BC) — Offset DCh................................................................ 951
9.29 Manufacturer's ID (ESPI_MANID) — Offset F8h .................................................... 953
10 PMC Registers ........................................................................................................954
10.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID) — Offset 0h ... 954
10.2 STATUSCOMMAND — Offset 4h.......................................................................... 954
10.3 REVCLASSCODE — Offset 8h ............................................................................. 955
10.4 CLLATHEADERBIST — Offset Ch......................................................................... 955
10.5 BAR — Offset 10h ............................................................................................ 956
10.6 BAR -Base Address Register High (BAR_HIGH) — Offset 14h ................................. 956
10.7 BAR1 — Offset 18h .......................................................................................... 957
10.8 BAR1 -Base Address Register1 High (BAR1_HIGH) — Offset 1Ch ............................ 957
10.9 BAR2 — Offset 20h .......................................................................................... 958
10.10 SUBSYSTEMID — Offset 2Ch ............................................................................. 958
10.11 EXPANSION ROM base address (EXPANSION_ROM_BASEADDR) — Offset 30h ......... 958
10.12 CAPABILITYPTR — Offset 34h ............................................................................ 959
10.13 INTERRUPTREG — Offset 3Ch ............................................................................ 959
10.14 POWERCAPID — Offset 80h............................................................................... 959
10.15 PMECTRLSTATUS — Offset 84h .......................................................................... 960
10.16 PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD) — Offset 90h... 960
10.17 DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) — Offset 94h ........... 961
10.18 D0I3_CONTROL_SW_LTR_MMIO_REG — Offset 98h ............................................. 961
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Datasheet Volume 2 of 2 23
TIES_0_2_0_GTTMMADR)—Offset 8178h ............................................................ 981
10.54 GT_PERF_LIMIT_REASONS (P_CR_GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR)—
Offset 8184h ................................................................................................... 982
10.55 GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR (P_CR_GTDRIVER_HWP_RE-
QUEST_0_2_0_GTTMMADR)—Offset 8190h ......................................................... 984
10.56 GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR (P_CR_GT_VIDEO_BUSYNESS_0_2_0_GTT-
MMADR)—Offset 819Ch .................................................................................... 985
10.57 GEN_REGRW1 - General Purpose register (GEN_REGRW1)—Offset 600h ................. 985
10.58 GEN_REGRW2 - General Purpose register (GEN_REGRW2)—Offset 604h ................. 986
10.59 GEN_REGRW3 - General Purpose register (GEN_REGRW3)—Offset 608h ................. 986
10.60 GEN_REGRW4 - General Purpose register (GEN_REGRW4)—Offset 60Ch ................. 986
10.61 Power Management 1 Control (PM1_CNT)—Offset 4h ............................................ 990
10.62 Power Management 1 Timer (PM1_TMR)—Offset 8h.............................................. 991
10.63 General Purpose Event 0 Status (GPE0a_STS)—Offset 20h .................................... 992
10.64 General Purpose Event 0 Status (GPE0b_STS)—Offset 24h .................................... 995
10.65 General Purpose Event 0 Status (GPE0c_STS)—Offset 28h .................................... 995
10.66 General Purpose Event 0 Status (GPE0d_STS)—Offset 2Ch.................................... 996
10.67 General Purpose Event 0 Enables (GPE0a_EN)—Offset 30h .................................... 996
10.68 General Purpose Event 0 Enable (GPE0b_EN)—Offset 34h ..................................... 999
10.69 General Purpose Event 0 Enable (GPE0c_EN)—Offset 38h ..................................... 999
10.70 General Purpose Event 0 Enable (GPE0d_EN)—Offset 3Ch ..................................... 999
10.71 SMI Control and Enable (SMI_EN)—Offset 40h................................................... 1000
10.72 SMI Status Register (SMI_STS)—Offset 44h ...................................................... 1002
10.73 Device Trap Status (DEVTRAP_STS)—Offset 4Ch................................................ 1006
10.74 General Purpose Event Control (GPE_CTRL)—Offset 50h ..................................... 1006
10.75 TCO Reload Register (TCO_RLD)—Offset 60h..................................................... 1007
10.76 TCO Timer Status (TCO_STS)—Offset 64h......................................................... 1007
10.77 TCO Timer Control (TCO1_CNT)—Offset 68h...................................................... 1008
10.78 TCO Timer Register (TCO_TMR)—Offset 70h...................................................... 1008
10.79 Advanced Power Management Status (APM_STS)—Offset 74h.............................. 1009
10.80 Advanced Power Management Control Port (APM_CNT)—Offset 78h ...................... 1009
10.81 Direct IRQ Enables (DIRECT_IRQ_EN)—Offset 7Ch ............................................. 1010
10.82 Power and Reset Status (PRSTS)—Offset 1000h................................................. 1011
10.83 PM CFG - Power Management Configuration (PMC_CFG)—Offset 1008h ................. 1012
10.84 Power Management Configuration (PMC_CFG2)—Offset 100Ch............................. 1015
10.85 SOC Power Management Status (SOC_PM_STS)—Offset 1010h ............................ 1016
10.86 General PM Configuration 1 (GEN_PMCON1)—Offset 1020h ................................. 1016
10.87 General PM Configuration 2 (GEN_PMCON2)—Offset 1024h ................................. 1019
10.88 General PM Configuration 3 (GEN_PMCON3)—Offset 1028h ................................. 1020
10.89 Configured Revision ID (CRID)—Offset 1030h .................................................... 1023
10.90 Function Disable 0 (FUNC_DIS_0)—Offset 1034h ............................................... 1023
10.91 Function Disable 1 (FUNC_DIS_1)—Offset 1038h ............................................... 1025
10.92 Extended Test Mode Register (ETR)—Offset 1048h ............................................. 1026
10.93 GPIO Group to General Purpose Event Register Configuration (GPIO_GPE_CFG)—Offset
1050h .......................................................................................................... 1027
10.94 UART IRQ Configuration (IRQ_CFG_UART)—Offset 1060h.................................... 1028
10.95 IRQ Select 0 (IRQ_SEL_0)—Offset 1064h.......................................................... 1029
10.96 IRQ Select 1 (IRQ_SEL_1)—Offset 1068h.......................................................... 1030
10.97 IRQ Select 2 (IRQ_SEL_2)—Offset 106Ch.......................................................... 1030
10.98 Function ACPI Enumeration 0 (FUNC_ACPI_ENUM_0)—Offset 1070h..................... 1031
10.99 Function ACPI Enumeration 1 (FUNC_ACPI_ENUM_1)—Offset 1074h..................... 1033
10.100Fixed Deep S0Ix Counter Lower 32 Bits (TELEM_DEEP_S0IX_LO_HOST)—Offset 1078h .
1033
10.101Fixed Deep S0Ix Counter Upper 32 Bits (TELEM_DEEP_S0IX_HI_HOST)—Offset 107Ch .
1034
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Datasheet Volume 2 of 2 25
11.26 Display Bus:Device:Function (DISPBDF) — Offset A0h ........................................ 1064
11.27 ICC Register Offsets (ICCOS) — Offset A4h ....................................................... 1065
11.28 Endpoint Mask 0 (EPMASK0) — Offset B0h ........................................................ 1065
11.29 Endpoint Mask 1 (EPMASK1) — Offset B4h ........................................................ 1066
11.30 Endpoint Mask 2 (EPMASK2) — Offset B8h ........................................................ 1066
11.31 Endpoint Mask 3 (EPMASK3) — Offset BCh ........................................................ 1066
11.32 Endpoint Mask 4 (EPMASK4) — Offset C0h ........................................................ 1067
11.33 Endpoint Mask 5 (EPMASK5) — Offset C4h ........................................................ 1067
11.34 Endpoint Mask 6 (EPMASK6) — Offset C8h ........................................................ 1067
11.35 Endpoint Mask 7 (EPMASK7) — Offset CCh ........................................................ 1067
11.36 SBI Address (SBIADDR) — Offset D0h .............................................................. 1068
11.37 SBI Data (SBIDATA) — Offset D4h ................................................................... 1068
11.38 SBI Status (SBISTAT) — Offset D8h ................................................................. 1069
11.39 SBI Routing Identification (SBIRID) — Offset DAh .............................................. 1069
11.40 SBI Extended Address (SBIEXTADDR) — Offset DCh........................................... 1070
11.41 P2SB Control (P2SBC) — Offset E0h ................................................................. 1070
11.42 Power Control Enable (PCE) — Offset E4h ......................................................... 1071
11.43 Power Gate Control Block Timing (PGCBT) — Offset E6h ..................................... 1071
11.44 Primary Clock Domain Controls (PDOMAIN) — Offset E8h .................................... 1072
11.45 Sideband Clock Domain Controls (SDOMAIN) — Offset EAh ................................. 1072
11.46 Unsupported Request Error Status (URES) — Offset F0h ..................................... 1073
11.47 Unsupported Request Error Control (UREC) — Offset F4h .................................... 1073
11.48 Manufacturers ID (MANID) — Offset F8h ........................................................... 1074
11.49 SAI Policy Control (SAIPOLCTRL0) — Offset 240h............................................... 1074
11.50 SAI Policy Control (SAIPOLCTRL1) — Offset 244h............................................... 1075
11.51 SAI Policy Access Control (SAIPOLAC0) — Offset 248h........................................ 1075
11.52 SAI Policy Access Control (SAIPOLAC1) — Offset 24Ch........................................ 1075
12 PWM Registers .....................................................................................................1077
12.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID) — Offset 0h . 1077
12.2 STATUSCOMMAND — Offset 4h........................................................................ 1077
12.3 REVCLASSCODE — Offset 8h ........................................................................... 1078
12.4 CLLATHEADERBIST — Offset Ch....................................................................... 1078
12.5 BAR — Offset 10h .......................................................................................... 1079
12.6 BAR -Base Address Register High (BAR_HIGH) — Offset 14h ............................... 1079
12.7 BAR1 — Offset 18h ........................................................................................ 1080
12.8 BAR1 -Base Address Register1 High (BAR1_HIGH) — Offset 1Ch .......................... 1080
12.9 BAR2 — Offset 20h ........................................................................................ 1081
12.10 SUBSYSTEMID — Offset 2Ch ........................................................................... 1081
12.11 EXPANSION ROM base address (EXPANSION_ROM_BASEADDR) — Offset 30h ....... 1081
12.12 CAPABILITYPTR — Offset 34h .......................................................................... 1082
12.13 INTERRUPTREG — Offset 3Ch .......................................................................... 1082
12.14 POWERCAPID — Offset 80h............................................................................. 1082
12.15 PMECTRLSTATUS — Offset 84h ........................................................................ 1083
12.16 PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD) — Offset 90h. 1083
12.17 DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) — Offset 94h ......... 1084
12.18 D0I3_CONTROL_SW_LTR_MMIO_REG — Offset 98h ........................................... 1084
12.19 DEVICE_IDLE_POINTER_REG — Offset 9Ch ....................................................... 1085
12.20 D0I3_MAX_POW_LAT_PG_CONFIG — Offset A0h ............................................... 1085
12.21 GEN_REGRW1 - General Purpose Read Write Register1 (GEN_REGRW1) — Offset B0h ...
1086
12.22 GEN_REGRW2 — Offset B4h............................................................................ 1086
12.23 GEN_REGRW3 — Offset B8h............................................................................ 1086
12.24 GEN_REGRW4 — Offset BCh............................................................................ 1087
12.25 GEN_INPUT_REG — Offset C0h........................................................................ 1087
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13.53 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h ..... 1117
13.54 BlockSize Register (blocksize)—Offset 4h .......................................................... 1117
13.55 BlockCount Register (blockcount)—Offset 6h ..................................................... 1117
13.56 Argument1 Register (argument1)—Offset 8h ..................................................... 1118
13.57 TransferMode Register (transfermode)—Offset Ch .............................................. 1118
13.58 Command Register (command)—Offset Eh ........................................................ 1119
13.59 Response Register (response01)—Offset 10h..................................................... 1119
13.60 Response Register (response2)—Offset 14h ...................................................... 1120
13.61 Response Register (response3)—Offset 16h ...................................................... 1120
13.62 Response Register (response4)—Offset 18h ...................................................... 1120
13.63 Response Register (response5)—Offset 1Ah ...................................................... 1121
13.64 Response Register (response6)—Offset 1Ch ...................................................... 1121
13.65 Response Register (response7)—Offset 1Eh ...................................................... 1121
13.66 Buffer DataPort Register (dataport)—Offset 20h................................................. 1122
13.67 PresentState Register (presentstate)—Offset 24h ............................................... 1122
13.68 HostControl1 Register (hostcontrol1)—Offset 28h............................................... 1124
13.69 PowerControl Register (powercontrol)—Offset 29h ............................................. 1124
13.70 BlockGapControl Register (blockgapcontrol)—Offset 2Ah ..................................... 1125
13.71 Wakeup Control Register (wakeupcontrol)—Offset 2Bh........................................ 1125
13.72 Clock Control Register (clockcontrol)—Offset 2Ch ............................................... 1126
13.73 Timeout Control Register (timeoutcontrol)—Offset 2Eh ....................................... 1126
13.74 Software Reset Register (softwarereset)—Offset 2Fh .......................................... 1127
13.75 Normal Interrupt Status Register (normalintrsts)—Offset 30h .............................. 1127
13.76 ErrorInterruptStatus_Register (errorintrsts)—Offset 32h ..................................... 1129
13.77 Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h ............... 1130
13.78 Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ..................... 1131
13.79 Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h ............... 1132
13.80 Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah ..................... 1133
13.81 Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ........................... 1134
13.82 Host Control2 Register (hostcontrol2)—Offset 3Eh.............................................. 1135
13.83 Capabilities Register (capabilities)—Offset 40h................................................... 1136
13.84 Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ................... 1138
13.85 Force Event REGISTER for AUTO CMD Error Status (ForceEventforAUTOCMDErrorSta-
tus)—Offset 50h ............................................................................................ 1139
13.86 Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset 52h 1139
13.87 ADMA Error Status Register (admaerrsts)—Offset 54h ........................................ 1140
13.88 ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ....................... 1141
13.89 ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ............................ 1141
13.90 ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ............................ 1141
13.91 Preset Value Register for Initialization (presetvalue0)—Offset 60h ........................ 1142
13.92 Preset Value Register for Default Speed (presetvalue1)—Offset 62h...................... 1142
13.93 Preset Value Register for High Speed (presetvalue2)—Offset 64h ......................... 1143
13.94 Preset Value Register for SDR12 (presetvalue3)—Offset 66h................................ 1143
13.95 Preset Value Register for SDR25 (presetvalue4)—Offset 68h................................ 1144
13.96 Preset Value Register for SDR50 (presetvalue5)—Offset 6Ah ............................... 1144
13.97 Preset Value Register for SDR104 (presetvalue6)—Offset 6Ch.............................. 1145
13.98 Preset Value Register for DDR50 (presetvalue7)—Offset 6Eh ............................... 1145
13.99 Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ............................... 1146
13.100Preset Value Register for DDR50 (presetvalue8)—Offset 74h ............................... 1146
13.101Vendor Register (vendreg)—Offset 78h ............................................................ 1147
13.102Slot Interrupt Status Register (slotintrsts)—Offset FCh ....................................... 1147
13.103Host Controller Version Register (hostcontrollerver)—Offset FEh .......................... 1148
13.104CQVER (CQVER)—Offset 200h......................................................................... 1148
13.105CQCAP (CQCAP)—Offset 204h......................................................................... 1148
13.106CQCFG (CQCFG)—Offset 208h ........................................................................ 1149
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15.7 IC_SS_SCL_LCNT — Offset 18h ....................................................................... 1175
15.8 IC_FS_SCL_HCNT — Offset 1Ch....................................................................... 1175
15.9 IC_FS_SCL_LCNT — Offset 20h ....................................................................... 1175
15.10 IC_HS_SCL_HCNT — Offset 24h ...................................................................... 1176
15.11 IC_HS_SCL_LCNT — Offset 28h ....................................................................... 1176
15.12 IC_INTR_STAT — Offset 2Ch ........................................................................... 1176
15.13 IC_INTR_MASK — Offset 30h .......................................................................... 1177
15.14 IC_RAW_INTR_STAT — Offset 34h ................................................................... 1178
15.15 IC_RX_TL — Offset 38h .................................................................................. 1179
15.16 IC_TX_TL — Offset 3Ch .................................................................................. 1179
15.17 IC_CLR_INTR — Offset 40h ............................................................................. 1180
15.18 IC_CLR_RX_UNDER — Offset 44h .................................................................... 1180
15.19 IC_CLR_RX_OVER — Offset 48h ...................................................................... 1180
15.20 IC_CLR_TX_OVER — Offset 4Ch....................................................................... 1181
15.21 IC_CLR_RD_REQ — Offset 50h ........................................................................ 1181
15.22 IC_CLR_TX_ABRT — Offset 54h ....................................................................... 1181
15.23 IC_CLR_RX_DONE — Offset 58h ...................................................................... 1182
15.24 IC_CLR_ACTIVITY — Offset 5Ch ...................................................................... 1182
15.25 IC_CLR_STOP_DET — Offset 60h ..................................................................... 1182
15.26 IC_CLR_START_DET — Offset 64h ................................................................... 1183
15.27 IC_CLR_GEN_CALL — Offset 68h ..................................................................... 1183
15.28 IC_ENABLE — Offset 6Ch ................................................................................ 1183
15.29 IC_STATUS — Offset 70h ................................................................................ 1184
15.30 IC_TXFLR — Offset 74h .................................................................................. 1184
15.31 IC_RXFLR — Offset 78h .................................................................................. 1185
15.32 IC_SDA_HOLD — Offset 7Ch ........................................................................... 1185
15.33 IC_TX_ABRT_SOURCE — Offset 80h................................................................. 1185
15.34 IC_SLV_DATA_NACK_ONLY — Offset 84h.......................................................... 1186
15.35 IC_DMA_CR — Offset 88h ............................................................................... 1187
15.36 IC_DMA_TDLR — Offset 8Ch ........................................................................... 1187
15.37 IC_DMA_RDLR — Offset 90h ........................................................................... 1187
15.38 IC_SDA_SETUP — Offset 94h .......................................................................... 1188
15.39 IC_ACK_GENERAL_CALL — Offset 98h .............................................................. 1188
15.40 IC_ENABLE_STATUS — Offset 9Ch ................................................................... 1188
15.41 IC_FS_SPKLEN — Offset A0h........................................................................... 1189
15.42 IC_HS_SPKLEN — Offset A4h .......................................................................... 1189
15.43 IC_CLR_RESTART_DET (IC_CLR_RESTRART_DET) — Offset A8h .......................... 1190
15.44 IC_COMP_PARAM_1 — Offset F4h .................................................................... 1190
15.45 IC_COMP_VERSION — Offset F8h .................................................................... 1190
15.46 IC_COMP_TYPE — Offset FCh .......................................................................... 1191
15.47 reg_Reserved0 (RESERVED0) — Offset 200h ..................................................... 1191
15.48 reg_RESETS (RESETS) — Offset 204h .............................................................. 1191
15.49 reg_GENERAL (GENERAL) — Offset 208h .......................................................... 1192
15.50 reg_ACTIVELTR (ACTIVELTR_VALUE) — Offset 210h........................................... 1193
15.51 reg_IDLELTR (IDLELTR_VALUE) — Offset 214h .................................................. 1193
15.52 reg_TX_ACK_COUNT (TX_ACK_COUNT) — Offset 218h ....................................... 1194
15.53 rx_ack_count (RX_BYTE_COUNT) — Offset 21Ch ............................................... 1194
15.54 TX_COMPLETE_INTR_STAT — Offset 220h ........................................................ 1195
15.55 TX_COMPLETE_INTR_CLR — Offset 224h .......................................................... 1195
15.56 reg_SW_SCRATCH_0 (SW_SCRATCH_0) — Offset 228h ...................................... 1195
15.57 reg_SW_SCRATCH_1 (SW_SCRATCH_1) — Offset 22Ch ...................................... 1196
15.58 reg_SW_SCRATCH_2 (SW_SCRATCH_2) — Offset 230h ...................................... 1196
15.59 reg_SW_SCRATCH_3 (SW_SCRATCH_3) — Offset 234h ...................................... 1196
15.60 reg_CLOCK_GATE (CLOCK_GATE) — Offset 238h ............................................... 1196
15.61 reg_Reserved1 (RESERVED1) — Offset 23Ch ..................................................... 1197
30 Datasheet Volume 2 of 2
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15.117MASKERR — Offset B30h................................................................................ 1228
15.118CLEARTFR — Offset B38h ............................................................................... 1229
15.119CLEARBLOCK — Offset B40h ........................................................................... 1229
15.120CLEARSRCTRAN — Offset B48h ....................................................................... 1229
15.121CLEARDSTTRAN — Offset B50h ....................................................................... 1230
15.122CLEARERR — Offset B58h............................................................................... 1230
15.123STATUSINT — Offset B60h ............................................................................. 1231
15.124DMACFGREG — Offset B98h ........................................................................... 1231
15.125CHENREG — Offset BA0h................................................................................ 1232
15.126RESERVED0_CPL — Offset BB8h...................................................................... 1232
15.127RESERVED0_CPH — Offset BBCh ..................................................................... 1232
15.128RESERVED1_CPL — Offset BC0h...................................................................... 1233
15.129RESERVED1_CPH — Offset BC4h ..................................................................... 1233
15.130RESERVED0_FPL — Offset C00h ...................................................................... 1233
15.131RESERVED0_FPH — Offset C04h ..................................................................... 1234
15.132RESERVED1_FPL — Offset C08h ...................................................................... 1234
15.133RESERVED1_FPH — Offset C0Ch ..................................................................... 1234
15.134SAI_ERR — Offset C10h ................................................................................. 1235
15.135GLOBAL_CFG — Offset C18h........................................................................... 1235
16 USB-Host (xHCI) Registers...................................................................................1236
16.1 Vendor ID (VID) — Offset 0h........................................................................... 1236
16.2 Device ID (DID) — Offset 2h ........................................................................... 1236
16.3 Command (CMD) — Offset 4h.......................................................................... 1236
16.4 Device Status (STS) — Offset 6h ..................................................................... 1237
16.5 Revision ID (RID) — Offset 8h ......................................................................... 1238
16.6 Programming Interface (PI) — Offset 9h ........................................................... 1238
16.7 Sub Class Code (SCC) — Offset Ah................................................................... 1239
16.8 Base Class Code (BCC) — Offset Bh ................................................................. 1239
16.9 Master Latency Timer (MLT) — Offset Dh .......................................................... 1239
16.10 Header Type (HT) — Offset Eh......................................................................... 1239
16.11 Memory Base Address (MBAR) — Offset 10h...................................................... 1240
16.12 USB Subsystem Vendor ID (SSVID) — Offset 2Ch .............................................. 1240
16.13 USB Subsystem ID (SSID) — Offset 2Eh ........................................................... 1240
16.14 Capabilities Pointer (CAP_PTR) — Offset 34h ..................................................... 1241
16.15 Interrupt Line (ILINE) — Offset 3Ch ................................................................. 1241
16.16 Interrupt Pin (IPIN) — Offset 3Dh .................................................................... 1241
16.17 XHC System Bus Configuration 1 (XHCC1) — Offset 40h ..................................... 1242
16.18 XHC System Bus Configuration 2 (XHCC2) — Offset 44h ..................................... 1243
16.19 Clock Gating (XHCLKGTEN) — Offset 50h .......................................................... 1244
16.20 Audio Time Synchronization (AUDSYNC) — Offset 58h ........................................ 1246
16.21 Serial Bus Release Number (SBRN) — Offset 60h ............................................... 1246
16.22 Frame Length Adjustment (FLADJ) — Offset 61h ................................................ 1246
16.23 Best Effort Service Latency (BESL) — Offset 62h ................................................ 1247
16.24 PCI Power Management Capability ID (PM_CID) — Offset 70h.............................. 1247
16.25 Next Item Pointer #1 (PM_NEXT) — Offset 71h.................................................. 1247
16.26 Power Management Capabilities (PM_CAP) — Offset 72h ..................................... 1248
16.27 Power Management Control/Status (PM_CS) — Offset 74h .................................. 1249
16.28 Message Signaled Interrupt CID (MSI_CID) — Offset 80h.................................... 1249
16.29 Next item pointer (MSI_NEXT) — Offset 81h ..................................................... 1250
16.30 Message Signaled Interrupt Message Control (MSI_MCTL) — Offset 82h ................ 1250
16.31 Message Signaled Interrupt Message Address (MSI_MAD) — Offset 84h ................ 1250
16.32 Message Signaled Interrupt Upper Address (MSI_MUAD) — Offset 88h.................. 1251
16.33 Message Signaled Interrupt Message Data (MSI_MD) — Offset 8Ch ...................... 1251
16.34 Device Idle Capability (DEVIDLE) — Offset 90h .................................................. 1251
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16.90 Port Power Management Status and Control USB3 (PORTPMSC10)—Offset 514h..... 1288
16.91 USB3 Port Link Info (PORTLI10)—Offset 518h.................................................... 1288
16.92 Port Status and Control USB3 (PORTSC11)—Offset 520h..................................... 1289
16.93 Port Power Management Status and Control USB3 (PORTPMSC11)—Offset 524h..... 1290
16.94 USB3 Port Link Info (PORTLI11)—Offset 528h.................................................... 1290
16.95 Port Status and Control USB3 (PORTSC12)—Offset 530h..................................... 1291
16.96 Port Power Management Status and Control USB3 (PORTPMSC12)—Offset 534h..... 1292
16.97 USB3 Port Link Info (PORTLI12)—Offset 538h.................................................... 1292
16.98 Port Status and Control USB3 (PORTSC13)—Offset 540h..................................... 1293
16.99 Port Power Management Status and Control USB3 (PORTPMSC13)—Offset 544h..... 1294
16.100USB3 Port Link Info (PORTLI13)—Offset 548h ................................................... 1294
16.101Port Status and Control USB3 (PORTSC14)—Offset 550h .................................... 1295
16.102Port Power Management Status and Control USB3 (PORTPMSC14)—Offset 554h .... 1296
16.103USB3 Port Link Info (PORTLI14)—Offset 558h ................................................... 1296
16.104Port Status and Control USB3 (PORTSC15)—Offset 560h .................................... 1297
16.105Port Power Management Status and Control USB3 (PORTPMSC15)—Offset 564h .... 1298
16.106USB3 Port Link Info (PORTLI15)—Offset 568h ................................................... 1298
16.107Port Status and Control USB3 (PORTSC16)—Offset 570h .................................... 1299
16.108Port Power Management Status and Control USB3 (PORTPMSC16)—Offset 574h .... 1300
16.109USB3 Port Link Info (PORTLI16)—Offset 578h ................................................... 1300
16.110Microframe Index (RTMFINDEX)—Offset 2000h ................................................. 1301
16.111Interrupter 1 Management (IMAN0)—Offset 2020h ............................................ 1301
16.112Interrupter 1 Moderation (IMOD0)—Offset 2024h .............................................. 1301
16.113Event Ring Segment Table Size 1 (ERSTSZ0)—Offset 2028h ............................... 1302
16.114Event Ring Segment Table Base Address Low 1 (ERSTBA_LO0)—Offset 2030h....... 1302
16.115Event Ring Segment Table Base Address High 1 (ERSTBA_HI0)—Offset 2034h ...... 1302
16.116Event Ring Dequeue Pointer Low 1 (ERDP_LO0)—Offset 2038h............................ 1303
16.117Event Ring Dequeue Pointer High 1 (ERDP_HI0)—Offset 203Ch ........................... 1303
16.118Interrupter 2 Management (IMAN1)—Offset 2040h ............................................ 1303
16.119Interrupter 2 Moderation (IMOD1)—Offset 2044h .............................................. 1304
16.120Event Ring Segment Table Size 2 (ERSTSZ1)—Offset 2048h ............................... 1304
16.121Event Ring Segment Table Base Address Low 2 (ERSTBA_LO1)—Offset 2050h....... 1305
16.122Event Ring Segment Table Base Address High 2 (ERSTBA_HI1)—Offset 2054h ...... 1305
16.123Event Ring Dequeue Pointer Low 2 (ERDP_LO1)—Offset 2058h............................ 1305
16.124Event Ring Dequeue Pointer High 2 (ERDP_HI1)—Offset 205Ch ........................... 1306
16.125Interrupter 3 Management (IMAN2)—Offset 2060h ............................................ 1306
16.126Interrupter 3 Moderation (IMOD2)—Offset 2064h .............................................. 1306
16.127Event Ring Segment Table Size 3 (ERSTSZ2)—Offset 2068h ............................... 1307
16.128Event Ring Segment Table Base Address Low 3 (ERSTBA_LO2)—Offset 2070h....... 1307
16.129Event Ring Segment Table Base Address High 3 (ERSTBA_HI2)—Offset 2074h ...... 1307
16.130Event Ring Dequeue Pointer Low 3 (ERDP_LO2)—Offset 2078h............................ 1308
16.131Event Ring Dequeue Pointer High 3 (ERDP_HI2)—Offset 207Ch ........................... 1308
16.132Interrupter 4 Management (IMAN3)—Offset 2080h ............................................ 1308
16.133Interrupter 4 Moderation (IMOD3)—Offset 2084h .............................................. 1309
16.134Event Ring Segment Table Size 4 (ERSTSZ3)—Offset 2088h ............................... 1309
16.135Event Ring Segment Table Base Address Low 4 (ERSTBA_LO3)—Offset 2090h....... 1310
16.136Event Ring Segment Table Base Address High 4 (ERSTBA_HI3)—Offset 2094h ...... 1310
16.137Event Ring Dequeue Pointer Low 4 (ERDP_LO3)—Offset 2098h............................ 1310
16.138Event Ring Dequeue Pointer High 4 (ERDP_HI3)—Offset 209Ch ........................... 1311
16.139Interrupter 5 Management (IMAN4)—Offset 20A0h ............................................ 1311
16.140Interrupter 5 Moderation (IMOD4)—Offset 20A4h .............................................. 1311
16.141Event Ring Segment Table Size 5 (ERSTSZ4)—Offset 20A8h ............................... 1312
16.142Event Ring Segment Table Base Address Low 5 (ERSTBA_LO4)—Offset 20B0h ...... 1312
16.143Event Ring Segment Table Base Address High 5 (ERSTBA_HI4)—Offset 20B4h ...... 1312
16.144Event Ring Dequeue Pointer Low 5 (ERDP_LO4)—Offset 20B8h ........................... 1313
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16.200XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)—Offset 8000h ................................ 1334
16.201XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)—Offset 8004h ................................ 1335
16.202XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)—Offset 8008h ................................ 1335
16.203XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset 8010h .............. 1336
16.204XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset 8014h .............. 1336
16.205XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset 8018h ............. 1337
16.206XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)—Offset 8020h ................................ 1337
16.207XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)—Offset 8024h ................................ 1338
16.208XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)—Offset 8028h ................................ 1338
16.209XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)—Offset 8030h ................................ 1339
16.210XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4)—Offset 8034h ................................ 1339
16.211XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5)—Offset 8038h ................................ 1340
16.212XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)—Offset 803Ch ................................ 1340
16.213XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)—Offset 8040h ................................ 1341
16.214XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)—Offset 8044h ................................ 1341
16.215XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)—Offset 8048h ................................ 1342
16.216Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h ....................... 1342
16.217Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h ....................... 1343
16.218Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch ....... 1343
16.219Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h ........................ 1343
16.220Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h .......................... 1344
16.221Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h ............................. 1345
16.222Power Management Control (PMCTRL_REG)—Offset 80A4h ................................. 1345
16.223PGCB Control (PGCBCTRL_REG)—Offset 80A8h ................................................. 1347
16.224D0I3 Control (DOI3CTRL_REG)—Offset 80ACh .................................................. 1350
16.225HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG)—Offset 80B0h........................ 1351
16.226HOST_CTRL_MISC_REG2 (HOST_CTRL_MISC_REG2)—Offset 80B4h .................... 1352
16.227SSPE_REG (SSPE_REG)—Offset 80B8h............................................................. 1353
16.228(SSPITPE)—Offset 80BCh ............................................................................... 1353
16.229AUX Reset Control (AUX_CTRL_REG)—Offset 80C0h .......................................... 1354
16.230Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—Offset 80C4h .......... 1356
16.231High Speed TT Bandwidth Overload (HOST_BW_OV_HS_REG)—Offset 80C8h........ 1356
16.232Bandwidth Overload Full Low Speed (HOST_BW_OV_FS_LS_REG)—Offset 80CCh .. 1357
16.233System Bandwidth Overload (HOST_BW_OV_SYS_REG)—Offset 80D0h ................ 1357
16.234Scheduler Async Delay (HOST_CTRL_SCH_ASYNC_DELAY_REG)—Offset 80D4h..... 1358
16.235DEVICE MODE CONTROL REG 0 (DUAL_ROLE_CFG_REG0)—Offset 80D8h............. 1358
16.236DEVICE MODE CONTROL REG 1 (DUAL_ROLE_CFG_REG1)—Offset 80DCh............. 1360
16.237AUX Power Management Control (AUX_CTRL_REG1)—Offset 80E0h ..................... 1361
16.238Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h.................................... 1363
16.239Port Watermark (HOST_CTRL_WATERMARK_REG)—Offset 80E8h ........................ 1363
16.240SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—Offset 80ECh ....... 1364
16.241USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)—Offset 80F0h .............. 1365
16.242USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—Offset 80F4h .............. 1367
16.243USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—Offset 80F8h .............. 1367
16.244USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—Offset 80FCh.............. 1368
16.245Bandwidth Calc Control (HOST_CTRL_BW_CTRL_REG)—Offset 8100h................... 1368
16.246Host Interface Control (HOST_IF_CTRL_REG)—Offset 8108h ............................... 1368
16.247Bandwidth Overload Burst (HOST_BW_OV_BURST_REG)—Offset 810Ch ............... 1369
16.248USB Max Bandwidth Control 4 (HOST_CTRL_BW_MAX_REG)—Offset 8128h .......... 1369
16.249USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h......................... 1370
16.250USB2 Protocol Gap Timer (USB2_PROTOCOL_GAP_TIMER_REG)—Offset 8134h ..... 1371
16.251USB2 Protocol Bus Timeout Timer (USB2_PROTOCOL_BTO_TIMER_REG)—Offset 813Ch
1371
16.252Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset 8140h......................... 1372
16.253Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset 8144h......................... 1372
36 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 37
16.306HW state register 3 (HW_STATE_REG3)—Offset 850Ch ...................................... 1405
16.307HW state register 4 (HW_STATE_REG4)—Offset 8510h ...................................... 1406
16.308CONFIG mirror capability register (CONFIG_MIRROR_CAPABILITY)—Offset 8600h.. 1406
16.309Command (CMD_MMIO)—Offset 8604h ............................................................ 1406
16.310Device Status (STS_MMIO)—Offset 8606h ........................................................ 1407
16.311Revision ID (RID_MMIO)—Offset 8608h ........................................................... 1408
16.312Programming Interface (PI_MMIO)—Offset 8609h.............................................. 1409
16.313Sub Class Code (SCC_MMIO)—Offset 860Ah ..................................................... 1409
16.314Base Class Code (BCC_MMIO)—Offset 860Bh .................................................... 1409
16.315Master Latency Timer (MLT_MMIO)—Offset 860Dh............................................. 1410
16.316Header Type (HT_MMIO)—Offset 860Eh ........................................................... 1410
16.317Memory Base Address (MBAR_MMIO)—Offset 8610h.......................................... 1410
16.318USB Subsystem Vendor ID (SSVID_MMIO)—Offset 862Ch .................................. 1411
16.319USB Subsystem ID (SSID_MMIO)—Offset 862Eh ............................................... 1411
16.320Capabilities Pointer (CAP_PTR_MMIO)—Offset 8634h ......................................... 1412
16.321Interrupt Line (ILINE_MMIO)—Offset 863Ch ..................................................... 1412
16.322Interrupt Pin (IPIN_MMIO)—Offset 863Dh ........................................................ 1412
16.323XHC System Bus Configuration 1 (XHCC1_MMIO)—Offset 8640h ......................... 1413
16.324XHC System Bus Configuration 2 (XHCC2_MMIO)—Offset 8644h ......................... 1414
16.325Clock Gating (XHCLKGTEN_MMIO)—Offset 8650h .............................................. 1416
16.326Audio Time Synchronization (AUDSYNC_MMIO)—Offset 8658h ............................ 1419
16.327Serial Bus Release Number (SBRN_MMIO)—Offset 8660h ................................... 1420
16.328Frame Length Adjustment (FLADJ_MMIO)—Offset 8661h .................................... 1420
16.329Best Effort Service Latency (BESL_MMIO)—Offset 8662h .................................... 1421
16.330PCI Power Management Capability ID (PM_CID_MMIO)—Offset 8670h.................. 1421
16.331Next Item Pointer #1 (PM_NEXT_MMIO)—Offset 8671h...................................... 1421
16.332Power Management Capabilities (PM_CAP_MMIO)—Offset 8672h ......................... 1422
16.333Power Management Control/Status (PM_CS_MMIO)—Offset 8674h....................... 1423
16.334Message Signaled Interrupt CID (MSI_CID_MMIO)—Offset 8680h ........................ 1424
16.335Next item pointer (MSI_NEXT_MMIO)—Offset 8681h.......................................... 1424
16.336Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)—Offset 8682h .... 1424
16.337Message Signaled Interrupt Message Address (MSI_MAD_MMIO)—Offset 8684h .... 1425
16.338Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)—Offset 8688h...... 1425
16.339Message Signaled Interrupt Message Data (MSI_MD_MMIO)—Offset 868Ch .......... 1426
16.340Device Idle Capability (DEVIDLE_MMIO)—Offset 8690h ...................................... 1426
16.341Vendor Specific Header (VSHDR_MMIO)—Offset 8694h ...................................... 1427
16.342SW LTR POINTER (SWLTRPTR_MMIO)—Offset 8698h ......................................... 1427
16.343Device Idle Pointer Register (DEVIDLEPTR_MMIO)—Offset 869Ch ........................ 1428
16.344Device Idle Power ON Latency (DEVIDLEPOL_MMIO)—Offset 86A0h ..................... 1429
16.345High Speed Configuration 2 (HSCFG2_MMIO)—Offset 86A4h ............................... 1429
16.346XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1_MMIO)—Offset 86B0h ............... 1431
16.347XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2_MMIO)—Offset 86B4h ............... 1431
16.348XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1_MMIO)—Offset 86D0h............... 1431
16.349XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2_MMIO)—Offset 86D4h............... 1432
16.350XHCC3 (XHCC3_MMIO)—Offset 86FCh ............................................................. 1432
16.351Debug Capability ID Register (DCID)—Offset 8700h........................................... 1433
16.352Debug Capability Doorbell Register (DCDB)—Offset 8704h .................................. 1433
16.353Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)—Offset 8708h ..
1434
16.354Debug Capability Event Ring Segment Table Base Address Register (DCERSTBA)—Offset
8710h .......................................................................................................... 1434
16.355Debug Capability Event Ring Dequeue Pointer Register (DCERDP)—Offset 8718h ... 1435
16.356Debug Capability Control Register (DCCTRL)—Offset 8720h ................................ 1435
16.357Debug Capability Status Register (DCST)—Offset 8724h ..................................... 1436
16.358Debug Capability Port Status and Control Register (DCPORTSC)—Offset 8728h...... 1436
38 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 39
16.409(PORT1_PROFILE_ATTRIBUTES_REG32)—Offset 898Ch ...................................... 1466
16.410(PORT1_PROFILE_ATTRIBUTES_REG33)—Offset 8990h ...................................... 1466
16.411(PORT1_PROFILE_ATTRIBUTES_REG34)—Offset 8994h ...................................... 1467
16.412(PORT1_PROFILE_ATTRIBUTES_REG35)—Offset 8998h ...................................... 1467
16.413(PORT1_PROFILE_ATTRIBUTES_REG36)—Offset 899Ch ...................................... 1468
16.414(PORT1_PROFILE_ATTRIBUTES_REG37)—Offset 89A0h ...................................... 1468
16.415(PORT1_PROFILE_ATTRIBUTES_REG38)—Offset 89A4h ...................................... 1469
16.416(PORT1_PROFILE_ATTRIBUTES_REG39)—Offset 89A8h ...................................... 1469
16.417(PORT1_PROFILE_ATTRIBUTES_REG40)—Offset 89ACh...................................... 1470
16.418(PORT1_PROFILE_ATTRIBUTES_REG41)—Offset 89B0h ...................................... 1470
16.419(PORT1_PROFILE_ATTRIBUTES_REG42)—Offset 89B4h ...................................... 1471
16.420(PORT1_PROFILE_ATTRIBUTES_REG43)—Offset 89B8h ...................................... 1471
16.421(PORT1_PROFILE_ATTRIBUTES_REG44)—Offset 89BCh...................................... 1472
16.422(PORT1_PROFILE_ATTRIBUTES_REG45)—Offset 89C0h ...................................... 1472
16.423(PORT1_PROFILE_ATTRIBUTES_REG46)—Offset 89C4h ...................................... 1473
16.424(PORT1_PROFILE_ATTRIBUTES_REG47)—Offset 89C8h ...................................... 1473
16.425(PORT1_PROFILE_ATTRIBUTES_REG48)—Offset 89CCh...................................... 1474
16.426(PORT1_PROFILE_ATTRIBUTES_REG49)—Offset 89D0h...................................... 1474
16.427(PORT1_PROFILE_ATTRIBUTES_REG50)—Offset 89D4h...................................... 1475
16.428(PORT1_PROFILE_ATTRIBUTES_REG51)—Offset 89D8h...................................... 1475
16.429(PORT1_PROFILE_ATTRIBUTES_REG52)—Offset 89DCh...................................... 1476
16.430(PORT1_PROFILE_ATTRIBUTES_REG53)—Offset 89E0h ...................................... 1476
16.431(PORT1_PROFILE_ATTRIBUTES_REG54)—Offset 89E4h ...................................... 1477
16.432(PORT1_PROFILE_ATTRIBUTES_REG55)—Offset 89E8h ...................................... 1477
16.433(PORT1_PROFILE_ATTRIBUTES_REG56)—Offset 89ECh ...................................... 1478
16.434(PORT1_PROFILE_ATTRIBUTES_REG57)—Offset 89F0h ...................................... 1478
16.435(PORT1_PROFILE_ATTRIBUTES_REG58)—Offset 89F4h ...................................... 1479
16.436(PORT1_PROFILE_ATTRIBUTES_REG59)—Offset 89F8h ...................................... 1479
16.437(PORT1_PROFILE_ATTRIBUTES_REG60)—Offset 89FCh ...................................... 1480
16.438(PORT1_PROFILE_ATTRIBUTES_REG61)—Offset 8A00h ...................................... 1480
16.439(PORT1_PROFILE_ATTRIBUTES_REG62)—Offset 8A04h ...................................... 1481
16.440(PORT1_PROFILE_ATTRIBUTES_REG63)—Offset 8A08h ...................................... 1481
16.441GLOBAL_TIME_SYNC_CAP_REG (GLOBAL_TIME_SYNC_CAP_REG)—Offset 8E10h... 1482
16.442GLOBAL_TIME_SYNC_CTRL_REG (GLOBAL_TIME_SYNC_CTRL_REG)—Offset 8E14h 1482
16.443MICROFRAME_TIME_REG (MICROFRAME_TIME_REG)—Offset 8E18h .................... 1482
16.444GLOBAL_TIME_LOW_REG (GLOBAL_TIME_LOW_REG)—Offset 8E20h ................... 1483
16.445GLOBAL_TIME_HI_REG (GLOBAL_TIME_HI_REG)—Offset 8E24h.......................... 1483
16.446Debug Status Capability Register (DEBUG_STATUS_CAPABILITY_REG)—Offset 8E58h ...
1484
16.447Host Ctrl USB3 Soft Error Count Register 1 (HOST_CTRL_USB3_ERR_COUNT_REG1)—
Offset 8E5Ch................................................................................................. 1484
16.448Host Ctrl USB3 Soft Error Count Register 2 (HOST_CTRL_USB3_ERR_COUNT_REG2)—
Offset 8E60h ................................................................................................. 1484
16.449Host Ctrl USB3 Soft Error Count Register 3 (HOST_CTRL_USB3_ERR_COUNT_REG3)—
Offset 8E64h ................................................................................................. 1485
16.450Host Ctrl USB3 Soft Error Count Register 4 (HOST_CTRL_USB3_ERR_COUNT_REG4)—
Offset 8E68h ................................................................................................. 1485
16.451Host Ctrl USB3 Soft Error Count Register 5 (HOST_CTRL_USB3_ERR_COUNT_REG5)—
Offset 8E6Ch................................................................................................. 1486
16.452Host Ctrl USB3 Soft Error Count Register 6 (HOST_CTRL_USB3_ERR_COUNT_REG6)—
Offset 8E70h ................................................................................................. 1486
16.453Host Ctrl USB3 Soft Error Count Register 7 (HOST_CTRL_USB3_ERR_COUNT_REG7)—
Offset 8E74h ................................................................................................. 1486
16.454DBC_GP2_OUT_PAYLOAD_BP_LOW (DBC_GP2_OUT_PAYLOAD_BP_LOW)—Offset 0h ....
1487
40 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 41
16.494DEBUG_REQUEST_INFO_AND_STATUS_REG (DEBUG_REQUEST_INFO_AND_STA-
TUS_REG)—Offset 104h ................................................................................. 1508
16.495DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_0)—Offset 108h ......... 1509
16.496DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_1)—Offset 10Ch ......... 1509
16.497DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_2)—Offset 110h ......... 1510
16.498DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_3)—Offset 114h ......... 1510
16.499DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_4)—Offset 118h ......... 1510
16.500DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_5)—Offset 11Ch ......... 1511
16.501DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_6)—Offset 120h ......... 1511
16.502DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_7)—Offset 124h ......... 1511
16.503DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_8)—Offset 128h ......... 1512
16.504DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_9)—Offset 12Ch ......... 1512
16.505DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_10)—Offset 130h ....... 1512
16.506DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_11)—Offset 134h ....... 1513
16.507DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_12)—Offset 138h ....... 1513
16.508DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_13)—Offset 13Ch ....... 1513
16.509DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_14)—Offset 140h ....... 1514
16.510DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_15)—Offset 144h ....... 1514
16.511DEBUG_RESPONSE_INFO_AND_STATUS_REG (DEBUG_RESPONSE_INFO_AND_STA-
TUS_REG)—Offset 148h ................................................................................. 1514
16.512DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_0)—Offset
180h ............................................................................................................ 1515
16.513DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_1)—Offset
184h ............................................................................................................ 1515
16.514DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_2)—Offset
188h ............................................................................................................ 1515
16.515DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_3)—Offset
18Ch............................................................................................................ 1516
16.516DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_4)—Offset
190h ............................................................................................................ 1516
16.517DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_5)—Offset
194h ............................................................................................................ 1516
16.518DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_6)—Offset
198h ............................................................................................................ 1517
16.519DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_7)—Offset
19Ch............................................................................................................ 1517
16.520DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_8)—Offset
1A0h............................................................................................................ 1517
16.521DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_9)—Offset
1A4h............................................................................................................ 1518
16.522DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_10)—Offset
1A8h............................................................................................................ 1518
16.523DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_11)—Offset
1ACh ........................................................................................................... 1518
16.524DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_12)—Offset
1B0h............................................................................................................ 1519
16.525DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_13)—Offset
1B4h............................................................................................................ 1519
16.526DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_14)—Offset
1B8h............................................................................................................ 1519
16.527DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_15)—Offset
1BCh ........................................................................................................... 1520
16.528DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_16)—Offset
1C0h............................................................................................................ 1520
16.529DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_17)—Offset
1C4h............................................................................................................ 1520
42 Datasheet Volume 2 of 2
16.530DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_18)—Offset
1C8h ............................................................................................................1521
16.531DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_19)—Offset
1CCh ............................................................................................................1521
16.532DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_20)—Offset
1D0h ............................................................................................................1521
16.533DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_21)—Offset
1D4h ............................................................................................................1522
16.534DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_22)—Offset
1D8h ............................................................................................................1522
16.535DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_23)—Offset
1DCh ............................................................................................................1522
16.536DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_24)—Offset
1E0h ............................................................................................................1523
16.537DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_25)—Offset
1E4h ............................................................................................................1523
16.538DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_26)—Offset
1E8h ............................................................................................................1523
16.539DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_27)—Offset
1ECh ............................................................................................................1524
16.540DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_28)—Offset
1F0h.............................................................................................................1524
16.541DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_29)—Offset
1F4h.............................................................................................................1524
16.542DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_30)—Offset
1F8h.............................................................................................................1525
16.543DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_31)—Offset
1FCh ............................................................................................................1525
16.544DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_32)—Offset
200h ............................................................................................................1525
16.545DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_33)—Offset
204h ............................................................................................................1526
16.546DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_34)—Offset
208h ............................................................................................................1526
16.547DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_35)—Offset
20Ch ............................................................................................................1526
16.548DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_36)—Offset
210h ............................................................................................................1527
16.549DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_37)—Offset
214h ............................................................................................................1527
16.550DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_38)—Offset
218h ............................................................................................................1527
16.551DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_39)—Offset
21Ch ............................................................................................................1528
16.552DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_40)—Offset
220h ............................................................................................................1528
16.553DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_41)—Offset
224h ............................................................................................................1528
16.554DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_42)—Offset
228h ............................................................................................................1529
16.555DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_43)—Offset
22Ch ............................................................................................................1529
16.556DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_44)—Offset
230h ............................................................................................................1529
16.557DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_45)—Offset
234h ............................................................................................................1530
16.558DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_46)—Offset
Datasheet Volume 2 of 2 43
238h ............................................................................................................ 1530
16.559DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_47)—Offset
23Ch............................................................................................................ 1530
16.560DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_48)—Offset
240h ............................................................................................................ 1531
16.561DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_49)—Offset
244h ............................................................................................................ 1531
16.562DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_50)—Offset
248h ............................................................................................................ 1531
16.563DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_51)—Offset
24Ch............................................................................................................ 1532
16.564DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_52)—Offset
250h ............................................................................................................ 1532
16.565DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_53)—Offset
254h ............................................................................................................ 1532
16.566DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_54)—Offset
258h ............................................................................................................ 1533
16.567DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_55)—Offset
25Ch............................................................................................................ 1533
16.568DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_56)—Offset
260h ............................................................................................................ 1533
16.569DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_57)—Offset
264h ............................................................................................................ 1534
16.570DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_58)—Offset
268h ............................................................................................................ 1534
16.571DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_59)—Offset
26Ch............................................................................................................ 1534
16.572DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_60)—Offset
270h ............................................................................................................ 1535
16.573DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_61)—Offset
274h ............................................................................................................ 1535
16.574DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_62)—Offset
278h ............................................................................................................ 1535
16.575DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_63)—Offset
27Ch............................................................................................................ 1536
16.576DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_64)—Offset
280h ............................................................................................................ 1536
16.577DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_65)—Offset
284h ............................................................................................................ 1536
16.578DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_66)—Offset
288h ............................................................................................................ 1537
16.579DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_67)—Offset
28Ch............................................................................................................ 1537
16.580DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_68)—Offset
290h ............................................................................................................ 1537
16.581DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_69)—Offset
294h ............................................................................................................ 1538
16.582DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_70)—Offset
298h ............................................................................................................ 1538
16.583DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_71)—Offset
29Ch............................................................................................................ 1538
16.584DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_72)—Offset
2A0h............................................................................................................ 1539
16.585DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_73)—Offset
2A4h............................................................................................................ 1539
16.586DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_74)—Offset
2A8h............................................................................................................ 1539
44 Datasheet Volume 2 of 2
16.587DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_75)—Offset
2ACh ............................................................................................................1540
16.588DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_76)—Offset
2B0h ............................................................................................................1540
16.589DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_77)—Offset
2B4h ............................................................................................................1540
16.590DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_78)—Offset
2B8h ............................................................................................................1541
16.591DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_79)—Offset
2BCh ............................................................................................................1541
16.592DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_80)—Offset
2C0h ............................................................................................................1541
16.593DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_81)—Offset
2C4h ............................................................................................................1542
16.594DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_82)—Offset
2C8h ............................................................................................................1542
16.595DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_83)—Offset
2CCh ............................................................................................................1542
16.596DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_84)—Offset
2D0h ............................................................................................................1543
16.597DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_85)—Offset
2D4h ............................................................................................................1543
16.598DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_86)—Offset
2D8h ............................................................................................................1543
16.599DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_87)—Offset
2DCh ............................................................................................................1544
16.600DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_88)—Offset
2E0h ............................................................................................................1544
16.601DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_89)—Offset
2E4h ............................................................................................................1544
16.602DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_90)—Offset
2E8h ............................................................................................................1545
16.603DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_91)—Offset
2ECh ............................................................................................................1545
16.604DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_92)—Offset
2F0h.............................................................................................................1545
16.605DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_93)—Offset
2F4h.............................................................................................................1546
16.606DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_94)—Offset
2F8h.............................................................................................................1546
16.607DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_95)—Offset
2FCh ............................................................................................................1546
16.608DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_96)—Offset
300h ............................................................................................................1547
16.609DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_97)—Offset
304h ............................................................................................................1547
16.610DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_98)—Offset
308h ............................................................................................................1547
16.611DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_99)—Offset
30Ch ............................................................................................................1548
16.612DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_100)—Off-
set 310h .......................................................................................................1548
16.613DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_101)—Off-
set 314h .......................................................................................................1549
16.614DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_102)—Off-
set 318h .......................................................................................................1549
16.615DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_103)—Off-
Datasheet Volume 2 of 2 45
set 31Ch ...................................................................................................... 1549
16.616DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_104)—Off-
set 320h....................................................................................................... 1550
16.617DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_105)—Off-
set 324h....................................................................................................... 1550
16.618DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_106)—Off-
set 328h....................................................................................................... 1550
16.619DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_107)—Off-
set 32Ch ...................................................................................................... 1551
16.620DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_108)—Off-
set 330h....................................................................................................... 1551
16.621DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_109)—Off-
set 334h....................................................................................................... 1552
16.622DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_110)—Off-
set 338h....................................................................................................... 1552
16.623DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_111)—Off-
set 33Ch ...................................................................................................... 1552
16.624DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_112)—Off-
set 340h....................................................................................................... 1553
16.625DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_113)—Off-
set 344h....................................................................................................... 1553
16.626DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_114)—Off-
set 348h....................................................................................................... 1553
16.627DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_115)—Off-
set 34Ch ...................................................................................................... 1554
16.628DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_116)—Off-
set 350h....................................................................................................... 1554
16.629DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_117)—Off-
set 354h....................................................................................................... 1555
16.630DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_118)—Off-
set 358h....................................................................................................... 1555
16.631DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_119)—Off-
set 35Ch ...................................................................................................... 1555
16.632DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_120)—Off-
set 360h....................................................................................................... 1556
16.633DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_121)—Off-
set 364h....................................................................................................... 1556
16.634DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_122)—Off-
set 368h....................................................................................................... 1556
16.635DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_123)—Off-
set 36Ch ...................................................................................................... 1557
16.636DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_124)—Off-
set 370h....................................................................................................... 1557
16.637DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_125)—Off-
set 374h....................................................................................................... 1558
16.638DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_126)—Off-
set 378h....................................................................................................... 1558
16.639DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_127)—Off-
set 37Ch ...................................................................................................... 1558
16.640DEBUG_RESPONSE_HEADER_STACK_REG (DEBUG_RESPONSE_HEAD-
ER_STACK_REG_0)—Offset 380h ..................................................................... 1559
16.641DEBUG_RESPONSE_HEADER_STACK_REG (DEBUG_RESPONSE_HEAD-
ER_STACK_REG_1)—Offset 384h ..................................................................... 1559
16.642DEBUG_RESPONSE_HEADER_STACK_REG (DEBUG_RESPONSE_HEAD-
ER_STACK_REG_2)—Offset 388h ..................................................................... 1559
16.643Vendor ID (VID)—Offset 0h ............................................................................ 1560
16.644Device ID (DID)—Offset 2h ............................................................................ 1560
46 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 47
16.700Command Ring High (CRCR_HI)—Offset 9Ch .................................................... 1592
16.701Device Context Base Address Array Pointer Low (DCBAAP_LO)—Offset B0h........... 1592
16.702Device Context Base Address Array Pointer High (DCBAAP_HI)—Offset B4h .......... 1592
16.703Configure (CONFIG)—Offset B8h ..................................................................... 1593
16.704Port Status and Control USB2 (PORTSC1)—Offset 480h ...................................... 1593
16.705Port Power Management Status and Control USB2 (PORTPMSC1)—Offset 484h...... 1594
16.706Port X Hardware LPM Control Register (PORTHLPMC1)—Offset 48Ch..................... 1595
16.707Port Status and Control USB2 (PORTSC2)—Offset 490h ...................................... 1596
16.708Port Power Management Status and Control USB2 (PORTPMSC2)—Offset 494h...... 1597
16.709Port X Hardware LPM Control Register (PORTHLPMC2)—Offset 49Ch..................... 1598
16.710Port Status and Control USB2 (PORTSC3)—Offset 4A0h...................................... 1598
16.711Port Power Management Status and Control USB2 (PORTPMSC3)—Offset 4A4h...... 1600
16.712Port X Hardware LPM Control Register (PORTHLPMC3)—Offset 4ACh .................... 1600
16.713Port Status and Control USB2 (PORTSC4)—Offset 4B0h...................................... 1601
16.714Port Power Management Status and Control USB2 (PORTPMSC4)—Offset 4B4h...... 1602
16.715Port X Hardware LPM Control Register (PORTHLPMC4)—Offset 4BCh .................... 1603
16.716Port Status and Control USB2 (PORTSC5)—Offset 4C0h...................................... 1603
16.717Port Power Management Status and Control USB2 (PORTPMSC5)—Offset 4C4h...... 1605
16.718Port X Hardware LPM Control Register (PORTHLPMC5)—Offset 4CCh .................... 1605
16.719Port Status and Control USB2 (PORTSC6)—Offset 4D0h...................................... 1606
16.720Port Power Management Status and Control USB2 (PORTPMSC6)—Offset 4D4h ..... 1607
16.721Port X Hardware LPM Control Register (PORTHLPMC6)—Offset 4DCh .................... 1608
16.722Port Status and Control USB2 (PORTSC7)—Offset 4E0h ...................................... 1609
16.723Port Power Management Status and Control USB2 (PORTPMSC7)—Offset 4E4h ...... 1610
16.724Port X Hardware LPM Control Register (PORTHLPMC7)—Offset 4ECh..................... 1611
16.725Port Status and Control USB2 (PORTSC8)—Offset 4F0h ...................................... 1611
16.726Port Power Management Status and Control USB2 (PORTPMSC8)—Offset 4F4h ...... 1613
16.727Port X Hardware LPM Control Register (PORTHLPMC8)—Offset 4FCh..................... 1613
16.728Port Status and Control USB2 (PORTSC9)—Offset 500h ...................................... 1614
16.729Port Power Management Status and Control USB2 (PORTPMSC9)—Offset 504h...... 1615
16.730Port X Hardware LPM Control Register (PORTHLPMC9)—Offset 50Ch..................... 1616
16.731Port Status and Control USB3 (PORTSC10)—Offset 510h .................................... 1616
16.732Port Power Management Status and Control USB3 (PORTPMSC10)—Offset 514h .... 1618
16.733USB3 Port Link Info (PORTLI10)—Offset 518h ................................................... 1618
16.734Port Status and Control USB3 (PORTSC11)—Offset 520h .................................... 1618
16.735Port Power Management Status and Control USB3 (PORTPMSC11)—Offset 524h .... 1620
16.736USB3 Port Link Info (PORTLI11)—Offset 528h ................................................... 1620
16.737Port Status and Control USB3 (PORTSC12)—Offset 530h .................................... 1620
16.738Port Power Management Status and Control USB3 (PORTPMSC12)—Offset 534h .... 1622
16.739USB3 Port Link Info (PORTLI12)—Offset 538h ................................................... 1622
16.740Port Status and Control USB3 (PORTSC13)—Offset 540h .................................... 1622
16.741Port Power Management Status and Control USB3 (PORTPMSC13)—Offset 544h .... 1624
16.742USB3 Port Link Info (PORTLI13)—Offset 548h ................................................... 1624
16.743Port Status and Control USB3 (PORTSC14)—Offset 550h .................................... 1624
16.744Port Power Management Status and Control USB3 (PORTPMSC14)—Offset 554h .... 1626
16.745USB3 Port Link Info (PORTLI14)—Offset 558h ................................................... 1626
16.746Port Status and Control USB3 (PORTSC15)—Offset 560h .................................... 1626
16.747Port Power Management Status and Control USB3 (PORTPMSC15)—Offset 564h .... 1628
16.748USB3 Port Link Info (PORTLI15)—Offset 568h ................................................... 1628
16.749Port Status and Control USB3 (PORTSC16)—Offset 570h .................................... 1628
16.750Port Power Management Status and Control USB3 (PORTPMSC16)—Offset 574h .... 1630
16.751USB3 Port Link Info (PORTLI16)—Offset 578h ................................................... 1630
16.752Microframe Index (RTMFINDEX)—Offset 2000h ................................................. 1630
16.753Interrupter 1 Management (IMAN0)—Offset 2020h ............................................ 1631
16.754Interrupter 1 Moderation (IMOD0)—Offset 2024h .............................................. 1631
48 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 49
16.810Door Bell 2 (DB1)—Offset 3004h ..................................................................... 1651
16.811Door Bell 3 (DB2)—Offset 3008h ..................................................................... 1652
16.812Door Bell 4 (DB3)—Offset 300Ch ..................................................................... 1652
16.813Door Bell 5 (DB4)—Offset 3010h ..................................................................... 1653
16.814Door Bell 6 (DB5)—Offset 3014h ..................................................................... 1653
16.815Door Bell 7 (DB6)—Offset 3018h ..................................................................... 1654
16.816Door Bell 8 (DB7)—Offset 301Ch ..................................................................... 1654
16.817Door Bell 9 (DB8)—Offset 3020h ..................................................................... 1654
16.818Door Bell 10 (DB9)—Offset 3024h ................................................................... 1655
16.819Door Bell 11 (DB10)—Offset 3028h ................................................................. 1655
16.820Door Bell 12 (DB11)—Offset 302Ch ................................................................. 1656
16.821Door Bell 13 (DB12)—Offset 3030h ................................................................. 1656
16.822Door Bell 14 (DB13)—Offset 3034h ................................................................. 1656
16.823Door Bell 15 (DB14)—Offset 3038h ................................................................. 1657
16.824Door Bell 16 (DB15)—Offset 303Ch ................................................................. 1657
16.825Door Bell 17 (DB16)—Offset 3040h ................................................................. 1658
16.826Door Bell 18 (DB17)—Offset 3044h ................................................................. 1658
16.827Door Bell 19 (DB18)—Offset 3048h ................................................................. 1658
16.828Door Bell 20 (DB19)—Offset 304Ch ................................................................. 1659
16.829Door Bell 21 (DB20)—Offset 3050h ................................................................. 1659
16.830Door Bell 22 (DB21)—Offset 3054h ................................................................. 1660
16.831Door Bell 23 (DB22)—Offset 3058h ................................................................. 1660
16.832Door Bell 24 (DB23)—Offset 305Ch ................................................................. 1660
16.833Door Bell 25 (DB24)—Offset 3060h ................................................................. 1661
16.834Door Bell 26 (DB25)—Offset 3064h ................................................................. 1661
16.835Door Bell 27 (DB26)—Offset 3068h ................................................................. 1662
16.836Door Bell 28 (DB27)—Offset 306Ch ................................................................. 1662
16.837Door Bell 29 (DB28)—Offset 3070h ................................................................. 1662
16.838Door Bell 30 (DB29)—Offset 3074h ................................................................. 1663
16.839Door Bell 31 (DB30)—Offset 3078h ................................................................. 1663
16.840Door Bell 32 (DB31)—Offset 307Ch ................................................................. 1664
16.841Door Bell 32 (DB32)—Offset 3080h ................................................................. 1664
16.842XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)—Offset 8000h ................................ 1664
16.843XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)—Offset 8004h ................................ 1665
16.844XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)—Offset 8008h ................................ 1665
16.845XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset 8010h .............. 1666
16.846XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset 8014h .............. 1666
16.847XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset 8018h ............. 1667
16.848XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)—Offset 8020h ................................ 1667
16.849XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)—Offset 8024h ................................ 1668
16.850XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)—Offset 8028h ................................ 1668
16.851XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)—Offset 8030h ................................ 1669
16.852XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4)—Offset 8034h ................................ 1669
16.853XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5)—Offset 8038h ................................ 1670
16.854XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)—Offset 803Ch ................................ 1670
16.855XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)—Offset 8040h ................................ 1671
16.856XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)—Offset 8044h ................................ 1671
16.857XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)—Offset 8048h ................................ 1672
16.858Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h ....................... 1672
16.859Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h ....................... 1673
16.860Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch ....... 1673
16.861Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h ........................ 1673
16.862Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h .......................... 1674
16.863Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h ............................. 1675
16.864Power Management Control (PMCTRL_REG)—Offset 80A4h ................................. 1675
50 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 51
16.916ECC_PARITY_ERROR_LOG_REG (ECC_PARITY_ERROR_LOG_REG)—Offset 83F8h... 1718
16.917ECC_POISONING_CTRL_REG (ECC_POISONING_CTRL_REG)—Offset 83FCh .......... 1720
16.918USB2_PORT_STATE_REG (USB2_PORT_STATE_REG)—Offset 8400h .................... 1721
16.919USB3_PORT_STATE_REG (USB3_PORT_STATE_REG)—Offset 8408h .................... 1721
16.920FUS1_REG (FUS1_REG)—Offset 8410h............................................................. 1722
16.921FUS2_REG (FUS2_REG)—Offset 8414h............................................................. 1723
16.922FUS3_REG (FUS3_REG)—Offset 8418h............................................................. 1723
16.923STRAP1_REG (STRAP1_REG)—Offset 841Ch ..................................................... 1723
16.924STRAP2_REG (STRAP2_REG)—Offset 8420h ..................................................... 1724
16.925STRAP3_REG (STRAP3_REG)—Offset 8424h ..................................................... 1724
16.926DFT_REG1 (DFT_REG1)—Offset 8430h............................................................. 1725
16.927DFT_REG2 (DFT_REG2)—Offset 8434h............................................................. 1725
16.928DFT_REG3 (DFT_REG3)—Offset 8438h............................................................. 1726
16.929dft_reg4 (DFT_REG4)—Offset 843Ch ............................................................... 1727
16.930dft_reg5 (DFT_REG5)—Offset 8440h................................................................ 1727
16.931XECP_CMDM_STS0 (XECP_CMDM_STS0)—Offset 8448h ..................................... 1728
16.932XECP_CMDM_STS1 (XECP_CMDM_STS1)—Offset 844Ch ..................................... 1729
16.933XECP_CMDM_STS2 (XECP_CMDM_STS2)—Offset 8450h ..................................... 1730
16.934XECP_CMDM_STS3 (XECP_CMDM_STS3)—Offset 8454h ..................................... 1730
16.935XECP_CMDM_STS4 (XECP_CMDM_STS4)—Offset 8458h ..................................... 1730
16.936XECP_CMDM_STS5 (XECP_CMDM_STS5)—Offset 845Ch ..................................... 1730
16.937AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 8460h .......................... 1731
16.938Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—Offset 8464h ....... 1731
16.939USB Legacy Support Capability (USBLEGSUP)—Offset 846Ch .............................. 1732
16.940USB Legacy Support Control Status (USBLEGCTLSTS)—Offset 8470h ................... 1733
16.941Port Disable Override capability register (PDO_CAPABILITY)—Offset 84F4h ........... 1733
16.942USB2 Port Disable Override (USB2PDO)—Offset 84F8h ....................................... 1734
16.943USB3 Port Disable Override (USB3PDO)—Offset 84FCh....................................... 1734
16.944HW state capability register (HW_STATE_CAPABILITY)—Offset 8500h .................. 1734
16.945HW state register 1 (HW_STATE_REG1)—Offset 8504h ...................................... 1735
16.946HW state register 2 (HW_STATE_REG2)—Offset 8508h ...................................... 1735
16.947HW state register 3 (HW_STATE_REG3)—Offset 850Ch ...................................... 1735
16.948HW state register 4 (HW_STATE_REG4)—Offset 8510h ...................................... 1736
16.949CONFIG mirror capability register (CONFIG_MIRROR_CAPABILITY)—Offset 8600h.. 1736
16.950Command (CMD_MMIO)—Offset 8604h ............................................................ 1736
16.951Device Status (STS_MMIO)—Offset 8606h ........................................................ 1737
16.952Revision ID (RID_MMIO)—Offset 8608h ........................................................... 1738
16.953Programming Interface (PI_MMIO)—Offset 8609h.............................................. 1739
16.954Sub Class Code (SCC_MMIO)—Offset 860Ah ..................................................... 1739
16.955Base Class Code (BCC_MMIO)—Offset 860Bh .................................................... 1739
16.956Master Latency Timer (MLT_MMIO)—Offset 860Dh............................................. 1740
16.957Header Type (HT_MMIO)—Offset 860Eh ........................................................... 1740
16.958Memory Base Address (MBAR_MMIO)—Offset 8610h.......................................... 1740
16.959USB Subsystem Vendor ID (SSVID_MMIO)—Offset 862Ch .................................. 1741
16.960USB Subsystem ID (SSID_MMIO)—Offset 862Eh ............................................... 1741
16.961Capabilities Pointer (CAP_PTR_MMIO)—Offset 8634h ......................................... 1742
16.962Interrupt Line (ILINE_MMIO)—Offset 863Ch ..................................................... 1742
16.963Interrupt Pin (IPIN_MMIO)—Offset 863Dh ........................................................ 1742
16.964XHC System Bus Configuration 1 (XHCC1_MMIO)—Offset 8640h ......................... 1743
16.965XHC System Bus Configuration 2 (XHCC2_MMIO)—Offset 8644h ......................... 1744
16.966Clock Gating (XHCLKGTEN_MMIO)—Offset 8650h .............................................. 1746
16.967Audio Time Synchronization (AUDSYNC_MMIO)—Offset 8658h ............................ 1749
16.968Serial Bus Release Number (SBRN_MMIO)—Offset 8660h ................................... 1750
16.969Frame Length Adjustment (FLADJ_MMIO)—Offset 8661h .................................... 1750
16.970Best Effort Service Latency (BESL_MMIO)—Offset 8662h .................................... 1751
52 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 53
16.1019(PORT1_PROFILE_ATTRIBUTES_REG1)—Offset 8910h ...................................... 1780
16.1020(PORT1_PROFILE_ATTRIBUTES_REG2)—Offset 8914h ...................................... 1781
16.1021(PORT1_PROFILE_ATTRIBUTES_REG3)—Offset 8918h ...................................... 1781
16.1022(PORT1_PROFILE_ATTRIBUTES_REG4)—Offset 891Ch ...................................... 1782
16.1023(PORT1_PROFILE_ATTRIBUTES_REG5)—Offset 8920h ...................................... 1782
16.1024(PORT1_PROFILE_ATTRIBUTES_REG6)—Offset 8924h ...................................... 1783
16.1025(PORT1_PROFILE_ATTRIBUTES_REG7)—Offset 8928h ...................................... 1783
16.1026(PORT1_PROFILE_ATTRIBUTES_REG8)—Offset 892Ch ...................................... 1784
16.1027(PORT1_PROFILE_ATTRIBUTES_REG9)—Offset 8930h ...................................... 1784
16.1028(PORT1_PROFILE_ATTRIBUTES_REG10)—Offset 8934h .................................... 1785
16.1029(PORT1_PROFILE_ATTRIBUTES_REG11)—Offset 8938h .................................... 1785
16.1030(PORT1_PROFILE_ATTRIBUTES_REG12)—Offset 893Ch .................................... 1786
16.1031(PORT1_PROFILE_ATTRIBUTES_REG13)—Offset 8940h .................................... 1786
16.1032(PORT1_PROFILE_ATTRIBUTES_REG14)—Offset 8944h .................................... 1787
16.1033(PORT1_PROFILE_ATTRIBUTES_REG15)—Offset 8948h .................................... 1787
16.1034(PORT1_PROFILE_ATTRIBUTES_REG16)—Offset 894Ch .................................... 1788
16.1035(PORT1_PROFILE_ATTRIBUTES_REG17)—Offset 8950h .................................... 1788
16.1036(PORT1_PROFILE_ATTRIBUTES_REG18)—Offset 8954h .................................... 1789
16.1037(PORT1_PROFILE_ATTRIBUTES_REG19)—Offset 8958h .................................... 1789
16.1038(PORT1_PROFILE_ATTRIBUTES_REG20)—Offset 895Ch .................................... 1790
16.1039(PORT1_PROFILE_ATTRIBUTES_REG21)—Offset 8960h .................................... 1790
16.1040(PORT1_PROFILE_ATTRIBUTES_REG22)—Offset 8964h .................................... 1791
16.1041(PORT1_PROFILE_ATTRIBUTES_REG23)—Offset 8968h .................................... 1791
16.1042(PORT1_PROFILE_ATTRIBUTES_REG24)—Offset 896Ch .................................... 1792
16.1043(PORT1_PROFILE_ATTRIBUTES_REG25)—Offset 8970h .................................... 1792
16.1044(PORT1_PROFILE_ATTRIBUTES_REG26)—Offset 8974h .................................... 1793
16.1045(PORT1_PROFILE_ATTRIBUTES_REG27)—Offset 8978h .................................... 1793
16.1046(PORT1_PROFILE_ATTRIBUTES_REG28)—Offset 897Ch .................................... 1794
16.1047(PORT1_PROFILE_ATTRIBUTES_REG29)—Offset 8980h .................................... 1794
16.1048(PORT1_PROFILE_ATTRIBUTES_REG30)—Offset 8984h .................................... 1795
16.1049(PORT1_PROFILE_ATTRIBUTES_REG31)—Offset 8988h .................................... 1795
16.1050(PORT1_PROFILE_ATTRIBUTES_REG32)—Offset 898Ch .................................... 1796
16.1051(PORT1_PROFILE_ATTRIBUTES_REG33)—Offset 8990h .................................... 1796
16.1052(PORT1_PROFILE_ATTRIBUTES_REG34)—Offset 8994h .................................... 1797
16.1053(PORT1_PROFILE_ATTRIBUTES_REG35)—Offset 8998h .................................... 1797
16.1054(PORT1_PROFILE_ATTRIBUTES_REG36)—Offset 899Ch .................................... 1798
16.1055(PORT1_PROFILE_ATTRIBUTES_REG37)—Offset 89A0h .................................... 1798
16.1056(PORT1_PROFILE_ATTRIBUTES_REG38)—Offset 89A4h .................................... 1799
16.1057(PORT1_PROFILE_ATTRIBUTES_REG39)—Offset 89A8h .................................... 1799
16.1058(PORT1_PROFILE_ATTRIBUTES_REG40)—Offset 89ACh .................................... 1800
16.1059(PORT1_PROFILE_ATTRIBUTES_REG41)—Offset 89B0h .................................... 1800
16.1060(PORT1_PROFILE_ATTRIBUTES_REG42)—Offset 89B4h .................................... 1801
16.1061(PORT1_PROFILE_ATTRIBUTES_REG43)—Offset 89B8h .................................... 1801
16.1062(PORT1_PROFILE_ATTRIBUTES_REG44)—Offset 89BCh .................................... 1802
16.1063(PORT1_PROFILE_ATTRIBUTES_REG45)—Offset 89C0h .................................... 1802
16.1064(PORT1_PROFILE_ATTRIBUTES_REG46)—Offset 89C4h .................................... 1803
16.1065(PORT1_PROFILE_ATTRIBUTES_REG47)—Offset 89C8h .................................... 1803
16.1066(PORT1_PROFILE_ATTRIBUTES_REG48)—Offset 89CCh .................................... 1804
16.1067(PORT1_PROFILE_ATTRIBUTES_REG49)—Offset 89D0h .................................... 1804
16.1068(PORT1_PROFILE_ATTRIBUTES_REG50)—Offset 89D4h .................................... 1805
16.1069(PORT1_PROFILE_ATTRIBUTES_REG51)—Offset 89D8h .................................... 1805
16.1070(PORT1_PROFILE_ATTRIBUTES_REG52)—Offset 89DCh .................................... 1806
16.1071(PORT1_PROFILE_ATTRIBUTES_REG53)—Offset 89E0h .................................... 1806
16.1072(PORT1_PROFILE_ATTRIBUTES_REG54)—Offset 89E4h .................................... 1807
16.1073(PORT1_PROFILE_ATTRIBUTES_REG55)—Offset 89E8h .................................... 1807
54 Datasheet Volume 2 of 2
16.1074(PORT1_PROFILE_ATTRIBUTES_REG56)—Offset 89ECh.....................................1808
16.1075(PORT1_PROFILE_ATTRIBUTES_REG57)—Offset 89F0h .....................................1808
16.1076(PORT1_PROFILE_ATTRIBUTES_REG58)—Offset 89F4h .....................................1809
16.1077(PORT1_PROFILE_ATTRIBUTES_REG59)—Offset 89F8h .....................................1809
16.1078(PORT1_PROFILE_ATTRIBUTES_REG60)—Offset 89FCh .....................................1810
16.1079(PORT1_PROFILE_ATTRIBUTES_REG61)—Offset 8A00h.....................................1810
16.1080(PORT1_PROFILE_ATTRIBUTES_REG62)—Offset 8A04h.....................................1811
16.1081(PORT1_PROFILE_ATTRIBUTES_REG63)—Offset 8A08h.....................................1811
16.1082GLOBAL_TIME_SYNC_CAP_REG (GLOBAL_TIME_SYNC_CAP_REG)—Offset 8E10h .1812
16.1083GLOBAL_TIME_SYNC_CTRL_REG (GLOBAL_TIME_SYNC_CTRL_REG)—Offset 8E14h .....
1812
16.1084MICROFRAME_TIME_REG (MICROFRAME_TIME_REG)—Offset 8E18h...................1812
16.1085GLOBAL_TIME_LOW_REG (GLOBAL_TIME_LOW_REG)—Offset 8E20h ..................1813
16.1086GLOBAL_TIME_HI_REG (GLOBAL_TIME_HI_REG)—Offset 8E24h ........................1813
16.1087Debug Status Capability Register (DEBUG_STATUS_CAPABILITY_REG)—Offset 8E58h ..
1814
16.1088Host Ctrl USB3 Soft Error Count Register 1 (HOST_CTRL_USB3_ERR_COUNT_REG1)—
Offset 8E5Ch .................................................................................................1814
16.1089Host Ctrl USB3 Soft Error Count Register 2 (HOST_CTRL_USB3_ERR_COUNT_REG2)—
Offset 8E60h .................................................................................................1814
16.1090Host Ctrl USB3 Soft Error Count Register 3 (HOST_CTRL_USB3_ERR_COUNT_REG3)—
Offset 8E64h .................................................................................................1815
16.1091Host Ctrl USB3 Soft Error Count Register 4 (HOST_CTRL_USB3_ERR_COUNT_REG4)—
Offset 8E68h .................................................................................................1815
16.1092Host Ctrl USB3 Soft Error Count Register 5 (HOST_CTRL_USB3_ERR_COUNT_REG5)—
Offset 8E6Ch .................................................................................................1816
16.1093Host Ctrl USB3 Soft Error Count Register 6 (HOST_CTRL_USB3_ERR_COUNT_REG6)—
Offset 8E70h .................................................................................................1816
16.1094Host Ctrl USB3 Soft Error Count Register 7 (HOST_CTRL_USB3_ERR_COUNT_REG7)—
Offset 8E74h .................................................................................................1816
16.1095(GEN_REGRW1)—Offset B0h .........................................................................1817
16.1096(GEN_REGRW2)—Offset B4h .........................................................................1817
16.1097(GEN_REGRW3)—Offset B8h .........................................................................1817
16.1098(GEN_REGRW4)—Offset BCh .........................................................................1818
16.1099 (GEN_INPUT_REGRW)—Offset C0h ................................................................1818
16.1100(GEN_REGRW1)—Offset B0h .........................................................................1819
16.1101(GEN_REGRW2)—Offset B4h .........................................................................1820
16.1102(GEN_REGRW3)—Offset B8h .........................................................................1820
16.1103(GEN_REGRW4)—Offset BCh .........................................................................1820
16.1104 (GEN_INPUT_REGRW)—Offset C0h ................................................................1821
16.1105APBFC_U3PMU_CFG0 (APBFC_U3PMU_CFG0)—Offset 10F808h ..........................1822
16.1106APBFC_U3PMU_CFG1 (APBFC_U3PMU_CFG1)—Offset 10F80Ch ..........................1822
16.1107APBFC_U3PMU_CFG2 (APBFC_U3PMU_CFG2)—Offset 10F810h ..........................1824
16.1108APBFC_U3PMU_CFG3 (APBFC_U3PMU_CFG3)—Offset 10F814h ..........................1824
16.1109APBFC_U3PMU_CFG4 (APBFC_U3PMU_CFG4)—Offset 10F818h ..........................1825
16.1110APBFC_U3PMU_CFG5 (APBFC_U3PMU_CFG5)—Offset 10F81Ch ..........................1826
16.1111APBFC_U3PMU_CFG6 (APBFC_U3PMU_CFG6)—Offset 10F820h ..........................1827
16.1112APBFC_D0I3C (APBFC_D0I3C)—Offset 10F830h ...............................................1827
16.1113GTXTHRCFG (GTXTHRCFG)—Offset C108h.......................................................1829
16.1114GRXTHRCFG (GRXTHRCFG)—Offset C10Ch ......................................................1830
16.1115GCTL (GCTL)—Offset C110h ..........................................................................1830
16.1116GPMSTS (GPMSTS)—Offset C114h..................................................................1831
16.1117GSTS (GSTS)—Offset C118h..........................................................................1832
16.1118GUCTL1 (GUCTL1)—Offset C11Ch ..................................................................1832
16.1119GSNPSID (GSNPSID)—Offset C120h ...............................................................1833
Datasheet Volume 2 of 2 55
16.1120GGPIO (GGPIO)—Offset C124h...................................................................... 1833
16.1121GUID (GUID)—Offset C128h ......................................................................... 1834
16.1122GUCTL (GUCTL)—Offset C12Ch ..................................................................... 1834
16.1123GBUSERRADDRLO (GBUSERRADDRLO)—Offset C130h ...................................... 1835
16.1124GBUSERRADDRHI (GBUSERRADDRHI)—Offset C134h....................................... 1835
16.1125GPRTBIMAPLO (GPRTBIMAPLO)—Offset C138h ................................................ 1835
16.1126GPRTBIMAPHI (GPRTBIMAPHI)—Offset C13Ch ................................................. 1836
16.1127GHWPARAMS0 (GHWPARAMS0)—Offset C140h ................................................ 1837
16.1128GHWPARAMS1 (GHWPARAMS1)—Offset C144h ................................................ 1837
16.1129GHWPARAMS2 (GHWPARAMS2)—Offset C148h ................................................ 1838
16.1130GHWPARAMS3 (GHWPARAMS3)—Offset C14Ch................................................ 1838
16.1131GHWPARAMS4 (GHWPARAMS4)—Offset C150h ................................................ 1839
16.1132GHWPARAMS5 (GHWPARAMS5)—Offset C154h ................................................ 1840
16.1133GHWPARAMS6 (GHWPARAMS6)—Offset C158h ................................................ 1841
16.1134GHWPARAMS7 (GHWPARAMS7)—Offset C15Ch................................................ 1841
16.1135GDBGFIFOSPACE (GDBGFIFOSPACE)—Offset C160h......................................... 1842
16.1136GDBGLTSSM (GDBGLTSSM)—Offset C164h ..................................................... 1842
16.1137GDBGLNMCC (GDBGLNMCC)—Offset C168h .................................................... 1843
16.1138GDBGBMU (GDBGBMU)—Offset C16Ch ........................................................... 1844
16.1139GDBGLSPMUX_DEV (GDBGLSPMUX_DEV)—Offset C170h .................................. 1844
16.1140GDBGLSP (GDBGLSP)—Offset C174h ............................................................. 1844
16.1141GDBGEPINFO0 (GDBGEPINFO0)—Offset C178h ............................................... 1845
16.1142GDBGEPINFO1 (GDBGEPINFO1)—Offset C17Ch ............................................... 1845
16.1143GPRTBIMAP_HSLO (GPRTBIMAP_HSLO)—Offset C180h ..................................... 1845
16.1144GPRTBIMAP_HSHI (GPRTBIMAP_HSHI)—Offset C184h...................................... 1846
16.1145GPRTBIMAP_FSLO (GPRTBIMAP_FSLO)—Offset C188h...................................... 1847
16.1146GPRTBIMAP_FSHI (GPRTBIMAP_FSHI)—Offset C18Ch....................................... 1847
16.1147Reserved_94 (Reserved_94)—Offset C194h .................................................... 1848
16.1148Reserved_98 (Reserved_98)—Offset C198h .................................................... 1848
16.1149GUSB2PHYCFG_0 (GUSB2PHYCFG_0)—Offset C200h........................................ 1848
16.1150GUSB2I2CCTL_0 (GUSB2I2CCTL_0)—Offset C240h .......................................... 1849
16.1151GUSB2PHYACC_ULPI_0 (GUSB2PHYACC_ULPI_0)—Offset C280h ....................... 1850
16.1152GUSB3PIPECTL_0 (GUSB3PIPECTL_0)—Offset C2C0h ....................................... 1850
16.1153GTXFIFOSIZ0_0 (GTXFIFOSIZ0_0)—Offset C300h ........................................... 1852
16.1154GTXFIFOSIZ1_0 (GTXFIFOSIZ1_0)—Offset C304h ........................................... 1852
16.1155GTXFIFOSIZ2_0 (GTXFIFOSIZ2_0)—Offset C308h ........................................... 1853
16.1156GTXFIFOSIZ3_0 (GTXFIFOSIZ3_0)—Offset C30Ch ........................................... 1853
16.1157GTXFIFOSIZ4_0 (GTXFIFOSIZ4_0)—Offset C310h ........................................... 1853
16.1158GTXFIFOSIZ5_0 (GTXFIFOSIZ5_0)—Offset C314h ........................................... 1854
16.1159GTXFIFOSIZ6_0 (GTXFIFOSIZ6_0)—Offset C318h ........................................... 1854
16.1160GTXFIFOSIZ7_0 (GTXFIFOSIZ7_0)—Offset C31Ch ........................................... 1854
16.1161GTXFIFOSIZ8_0 (GTXFIFOSIZ8_0)—Offset C320h ........................................... 1855
16.1162GTXFIFOSIZ9_0 (GTXFIFOSIZ9_0)—Offset C324h ........................................... 1855
16.1163GTXFIFOSIZ10_0 (GTXFIFOSIZ10_0)—Offset C328h ........................................ 1855
16.1164GTXFIFOSIZ11_0 (GTXFIFOSIZ11_0)—Offset C32Ch ........................................ 1856
16.1165GTXFIFOSIZ12_0 (GTXFIFOSIZ12_0)—Offset C330h ........................................ 1856
16.1166GTXFIFOSIZ13_0 (GTXFIFOSIZ13_0)—Offset C334h ........................................ 1856
16.1167GTXFIFOSIZ14_0 (GTXFIFOSIZ14_0)—Offset C338h ........................................ 1857
16.1168GTXFIFOSIZ15_0 (GTXFIFOSIZ15_0)—Offset C33Ch ........................................ 1857
16.1169GRXFIFOSIZ0_0 (GRXFIFOSIZ0_0)—Offset C380h ........................................... 1857
16.1170GEVNTADRLO_0 (GEVNTADRLO_0)—Offset C400h ........................................... 1858
16.1171GEVNTADRHI_0 (GEVNTADRHI_0)—Offset C404h ............................................ 1858
16.1172GEVNTSIZ_0 (GEVNTSIZ_0)—Offset C408h .................................................... 1858
16.1173GEVNTCOUNT_0 (GEVNTCOUNT_0)—Offset C40Ch .......................................... 1859
16.1174GHWPARAMS8 (GHWPARAMS8)—Offset C600h ................................................ 1859
56 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 57
17.11 POWERCAPID — Offset 80h............................................................................. 1884
17.12 PMECTRLSTATUS — Offset 84h ........................................................................ 1885
17.13 PCIDEVIDLE_CAP_RECORD — Offset 90h .......................................................... 1885
17.14 DEVID_VEND_SPECIFIC_REG — Offset 94h ....................................................... 1886
17.15 D0I3_CONTROL_SW_LTR_MMIO_REG — Offset 98h ........................................... 1886
17.16 DEVICE_IDLE_POINTER_REG — Offset 9Ch ....................................................... 1886
17.17 D0I3_MAX_POW_LAT_PG_CONFIG — Offset A0h ............................................... 1887
17.18 GEN_REGRW1 — Offset B0h............................................................................ 1887
17.19 GEN_REGRW2 — Offset B4h............................................................................ 1888
17.20 GEN_REGRW3 — Offset B8h............................................................................ 1888
17.21 GEN_REGRW4 — Offset BCh............................................................................ 1888
17.22 GEN_INPUT_REGRW — Offset C0h ................................................................... 1889
17.23 MANID — Offset F8h ...................................................................................... 1890
18 PCI Express* Controller Registers ........................................................................1891
18.1 ID — Offset 0h .............................................................................................. 1891
18.2 Device Command; Primary Status (CMD_PSTS) — Offset 4h................................ 1891
18.3 Revision ID;Class Code (RID_CC) — Offset 8h ................................................... 1893
18.4 Cache Line Size; Primary Latency Timer; Header Type (CLS_PLT_HTYPE) — Offset Ch ...
1893
18.5 Bus Numbers; Secondary Latency Timer (BNUM_SLT) — Offset 18h ..................... 1894
18.6 I/O Base and Limit; Secondary Status (IOBL_SSTS) — Offset 1Ch........................ 1894
18.7 Memory Base and Limit (MBL) — Offset 20h ...................................................... 1895
18.8 Prefetchable Memory Base and Limit (PMBL) — Offset 24h .................................. 1896
18.9 Prefetchable Memory Base Upper 32 Bits (PMBU32) — Offset 28h ........................ 1896
18.10 Prefetchable Memory Limit Upper 32 Bits (PMLU32) — Offset 2Ch ........................ 1896
18.11 Capabilities List Pointer (CAPP) — Offset 34h ..................................................... 1897
18.12 Interrupt Information; Bridge Control (INTR_BCTRL) — Offset 3Ch....................... 1897
18.13 Capabilities List; PCI Express Capabilities (CLIST_XCAP) — Offset 40h .................. 1898
18.14 Device Capabilities (DCAP) — Offset 44h........................................................... 1899
18.15 Device Control; Device Status (DCTL_DSTS) — Offset 48h .................................. 1900
18.16 Link Capabilities (LCAP) — Offset 4Ch............................................................... 1901
18.17 Link Control; Link Status (LCTL_LSTS) — Offset 50h .......................................... 1902
18.18 Slot Capabilities (SLCAP) — Offset 54h ............................................................. 1904
18.19 Slot Control; Slot Status (SLCTL_SLSTS) — Offset 58h ....................................... 1905
18.20 Root Control (RCTL) — Offset 5Ch.................................................................... 1906
18.21 Root Status (RSTS) — Offset 60h..................................................................... 1907
18.22 Device Capabilities 2 (DCAP2) — Offset 64h ...................................................... 1907
18.23 Device Control 2; Device Status 2 (DCTL2_DSTS2) — Offset 68h ......................... 1908
18.24 Link Capabilities 2 (LCAP2) — Offset 6Ch .......................................................... 1909
18.25 Link Control 2; Link Status 2 (LCTL2_LSTS2) — Offset 70h.................................. 1910
18.26 Slot Capabilities 2 (SLCAP2) — Offset 74h......................................................... 1911
18.27 Slot Control 2; Slot Status 2 (SLCTL2_SLSTS2) — Offset 78h .............................. 1912
18.28 Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message Control
(MID_MC) — Offset 80h.................................................................................. 1912
18.29 Message Signaled Interrupt Message Address (MA) — Offset 84h ......................... 1913
18.30 Message Signaled Interrupt Message Data (MD) — Offset 88h ............................. 1913
18.31 Subsystem Vendor Capability (SVCAP) — Offset 90h .......................................... 1913
18.32 Subsystem Vendor IDs (SVID) — Offset 94h ..................................................... 1914
18.33 Power Management Capability; PCI Power Management Capabilities (PMCAP_PMC) — Off-
set A0h ........................................................................................................ 1914
18.34 PCI Power Management Control And Status (PMCS) — Offset A4h ........................ 1915
18.35 Advanced Error Extended Reporting Capability Header (AECH) — Offset 100h ........ 1916
18.36 Uncorrectable Error Status (UES) — Offset 104h ................................................ 1916
18.37 Uncorrectable Error Mask (UEM) — Offset 108h ................................................. 1917
58 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 59
18.91 Figure Of Merit Status (FOMS) — Offset 464h .................................................... 1957
18.92 Hardware Autonomous Equalization Control (HAEQ) — Offset 468h ...................... 1957
18.93 Local Transmitter Coefficient Override 1 (LTCO1) — Offset 470h .......................... 1958
18.94 Local Transmitter Coefficient Override 2 (LTCO2) — Offset 474h .......................... 1959
18.95 GEN3 L0s Control (G3L0SCTL) — Offset 478h .................................................... 1960
18.96 Equalization Configuration 2 (EQCFG2) — Offset 47Ch ........................................ 1961
18.97 Monitor Mux (MM) — Offset 480h..................................................................... 1962
18.98 Lane0 P0 and P1 Preset-Coefficient Mapping (L0P0P1PCM) — Offset 500h ............. 1963
18.99 Lane0 P1, P2 and P3 Preset-Coefficient Mapping (L0P1P2P3PCM) — Offset 504h..... 1963
18.100Lane0 P3 and P4 Preset-Coefficient Mapping (L0P3P4PCM) — Offset 508h ............. 1964
18.101Lane0 P5 and P6 Preset-Coefficient Mapping (L0P5P6PCM) — Offset 50Ch............. 1965
18.102Lane0 P6, P7 and P8 Preset-Coefficient Mapping (L0P6P7P8PCM) — Offset 510h .... 1965
18.103Lane0 P8 and P9 Preset-Coefficient Mapping (L0P8P9PCM) — Offset 514h ............. 1966
18.104Lane0 P10 Preset-Coefficient Mapping (L0P10PCM) — Offset 518h ....................... 1967
18.105Lane0 LF and FS (L0LFFS) — Offset 51Ch ......................................................... 1967
18.106Lane1 P0 and P1 Preset-Coefficient Mapping (L1P0P1PCM) — Offset 520h ............. 1968
18.107Lane1 P1, P2 and P3 Preset-Coefficient Mapping (L1P1P2P3PCM) — Offset 524h .... 1969
18.108Lane1 P3 and P4 Preset-Coefficient Mapping (L1P3P4PCM) — Offset 528h ............. 1969
18.109Lane1 P5 and P6 Preset-Coefficient Mapping (L1P5P6PCM) — Offset 52Ch............. 1970
18.110Lane1 P6, P7 and P8 Preset-Coefficient Mapping (L1P6P7P8PCM) — Offset 530h .... 1971
18.111Lane1 P8 and P9 Preset-Coefficient Mapping (L1P8P9PCM) — Offset 534h ............. 1971
18.112Lane1 P10 Preset-Coefficient Mapping (L1P10PCM) — Offset 538h ....................... 1972
18.113Lane1 LF and FS (L1LFFS) — Offset 53Ch ......................................................... 1973
18.114Lane2 P0 and P1 Preset-Coefficient Mapping (L2P0P1PCM) — Offset 540h ............. 1973
18.115Lane2 P1, P2 and P3 Preset-Coefficient Mapping (L2P1P2P3PCM) — Offset 544h .... 1974
18.116Lane2 P3 and P4 Preset-Coefficient Mapping (L2P3P4PCM) — Offset 548h ............. 1975
18.117Lane2 P5 and P6 Preset-Coefficient Mapping (L2P5P6PCM) — Offset 54Ch............. 1975
18.118Lane2 P6, P7 and P8 Preset-Coefficient Mapping (L2P6P7P8PCM) — Offset 550h .... 1976
18.119Lane2 P8 and P9 Preset-Coefficient Mapping (L2P8P9PCM) — Offset 554h ............. 1977
18.120Lane2 P10 Preset-Coefficient Mapping (L2P10PCM) — Offset 558h ....................... 1977
18.121Lane2 LF and FS (L2LFFS) — Offset 55Ch ......................................................... 1978
18.122Lane3 P0 and P1 Preset-Coefficient Mapping (L3P0P1PCM) — Offset 560h ............. 1979
18.123Lane3 P1, P2 and P3 Preset-Coefficient Mapping (L3P1P2P3PCM) — Offset 564h .... 1979
18.124Lane3 P3 and P4 Preset-Coefficient Mapping (L3P3P4PCM) — Offset 568h ............. 1980
18.125Lane3 P5 and P6 Preset-Coefficient Mapping (L3P5P6PCM) — Offset 56Ch............. 1981
18.126Lane3 P6, P7 and P8 Preset-Coefficient Mapping (L3P6P7P8PCM) — Offset 570h .... 1981
18.127Lane3 P8 and P9 Preset-Coefficient Mapping (L3P8P9PCM) — Offset 574h ............. 1982
18.128Lane3 P10 Preset-Coefficient Mapping (L3P10PCM) — Offset 578h ....................... 1983
18.129Lane3 LF and FS (L3LFFS) — Offset 57Ch ......................................................... 1983
18.130Common Control (CC)—Offset 0h .................................................................... 1984
18.131Device Reference Clock Request Mapping 1 (DRCRM1)—Offset 100h .................... 1986
18.132Device Reference Clock Request Mapping 2 (DRCRM2)—Offset 104h .................... 1993
18.133Device Reference Clock Request Mapping 3 (DRCRM3)—Offset 108h .................... 2001
19 SATA Registers .....................................................................................................2006
19.1 ID — Offset 0h .............................................................................................. 2006
19.2 Command (CMD) — Offset 4h.......................................................................... 2006
19.3 Device Status (STS) — Offset 6h ..................................................................... 2007
19.4 Revision ID (RID) — Offset 8h ......................................................................... 2008
19.5 Programming Interface (PI) — Offset 9h ........................................................... 2008
19.6 Class Code (CC) — Offset Ah ........................................................................... 2008
19.7 Cache Line Size (CLS) — Offset Ch................................................................... 2009
19.8 Master Latency Timer (MLT) — Offset Dh .......................................................... 2009
19.9 Header Type (HTYPE) — Offset Eh.................................................................... 2009
19.10 MSI-X Table Base Address (MXTBA) — Offset 10h .............................................. 2010
60 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 61
19.66 Port [0-7] Interrupt Enable (PxIE0)—Offset 114h ............................................... 2047
19.67 Port [0-7] Command (PxCMD0)—Offset 118h .................................................... 2049
19.68 Port [0-7] Task File Data (PxTFD0)—Offset 120h................................................ 2051
19.69 Port [0-7] Signature (PxSIG0)—Offset 124h ...................................................... 2052
19.70 Port [0-7] Serial ATA Status (PxSSTS0)—Offset 128h ......................................... 2052
19.71 Port [0-7] Serial ATA Control (PxSCTL0)—Offset 12Ch ........................................ 2053
19.72 Port [0-7] Serial ATA Error (PxSERR0)—Offset 130h ........................................... 2053
19.73 Port [0-7] Serial ATA Active (PxSACT0)—Offset 134h.......................................... 2054
19.74 Port [0-7] Commands Issued (PxCI0)—Offset 138h ............................................ 2054
19.75 Port [0-7] SNotification (PxSNTF0)—Offset 13Ch................................................ 2055
19.76 Port [0-7] Device Sleep (PxDEVSLP0)—Offset 144h ............................................ 2055
19.77 Port [0-7] Command List Base Address (PxCLB1)—Offset 180h ............................ 2057
19.78 Port [0-7] Command List Base Address Upper 32-bits (PxCLBU1)—Offset 184h ...... 2057
19.79 Port [0-7] FIS Base Address (PxFB1)—Offset 188h ............................................. 2057
19.80 Port [0-7] FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch ....................... 2058
19.81 Port [0-7] Interrupt Status (PxIS1)—Offset 190h ............................................... 2058
19.82 Port [0-7] Interrupt Enable (PxIE1)—Offset 194h ............................................... 2060
19.83 Port [0-7] Command (PxCMD1)—Offset 198h .................................................... 2061
19.84 Port [0-7] Task File Data (PxTFD1)—Offset 1A0h................................................ 2064
19.85 Port [0-7] Signature (PxSIG1)—Offset 1A4h ...................................................... 2065
19.86 Port [0-7] Serial ATA Status (PxSSTS1)—Offset 1A8h ......................................... 2065
19.87 Port [0-7] Serial ATA Control (PxSCTL1)—Offset 1ACh ........................................ 2066
19.88 Port [0-7] Serial ATA Error (PxSERR1)—Offset 1B0h ........................................... 2066
19.89 Port [0-7] Serial ATA Active (PxSACT1)—Offset 1B4h ......................................... 2067
19.90 Port [0-7] Commands Issued (PxCI1)—Offset 1B8h ............................................ 2067
19.91 Port [0-7] SNotification (PxSNTF1)—Offset 1BCh................................................ 2067
19.92 Port [0-7] Device Sleep (PxDEVSLP1)—Offset 1C4h ............................................ 2068
19.93 Enclosure Management Message Format (EM_MF)—Offset 580h ........................... 2069
19.94 Enclosure Management LED (EM_LED)—Offset 584h........................................... 2070
19.95 MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)—Offset 0h ................................. 2071
19.96 MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)—Offset 4h ................................. 2072
19.97 MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)—Offset 0h................. 2072
19.98 MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)—Offset 4h ................ 2073
19.99 MSI-X Table Entries 0 Message Data (MXTE0MD)—Offset 8h................................ 2073
19.100MSI-X Table Entries 0 Vector Control (MXTE0VC)—Offset Ch ............................... 2073
20 I/O Sensor Hub (ISH) Registers...........................................................................2075
20.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID) — Offset 0h . 2075
20.2 STATUSCOMMAND — Offset 4h........................................................................ 2075
20.3 REVCLASSCODE — Offset 8h ........................................................................... 2076
20.4 CLLATHEADERBIST — Offset Ch....................................................................... 2076
20.5 BAR — Offset 10h .......................................................................................... 2077
20.6 BAR -Base Address Register High (BAR_HIGH) — Offset 14h ............................... 2077
20.7 BAR1 — Offset 18h ........................................................................................ 2078
20.8 BAR1 -Base Address Register1 High (BAR1_HIGH) — Offset 1Ch .......................... 2078
20.9 SUBSYSTEMID — Offset 2Ch ........................................................................... 2078
20.10 EXPANSION ROM base address (EXPANSION_ROM_BASEADDR) — Offset 30h ....... 2079
20.11 CAPABILITYPTR — Offset 34h .......................................................................... 2079
20.12 INTERRUPTREG — Offset 3Ch .......................................................................... 2079
20.13 POWERCAPID — Offset 80h............................................................................. 2080
20.14 PMECTRLSTATUS — Offset 84h ........................................................................ 2080
20.15 PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD) — Offset 90h. 2081
20.16 DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) — Offset 94h ......... 2082
20.17 D0I3_CONTROL_SW_LTR_MMIO_REG — Offset 98h ........................................... 2082
20.18 DEVICE_IDLE_POINTER_REG — Offset 9Ch ....................................................... 2082
62 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 63
20.62 Outbound Inter Processor Messages 13 ISH to Host (ISH2HOST_MSG13)—Offset 1090h
2102
20.63 Outbound Inter Processor Messages 14 ISH to Host (ISH2HOST_MSG14)—Offset 1094h
2102
20.64 Outbound Inter Processor Messages 15 ISH to Host (ISH2HOST_MSG15)—Offset 1098h
2102
20.65 Outbound Inter Processor Messages 16 ISH to Host (ISH2HOST_MSG16)—Offset 109Ch
2103
20.66 Outbound Inter Processor Messages 17 ISH to Host (ISH2HOST_MSG17)—Offset 10A0h
2103
20.67 Outbound Inter Processor Messages 18 ISH to Host (ISH2HOST_MSG18)—Offset 10A4h
2104
20.68 Outbound Inter Processor Messages 19 ISH to Host (ISH2HOST_MSG19)—Offset 10A8h
2104
20.69 Outbound Inter Processor Messages 20 ISH to Host (ISH2HOST_MSG20)—Offset 10ACh
2104
20.70 Outbound Inter Processor Messages 21 ISH to Host (ISH2HOST_MSG21)—Offset 10B0h
2105
20.71 Outbound Inter Processor Messages 22 ISH to Host (ISH2HOST_MSG22)—Offset 10B4h
2105
20.72 Outbound Inter Processor Messages 23 ISH to Host (ISH2HOST_MSG23)—Offset 10B8h
2106
20.73 Outbound Inter Processor Messages 24 ISH to Host (ISH2HOST_MSG24)—Offset 10BCh
2106
20.74 Outbound Inter Processor Messages 25 ISH to Host (ISH2HOST_MSG25)—Offset 10C0h
2106
20.75 Outbound Inter Processor Messages 26 ISH to Host (ISH2HOST_MSG26)—Offset 10C4h
2107
20.76 Outbound Inter Processor Messages 27 ISH to Host (ISH2HOST_MSG27)—Offset 10C8h
2107
20.77 Outbound Inter Processor Messages 28 ISH to Host (ISH2HOST_MSG28)—Offset 10CCh
2108
20.78 Outbound Inter Processor Messages 29 ISH to Host (ISH2HOST_MSG29)—Offset 10D0h
2108
20.79 Outbound Inter Processor Messages 30 ISH to Host (ISH2HOST_MSG30)—Offset 10D4h
2108
20.80 Outbound Inter Processor Messages 31 ISH to Host (ISH2HOST_MSG31)—Offset 10D8h
2109
20.81 Outbound Inter Processor Messages 32 ISH to Host (ISH2HOST_MSG32)—Offset 10DCh
2109
20.82 Inbound Inter Processor Messages 1 Host to ISH (HOST2ISH_MSG1)—Offset 10E0h ......
2110
20.83 Inbound Inter Processor Messages 2 Host to ISH (HOST2ISH_MSG2)—Offset 10E4h ......
2110
20.84 Inbound Inter Processor Messages 3 Host to ISH (HOST2ISH_MSG3)—Offset 10E8h ......
2110
20.85 Inbound Inter Processor Messages 4 Host to ISH (HOST2ISH_MSG4)—Offset 10ECh......
2111
20.86 Inbound Inter Processor Messages 5 Host to ISH (HOST2ISH_MSG5)—Offset 10F0h2111
20.87 Inbound Inter Processor Messages 6 Host to ISH (HOST2ISH_MSG6)—Offset 10F4h2112
20.88 Inbound Inter Processor Messages 7 Host to ISH (HOST2ISH_MSG7)—Offset 10F8h2112
20.89 Inbound Inter Processor Messages 8 Host to ISH (HOST2ISH_MSG8)—Offset 10FCh ......
2112
20.90 Inbound Inter Processor Messages 9 Host to ISH (HOST2ISH_MSG9)—Offset 1100h ......
2113
20.91 Inbound Inter Processor Messages 10 Host to ISH (HOST2ISH_MSG10)—Offset 1104h ..
2113
64 Datasheet Volume 2 of 2
20.92 Inbound Inter Processor Messages 11 Host to ISH (HOST2ISH_MSG11)—Offset 1108h ...
2114
20.93 Inbound Inter Processor Messages 12 Host to ISH (HOST2ISH_MSG12)—Offset 110Ch...
2114
20.94 Inbound Inter Processor Messages 13 Host to ISH (HOST2ISH_MSG13)—Offset 1110h ...
2114
20.95 Inbound Inter Processor Messages 14 Host to ISH (HOST2ISH_MSG14)—Offset 1114h ...
2115
20.96 Inbound Inter Processor Messages 15 Host to ISH (HOST2ISH_MSG15)—Offset 1118h ...
2115
20.97 Inbound Inter Processor Messages 16 Host to ISH (HOST2ISH_MSG16)—Offset 111Ch...
2116
20.98 Inbound Inter Processor Messages 17 Host to ISH (HOST2ISH_MSG17)—Offset 1120h ...
2116
20.99 Inbound Inter Processor Messages 18 Host to ISH (HOST2ISH_MSG18)—Offset 1124h ...
2116
20.100Inbound Inter Processor Messages 19 Host to ISH (HOST2ISH_MSG19)—Offset 1128h ..
2117
20.101Inbound Inter Processor Messages 20 Host to ISH (HOST2ISH_MSG20)—Offset 112Ch ..
2117
20.102Inbound Inter Processor Messages 21 Host to ISH (HOST2ISH_MSG21)—Offset 1130h ..
2118
20.103Inbound Inter Processor Messages 22 Host to ISH (HOST2ISH_MSG22)—Offset 1134h ..
2118
20.104Inbound Inter Processor Messages 23 Host to ISH (HOST2ISH_MSG23)—Offset 1138h ..
2118
20.105Inbound Inter Processor Messages 24 Host to ISH (HOST2ISH_MSG24)—Offset 113Ch ..
2119
20.106Inbound Inter Processor Messages 25 Host to ISH (HOST2ISH_MSG25)—Offset 1140h ..
2119
20.107Inbound Inter Processor Messages 26 Host to ISH (HOST2ISH_MSG26)—Offset 1144h ..
2120
20.108Inbound Inter Processor Messages 27 Host to ISH (HOST2ISH_MSG27)—Offset 1148h ..
2120
20.109Inbound Inter Processor Messages 28 Host to ISH (HOST2ISH_MSG28)—Offset 114Ch ..
2120
20.110Inbound Inter Processor Messages 29 Host to ISH (HOST2ISH_MSG29)—Offset 1150h ..
2121
20.111Inbound Inter Processor Messages 30 Host to ISH (HOST2ISH_MSG30)—Offset 1154h ..
2121
20.112Inbound Inter Processor Messages 31 Host to ISH (HOST2ISH_MSG31)—Offset 1158h ..
2122
20.113Inbound Inter Processor Messages 32 Host to ISH (HOST2ISH_MSG32)—Offset 115Ch ..
2122
20.114Outbound Inter Processor Messages 1 ISH to SEC (ISH2SEC_MSG1)—Offset 1160h2122
20.115Outbound Inter Processor Messages 2 ISH to SEC (ISH2SEC_MSG2)—Offset 1164h2123
20.116Outbound Inter Processor Messages 3 ISH to SEC (ISH2SEC_MSG3)—Offset 1168h2123
20.117Outbound Inter Processor Messages 4 ISH to SEC (ISH2SEC_MSG4)—Offset 116Ch2124
20.118Outbound Inter Processor Messages 5 ISH to SEC (ISH2SEC_MSG5)—Offset 1170h2124
20.119Outbound Inter Processor Messages 6 ISH to SEC (ISH2SEC_MSG6)—Offset 1174h2124
20.120Outbound Inter Processor Messages 7 ISH to SEC (ISH2SEC_MSG7)—Offset 1178h2125
20.121Outbound Inter Processor Messages 8 ISH to SEC (ISH2SEC_MSG8)—Offset 117Ch2125
20.122Outbound Inter Processor Messages 9 ISH to SEC (ISH2SEC_MSG9)—Offset 1180h2126
20.123Outbound Inter Processor Messages 10 ISH to SEC (ISH2SEC_MSG10)—Offset 1184h ...
2126
20.124Outbound Inter Processor Messages 11 ISH to SEC (ISH2SEC_MSG11)—Offset 1188h ...
2126
Datasheet Volume 2 of 2 65
20.125Outbound Inter Processor Messages 12 ISH to SEC (ISH2SEC_MSG12)—Offset 118Ch ..
2127
20.126Outbound Inter Processor Messages 13 ISH to SEC (ISH2SEC_MSG13)—Offset 1190h...
2127
20.127Outbound Inter Processor Messages 14 ISH to SEC (ISH2SEC_MSG14)—Offset 1194h...
2128
20.128Outbound Inter Processor Messages 15 ISH to SEC (ISH2SEC_MSG15)—Offset 1198h...
2128
20.129Outbound Inter Processor Messages 16 ISH to SEC (ISH2SEC_MSG16)—Offset 119Ch ..
2128
20.130Outbound Inter Processor Messages 17 ISH to SEC (ISH2SEC_MSG17)—Offset 11A0h ..
2129
20.131Outbound Inter Processor Messages 18 ISH to SEC (ISH2SEC_MSG18)—Offset 11A4h ..
2129
20.132Outbound Inter Processor Messages 19 ISH to SEC (ISH2SEC_MSG19)—Offset 11A8h ..
2130
20.133Outbound Inter Processor Messages 20 ISH to SEC (ISH2SEC_MSG20)—Offset 11ACh ..
2130
20.134Outbound Inter Processor Messages 21 ISH to SEC (ISH2SEC_MSG21)—Offset 11B0h ..
2130
20.135Outbound Inter Processor Messages 22 ISH to SEC (ISH2SEC_MSG22)—Offset 11B4h ..
2131
20.136Outbound Inter Processor Messages 23 ISH to SEC (ISH2SEC_MSG23)—Offset 11B8h ..
2131
20.137Outbound Inter Processor Messages 24 ISH to SEC (ISH2SEC_MSG24)—Offset 11BCh ..
2132
20.138Outbound Inter Processor Messages 25 ISH to SEC (ISH2SEC_MSG25)—Offset 11C0h ..
2132
20.139Outbound Inter Processor Messages 26 ISH to SEC (ISH2SEC_MSG26)—Offset 11C4h ..
2132
20.140Outbound Inter Processor Messages 27 ISH to SEC (ISH2SEC_MSG27)—Offset 11C8h ..
2133
20.141Outbound Inter Processor Messages 28 ISH to SEC (ISH2SEC_MSG28)—Offset 11CCh ..
2133
20.142Outbound Inter Processor Messages 29 ISH to SEC (ISH2SEC_MSG29)—Offset 11D0h ..
2134
20.143Outbound Inter Processor Messages 30 ISH to SEC (ISH2SEC_MSG30)—Offset 11D4h ..
2134
20.144Outbound Inter Processor Messages 31 ISH to SEC (ISH2SEC_MSG31)—Offset 11D8h ..
2134
20.145Outbound Inter Processor Messages 32 ISH to SEC (ISH2SEC_MSG32)—Offset 11DCh ..
2135
20.146Inbound Inter Processor Messages 1 SEC to ISH (SEC2ISH_MSG1)—Offset 11E0h . 2135
20.147Inbound Inter Processor Messages 2 SEC to ISH (SEC2ISH_MSG2)—Offset 11E4h . 2136
20.148Inbound Inter Processor Messages 3 SEC to ISH (SEC2ISH_MSG3)—Offset 11E8h . 2136
20.149Inbound Inter Processor Messages 4 SEC to ISH (SEC2ISH_MSG4)—Offset 11ECh . 2136
20.150Inbound Inter Processor Messages 5 SEC to ISH (SEC2ISH_MSG5)—Offset 11F0h . 2137
20.151Inbound Inter Processor Messages 6 SEC to ISH (SEC2ISH_MSG6)—Offset 11F4h . 2137
20.152Inbound Inter Processor Messages 7 SEC to ISH (SEC2ISH_MSG7)—Offset 11F8h . 2138
20.153Inbound Inter Processor Messages 8 SEC to ISH (SEC2ISH_MSG8)—Offset 11FCh . 2138
20.154Inbound Inter Processor Messages 9 SEC To ISH (SEC2ISH_MSG9)—Offset 1200h. 2138
20.155Inbound Inter Processor Messages 10 SEC to ISH (SEC2ISH_MSG10)—Offset 1204h.....
2139
20.156Inbound Inter Processor Messages 11 SEC to ISH (SEC2ISH_MSG11)—Offset 1208h.....
2139
20.157Inbound Inter Processor Messages 12 SEC to ISH (SEC2ISH_MSG12)—Offset 120Ch.....
2140
66 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 67
2151
20.187Outbound Inter Processor Messages 10 ISH to PMC (ISH2PMC_MSG10)—Offset 1284h ..
2152
20.188Outbound Inter Processor Messages 11 ISH to PMC (ISH2PMC_MSG11)—Offset 1288h ..
2152
20.189Outbound Inter Processor Messages 12 ISH to PMC (ISH2PMC_MSG12)—Offset 128Ch..
2152
20.190Outbound Inter Processor Messages 13 ISH to PMC (ISH2PMC_MSG13)—Offset 1290h ..
2153
20.191Outbound Inter Processor Messages 14 ISH to PMC (ISH2PMC_MSG14)—Offset 1294h ..
2153
20.192Outbound Inter Processor Messages 15 ISH to PMC (ISH2PMC_MSG15)—Offset 1298h ..
2154
20.193Outbound Inter Processor Messages 16 ISH to PMC (ISH2PMC_MSG16)—Offset 129Ch..
2154
20.194Outbound Inter Processor Messages 17 ISH to PMC (ISH2PMC_MSG17)—Offset 12A0h..
2154
20.195Outbound Inter Processor Messages 18 ISH to PMC (ISH2PMC_MSG18)—Offset 12A4h..
2155
20.196Outbound Inter Processor Messages 19 ISH to PMC (ISH2PMC_MSG19)—Offset 12A8h..
2155
20.197Outbound Inter Processor Messages 20 ISH To PMC (ISH2PMC_MSG20)—Offset 12ACh .
2156
20.198Outbound Inter Processor Messages 21 ISH to PMC (ISH2PMC_MSG21)—Offset 12B0h..
2156
20.199Outbound Inter Processor Messages 22 ISH to PMC (ISH2PMC_MSG22)—Offset 12B4h..
2156
20.200Outbound Inter Processor Messages 23 ISH to PMC (ISH2PMC_MSG23)—Offset 12B8h..
2157
20.201Outbound Inter Processor Messages 24 ISH to PMC (ISH2PMC_MSG24)—Offset 12BCh..
2157
20.202Outbound Inter Processor Messages 25 ISH to PMC (ISH2PMC_MSG25)—Offset 12C0h..
2158
20.203Outbound Inter Processor Messages 26 ISH to PMC (ISH2PMC_MSG26)—Offset 12C4h..
2158
20.204Outbound Inter Processor Messages 27 ISH to PMC (ISH2PMC_MSG27)—Offset 12C8h..
2158
20.205Outbound Inter Processor Messages 28 ISH to PMC (ISH2PMC_MSG28)—Offset 12CCh..
2159
20.206Outbound Inter Processor Messages 29 ISH to PMC (ISH2PMC_MSG29)—Offset 12D0h..
2159
20.207Outbound Inter Processor Messages 30 ISH to PMC (ISH2PMC_MSG30)—Offset 12D4h..
2160
20.208Outbound Inter Processor Messages 31 ISH to PMC (ISH2PMC_MSG31)—Offset 12D8h..
2160
20.209Outbound Inter Processor Messages 32 ISH to PMC (ISH2PMC_MSG32)—Offset 12DCh .
2160
20.210Inbound Inter Processor Messages 1 PMC to ISH (PMC2ISH_MSG1)—Offset 12E0h 2161
20.211Inbound Inter Processor Messages 2 PMC to ISH (PMC2ISH_MSG2)—Offset 12E4h 2161
20.212Inbound Inter Processor Messages 3 PMC to ISH (PMC2ISH_MSG3)—Offset 12E8h 2162
20.213Inbound Inter Processor Messages 4 PMC to ISH (PMC2ISH_MSG4)—Offset 12ECh 2162
20.214Inbound Inter Processor Messages 5 PMC to ISH (PMC2ISH_MSG5)—Offset 12F0h. 2162
20.215Inbound Inter Processor Messages 6 PMC to ISH (PMC2ISH_MSG6)—Offset 12F4h. 2163
20.216Inbound Inter Processor Messages 7 PMC to ISH (PMC2ISH_MSG7)—Offset 12F8h. 2163
20.217Inbound Inter Processor Messages 8 PMC to ISH (PMC2ISH_MSG8)—Offset 12FCh 2164
20.218Inbound Inter Processor Messages 9 PMC to ISH (PMC2ISH_MSG9)—Offset 1300h 2164
20.219Inbound Inter Processor Messages 10 PMC to ISH (PMC2ISH_MSG10)—Offset 1304h ....
68 Datasheet Volume 2 of 2
2164
20.220Inbound Inter Processor Messages 11 PMC to ISH (PMC2ISH_MSG11)—Offset 1308h.....
2165
20.221Inbound Inter Processor Messages 12 PMC to ISH (PMC2ISH_MSG12)—Offset 130Ch ....
2165
20.222Inbound Inter Processor Messages 13 PMC to ISH (PMC2ISH_MSG13)—Offset 1310h.....
2166
20.223Inbound Inter Processor Messages 14 PMC to ISH (PMC2ISH_MSG14)—Offset 1314h.....
2166
20.224Inbound Inter Processor Messages 15 PMC to ISH (PMC2ISH_MSG15)—Offset 1318h.....
2166
20.225Inbound Inter Processor Messages 16 PMC to ISH (PMC2ISH_MSG16)—Offset 131Ch ....
2167
20.226Inbound Inter Processor Messages 17 PMC to ISH (PMC2ISH_MSG17)—Offset 1320h.....
2167
20.227Inbound Inter Processor Messages 18 PMC to ISH (PMC2ISH_MSG18)—Offset 1324h.....
2168
20.228Inbound Inter Processor Messages 19 PMC to ISH (PMC2ISH_MSG19)—Offset 1328h.....
2168
20.229Inbound Inter Processor Messages 20 PMC to ISH (PMC2ISH_MSG20)—Offset 132Ch ....
2168
20.230Inbound Inter Processor Messages 21 PMC to ISH (PMC2ISH_MSG21)—Offset 1330h.....
2169
20.231Inbound Inter Processor Messages 22 PMC to ISH (PMC2ISH_MSG22)—Offset 1334h.....
2169
20.232Inbound Inter Processor Messages 23 PMC to ISH (PMC2ISH_MSG23)—Offset 1338h.....
2170
20.233Inbound Inter Processor Messages 24 PMC to ISH (PMC2ISH_MSG24)—Offset 133Ch ....
2170
20.234Inbound Inter Processor Messages 25 PMC to ISH (PMC2ISH_MSG25)—Offset 1340h.....
2170
20.235Inbound Inter Processor Messages 26 PMC to ISH (PMC2ISH_MSG26)—Offset 1344h.....
2171
20.236Inbound Inter Processor Messages 27 PMC to ISH (PMC2ISH_MSG27)—Offset 1348h.....
2171
20.237Inbound Inter Processor Messages 28 PMC to ISH (PMC2ISH_MSG28)—Offset 134Ch ....
2172
20.238Inbound Inter Processor Messages 29 PMC to ISH (PMC2ISH_MSG29)—Offset 1350h.....
2172
20.239Inbound Inter Processor Messages 30 PMC to ISH (PMC2ISH_MSG30)—Offset 1354h.....
2172
20.240Inbound Inter Processor Messages 31 PMC to ISH (PMC2ISH_MSG31)—Offset 1358h.....
2173
20.241Inbound Inter Processor Messages 32 PMC to ISH (PMC2ISH_MSG32)—Offset 135Ch ....
2173
20.242Remap 0 (REMAP0)—Offset 1360h ...................................................................2173
20.243Remap 1 (REMAP1)—Offset 1364h ...................................................................2174
20.244Remap 2 (REMAP2)—Offset 1368h ...................................................................2174
20.245Remap 3 (REMAP3)—Offset 136Ch ...................................................................2174
20.246Remap 4 (REMAP4)—Offset 1370h ...................................................................2175
20.247Remap 5 (REMAP5)—Offset 1374h ...................................................................2175
20.248ISH IPC Busy Clear (ISH_IPC_BUSY_CLEAR)—Offset 1378h.................................2175
20.249ISH Fuse (ISH_FUSE)—Offset 137Ch ................................................................2176
20.250UMA Base Address LSB (UMA_RANGE_LOWER_0)—Offset 1380h..........................2177
20.251UMA Base Address MSB (UMA_RANGE_LOWER_1)—Offset 1384h .........................2177
20.252UMA Limit Address LSB (UMA_RANGE_UPPER_0)—Offset 1388h...........................2178
20.253UMA Base Address MSB (UMA_RANGE_UPPER_1)—Offset 138Ch ..........................2178
Datasheet Volume 2 of 2 69
20.254Outbound Inter Processor Messages 1 ISH to ISP (ISH2ISP_MSG1)—Offset 1390h . 2178
20.255Outbound Inter Processor Messages 2 ISH to ISP (ISH2ISP_MSG2)—Offset 1394h . 2179
20.256Outbound Inter Processor Messages 3 ISH to ISP (ISH2ISP_MSG3)—Offset 1398h . 2179
20.257Outbound Inter Processor Messages 4 ISH to ISP (ISH2ISP_MSG4)—Offset 139Ch. 2180
20.258Outbound Inter Processor Messages 5 ISH to ISP (ISH2ISP_MSG5)—Offset 13A0h. 2180
20.259Outbound Inter Processor Messages 6 ISH to ISP (ISH2ISP_MSG6)—Offset 13A4h. 2180
20.260Outbound Inter Processor Messages 7 ISH to ISP (ISH2ISP_MSG7)—Offset 13A8h. 2181
20.261Outbound Inter Processor Messages 8 ISH to ISP (ISH2ISP_MSG8)—Offset 13ACh 2181
20.262Outbound Inter Processor Messages 9 ISH to ISP (ISH2ISP_MSG9)—Offset 13B0h. 2182
20.263Outbound Inter Processor Messages 10 ISH to ISP (ISH2ISP_MSG10)—Offset 13B4h ....
2182
20.264Outbound Inter Processor Messages 11 ISH to ISP (ISH2ISP_MSG11)—Offset 13B8h ....
2183
20.265Outbound Inter Processor Messages 12 ISH to ISP (ISH2ISP_MSG12)—Offset 13BCh ....
2183
20.266Outbound Inter Processor Messages 13 ISH to ISP (ISH2ISP_MSG13)—Offset 13C0h ....
2183
20.267Outbound Inter Processor Messages 14 ISH to ISP (ISH2ISP_MSG14)—Offset 13C4h ....
2184
20.268Outbound Inter Processor Messages 15 ISH to ISP (ISH2ISP_MSG15)—Offset 13C8h ....
2184
20.269Outbound Inter Processor Messages 16 ISH to ISP (ISH2ISP_MSG16)—Offset 13CCh ....
2185
20.270Outbound Inter Processor Messages 17 ISH to ISP (ISH2ISP_MSG17)—Offset 13D0h ....
2185
20.271Outbound Inter Processor Messages 18 ISH to ISP (ISH2ISP_MSG18)—Offset 13D4h ....
2186
20.272Outbound Inter Processor Messages 19 ISH to ISP (ISH2ISP_MSG19)—Offset 13D8h ....
2186
20.273Outbound Inter Processor Messages 20 ISH to ISP (ISH2ISP_MSG20)—Offset 13DCh....
2186
20.274Outbound Inter Processor Messages 21 ISH To ISP (ISH2ISP_MSG21)—Offset 13E0h....
2187
20.275Outbound Inter Processor Messages 22 ISH to ISP (ISH2ISP_MSG22)—Offset 13E4h ....
2187
20.276Outbound Inter Processor Messages 23 ISH to ISP (ISH2ISP_MSG23)—Offset 13E8h ....
2188
20.277Outbound Inter Processor Messages 24 ISH to ISP (ISH2ISP_MSG24)—Offset 13ECh ....
2188
20.278Outbound Inter Processor Messages 25 ISH to ISP (ISH2ISP_MSG25)—Offset 13F0h ....
2189
20.279Outbound Inter Processor Messages 26 ISH to ISP (ISH2ISP_MSG26)—Offset 13F4h ....
2189
20.280Outbound Inter Processor Messages 27 ISH to ISP (ISH2ISP_MSG27)—Offset 13F8h ....
2189
20.281Outbound Inter Processor Messages 28 ISH to ISP (ISH2ISP_MSG28)—Offset 13FCh ....
2190
20.282Outbound Inter Processor Messages 29 ISH to ISP (ISH2ISP_MSG29)—Offset 1400h ....
2190
20.283Outbound Inter Processor Messages 30 ISH to ISP (ISH2ISP_MSG30)—Offset 1404h ....
2191
20.284Outbound Inter Processor Messages 31 ISH to ISP (ISH2ISP_MSG31)—Offset 1408h ....
2191
20.285Outbound Inter Processor Messages 32 ISH to ISP (ISH2ISP_MSG32)—Offset 140Ch ....
2192
20.286Inbound Inter Processor Messages 1 ISP to ISH (ISP2ISH_MSG1)—Offset 1410h ... 2192
20.287Inbound Inter Processor Messages 2 ISP to ISH (ISP2ISH_MSG2)—Offset 1414h ... 2192
70 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 71
20.331Outbound Inter Processor Messages 14 ISH to Audio (ISH2AUDIO_MSG14)—Offset
14C4h .......................................................................................................... 2211
20.332Outbound Inter Processor Messages 15 ISH to Audio (ISH2AUDIO_MSG15)—Offset
14C8h .......................................................................................................... 2212
20.333Outbound Inter Processor Messages 16 ISH to Audio (ISH2AUDIO_MSG16)—Offset
14CCh.......................................................................................................... 2212
20.334Outbound Inter Processor Messages 17 ISH to Audio (ISH2AUDIO_MSG17)—Offset
14D0h.......................................................................................................... 2213
20.335Outbound Inter Processor Messages 18 ISH to Audio (ISH2AUDIO_MSG18)—Offset
14D4h.......................................................................................................... 2213
20.336Outbound Inter Processor Messages 19 ISH to Audio (ISH2AUDIO_MSG19)—Offset
14D8h.......................................................................................................... 2213
20.337Outbound Inter Processor Messages 20 ISH to Audio (ISH2AUDIO_MSG20)—Offset
14DCh ......................................................................................................... 2214
20.338Outbound Inter Processor Messages 21 ISH to Audio (ISH2AUDIO_MSG21)—Offset
14E0h .......................................................................................................... 2214
20.339Outbound Inter Processor Messages 22 ISH to Audio (ISH2AUDIO_MSG22)—Offset
14E4h .......................................................................................................... 2215
20.340Outbound Inter Processor Messages 23 ISH to Audio (ISH2AUDIO_MSG23)—Offset
14E8h .......................................................................................................... 2215
20.341Outbound Inter Processor Messages 24 ISH to Audio (ISH2AUDIO_MSG24)—Offset
14ECh .......................................................................................................... 2216
20.342Outbound Inter Processor Messages 25 ISH to Audio (ISH2AUDIO_MSG25)—Offset 14F0h
2216
20.343Outbound Inter Processor Messages 26 ISH to Audio (ISH2AUDIO_MSG26)—Offset 14F4h
2216
20.344Outbound Inter Processor Messages 27 ISH to Audio (ISH2AUDIO_MSG27)—Offset 14F8h
2217
20.345Outbound Inter Processor Messages 28 ISH to Audio (ISH2AUDIO_MSG28)—Offset
14FCh .......................................................................................................... 2217
20.346Outbound Inter Processor Messages 29 ISH to Audio (ISH2AUDIO_MSG29)—Offset
1500h .......................................................................................................... 2218
20.347Outbound Inter Processor Messages 30 ISH to Audio (ISH2AUDIO_MSG30)—Offset
1504h .......................................................................................................... 2218
20.348Outbound Inter Processor Messages 31 ISH to Audio (ISH2AUDIO_MSG31)—Offset
1508h .......................................................................................................... 2219
20.349Outbound Inter Processor Messages 32 ISH to Audio (ISH2AUDIO_MSG32)—Offset
150Ch .......................................................................................................... 2219
20.350Inbound Inter Processor Messages 1 Audio to ISH (AUDIO2ISH_MSG1)—Offset 1510h ..
2219
20.351Inbound Inter Processor Messages 2 Audio to ISH (AUDIO2ISH_MSG2)—Offset 1514h ..
2220
20.352Inbound Inter Processor Messages 3 Audio to ISH (AUDIO2ISH_MSG3)—Offset 1518h ..
2220
20.353Inbound Inter Processor Messages 4 Audio to ISH (AUDIO2ISH_MSG4)—Offset 151Ch ..
2221
20.354Inbound Inter Processor Messages 5 Audio to ISH (AUDIO2ISH_MSG5)—Offset 1520h ..
2221
20.355Inbound Inter Processor Messages 6 Audio to ISH (AUDIO2ISH_MSG6)—Offset 1524h ..
2222
20.356Inbound Inter Processor Messages 7 Audio to ISH (AUDIO2ISH_MSG7)—Offset 1528h ..
2222
20.357Inbound Inter Processor Messages 8 Audio to ISH (AUDIO2ISH_MSG8)—Offset 152Ch ..
2222
20.358Inbound Inter Processor Messages 9 Audio to ISH (AUDIO2ISH_MSG9)—Offset 1530h ..
2223
20.359Inbound Inter Processor Messages 10 Audio to ISH (AUDIO2ISH_MSG10)—Offset 1534h
72 Datasheet Volume 2 of 2
2223
20.360Inbound Inter Processor Messages 11 Audio to ISH (AUDIO2ISH_MSG11)—Offset 1538h
2224
20.361Inbound Inter Processor Messages 12 Audio to ISH (AUDIO2ISH_MSG12)—Offset 153Ch
2224
20.362Inbound Inter Processor Messages 13 Audio to ISH (AUDIO2ISH_MSG13)—Offset 1540h
2225
20.363Inbound Inter Processor Messages 14 Audio to ISH (AUDIO2ISH_MSG14)—Offset 1544h
2225
20.364Inbound Inter Processor Messages 15 Audio to ISH (AUDIO2ISH_MSG15)—Offset 1548h
2225
20.365Inbound Inter Processor Messages 16 Audio to ISH (AUDIO2ISH_MSG16)—Offset 154Ch
2226
20.366Inbound Inter Processor Messages 17 Audio to ISH (AUDIO2ISH_MSG17)—Offset 1550h
2226
20.367Inbound Inter Processor Messages 18 Audio to ISH (AUDIO2ISH_MSG18)—Offset 1554h
2227
20.368Inbound Inter Processor Messages 19 Audio to ISH (AUDIO2ISH_MSG19)—Offset 1558h
2227
20.369Inbound Inter Processor Messages 20 Audio to ISH (AUDIO2ISH_MSG20)—Offset 155Ch
2228
20.370Inbound Inter Processor Messages 21 Audio to ISH (AUDIO2ISH_MSG21)—Offset 1560h
2228
20.371Inbound Inter Processor Messages 22 Audio to ISH (AUDIO2ISH_MSG22)—Offset 1564h
2228
20.372Inbound Inter Processor Messages 23 Audio to ISH (AUDIO2ISH_MSG23)—Offset 1568h
2229
20.373Inbound Inter Processor Messages 24 Audio to ISH (AUDIO2ISH_MSG24)—Offset 156Ch
2229
20.374Inbound Inter Processor Messages 25 Audio to ISH (AUDIO2ISH_MSG25)—Offset 1570h
2230
20.375Inbound Inter Processor Messages 26 Audio to ISH (AUDIO2ISH_MSG26)—Offset 1574h
2230
20.376Inbound Inter Processor Messages 27 Audio to ISH (AUDIO2ISH_MSG27)—Offset 1578h
2231
20.377Inbound Inter Processor Messages 28 Audio to ISH (AUDIO2ISH_MSG28)—Offset 157Ch
2231
20.378Inbound Inter Processor Messages 29 Audio to ISH (AUDIO2ISH_MSG29)—Offset 1580h
2231
20.379Inbound Inter Processor Messages 30 Audio to ISH (AUDIO2ISH_MSG30)—Offset 1584h
2232
20.380Inbound Inter Processor Messages 31 Audio to ISH (AUDIO2ISH_MSG31)—Offset 1588h
2232
20.381Inbound Inter Processor Messages 32 Audio to ISH (AUDIO2ISH_MSG32)—Offset 158Ch
2233
20.382Outbound Inter Processor Messages 1 ISH to Gfx (ISH2GFX_MSG1)—Offset 1590h 2233
20.383Outbound Inter Processor Messages 2 ISH to Gfx (ISH2GFX_MSG2)—Offset 1594h 2234
20.384Outbound Inter Processor Messages 3 ISH to Gfx (ISH2GFX_MSG3)—Offset 1598h 2234
20.385Outbound Inter Processor Messages 4 ISH to Gfx (ISH2GFX_MSG4)—Offset 159Ch 2234
20.386Outbound Inter Processor Messages 5 ISH to Gfx (ISH2GFX_MSG5)—Offset 15A0h 2235
20.387Outbound Inter Processor Messages 6 ISH to Gfx (ISH2GFX_MSG6)—Offset 15A4h 2235
20.388Outbound Inter Processor Messages 7 ISH to Gfx (ISH2GFX_MSG7)—Offset 15A8h 2236
20.389Outbound Inter Processor Messages 8 ISH to Gfx (ISH2GFX_MSG8)—Offset 15ACh 2236
20.390Outbound Inter Processor Messages 9 ISH to Gfx (ISH2GFX_MSG9)—Offset 15B0h 2237
20.391Outbound Inter Processor Messages 10 ISH to Gfx (ISH2GFX_MSG10)—Offset 15B4h....
2237
20.392Outbound Inter Processor Messages 11 ISH to Gfx (ISH2GFX_MSG11)—Offset 15B8h....
Datasheet Volume 2 of 2 73
2237
20.393Outbound Inter Processor Messages 12 ISH to Gfx (ISH2GFX_MSG12)—Offset 15BCh ...
2238
20.394Outbound Inter Processor Messages 13 ISH to Gfx (ISH2GFX_MSG13)—Offset 15C0h ...
2238
20.395Outbound Inter Processor Messages 14 ISH to Gfx (ISH2GFX_MSG14)—Offset 15C4h ...
2239
20.396Outbound Inter Processor Messages 15 ISH to Gfx (ISH2GFX_MSG15)—Offset 15C8h ...
2239
20.397Outbound Inter Processor Messages 16 ISH to Gfx (ISH2GFX_MSG16)—Offset 15CCh ...
2240
20.398Outbound Inter Processor Messages 17 ISH to Gfx (ISH2GFX_MSG17)—Offset 15D0h ...
2240
20.399Outbound Inter Processor Messages 18 ISH to Gfx (ISH2GFX_MSG18)—Offset 15D4h ...
2240
20.400Outbound Inter Processor Messages 19 ISH to Gfx (ISH2GFX_MSG19)—Offset 15D8h ...
2241
20.401Outbound Inter Processor Messages 20 ISH to Gfx (ISH2GFX_MSG20)—Offset 15DCh ...
2241
20.402Outbound Inter Processor Messages 21 ISH to Gfx (ISH2GFX_MSG21)—Offset 15E0h ...
2242
20.403Outbound Inter Processor Messages 22 ISH to Gfx (ISH2GFX_MSG22)—Offset 15E4h ...
2242
20.404Outbound Inter Processor Messages 23 ISH to Gfx (ISH2GFX_MSG23)—Offset 15E8h ...
2243
20.405Outbound Inter Processor Messages 24 ISH to Gfx (ISH2GFX_MSG24)—Offset 15ECh ...
2243
20.406Outbound Inter Processor Messages 25 ISH to Gfx (ISH2GFX_MSG25)—Offset 15F0h....
2243
20.407Outbound Inter Processor Messages 26 ISH to Gfx (ISH2GFX_MSG26)—Offset 15F4h....
2244
20.408Outbound Inter Processor Messages 27 ISH to Gfx (ISH2GFX_MSG27)—Offset 15F8h....
2244
20.409Outbound Inter Processor Messages 28 ISH to Gfx (ISH2GFX_MSG28)—Offset 15FCh ...
2245
20.410Outbound Inter Processor Messages 29 ISH to Gfx (ISH2GFX_MSG29)—Offset 1600h ...
2245
20.411Outbound Inter Processor Messages 30 ISH to Gfx (ISH2GFX_MSG30)—Offset 1604h ...
2246
20.412Outbound Inter Processor Messages 31 ISH to Gfx (ISH2GFX_MSG31)—Offset 1608h ...
2246
20.413Outbound Inter Processor Messages 32 ISH to Gfx (ISH2GFX_MSG32)—Offset 160Ch ...
2246
20.414Inbound Inter Processor Messages 1 Gfx to ISH (GFX2ISH_MSG1)—Offset 1610h .. 2247
20.415Inbound Inter Processor Messages 2 Gfx to ISH (GFX2ISH_MSG2)—Offset 1614h .. 2247
20.416Inbound Inter Processor Messages 3 Gfx to ISH (GFX2ISH_MSG3)—Offset 1618h .. 2248
20.417Inbound Inter Processor Messages 4 Gfx to ISH (GFX2ISH_MSG4)—Offset 161Ch.. 2248
20.418Inbound Inter Processor Messages 5 Gfx to ISH (GFX2ISH_MSG5)—Offset 1620h .. 2249
20.419Inbound Inter Processor Messages 6 Gfx to ISH (GFX2ISH_MSG6)—Offset 1624h .. 2249
20.420Inbound Inter Processor Messages 7 Gfx to ISH (GFX2ISH_MSG7)—Offset 1628h .. 2249
20.421Inbound Inter Processor Messages 8 Gfx to ISH (GFX2ISH_MSG8)—Offset 162Ch.. 2250
20.422Inbound Inter Processor Messages 9 Gfx to ISH (GFX2ISH_MSG9)—Offset 1630h .. 2250
20.423Inbound Inter Processor Messages 10 Gfx to ISH (GFX2ISH_MSG10)—Offset 1634h .....
2251
20.424Inbound Inter Processor Messages 11 Gfx to ISH (GFX2ISH_MSG11)—Offset 1638h .....
2251
20.425Inbound Inter Processor Messages 12 Gfx to ISH (GFX2ISH_MSG12)—Offset 163Ch .....
74 Datasheet Volume 2 of 2
2252
20.426Inbound Inter Processor Messages 13 Gfx to ISH (GFX2ISH_MSG13)—Offset 1640h ......
2252
20.427Inbound Inter Processor Messages 14 Gfx to ISH (GFX2ISH_MSG14)—Offset 1644h ......
2252
20.428Inbound Inter Processor Messages 15 Gfx to ISH (GFX2ISH_MSG15)—Offset 1648h ......
2253
20.429Inbound Inter Processor Messages 16 Gfx to ISH (GFX2ISH_MSG16)—Offset 164Ch ......
2253
20.430Inbound Inter Processor Messages 17 Gfx to ISH (GFX2ISH_MSG17)—Offset 1650h ......
2254
20.431Inbound Inter Processor Messages 18 Gfx to ISH (GFX2ISH_MSG18)—Offset 1654h ......
2254
20.432Inbound Inter Processor Messages 19 Gfx to ISH (GFX2ISH_MSG19)—Offset 1658h ......
2255
20.433Inbound Inter Processor Messages 20 Gfx to ISH (GFX2ISH_MSG20)—Offset 165Ch ......
2255
20.434Inbound Inter Processor Messages 21 Gfx to ISH (GFX2ISH_MSG21)—Offset 1660h ......
2255
20.435Inbound Inter Processor Messages 22 Gfx to ISH (GFX2ISH_MSG22)—Offset 1664h ......
2256
20.436Inbound Inter Processor Messages 23 Gfx to ISH (GFX2ISH_MSG23)—Offset 1668h ......
2256
20.437Inbound Inter Processor Messages 24 Gfx to ISH (GFX2ISH_MSG24)—Offset 166Ch ......
2257
20.438Inbound Inter Processor Messages 25 Gfx to ISH (GFX2ISH_MSG25)—Offset 1670h ......
2257
20.439Inbound Inter Processor Messages 26 Gfx to ISH (GFX2ISH_MSG26)—Offset 1674h ......
2258
20.440Inbound Inter Processor Messages 27 Gfx to ISH (GFX2ISH_MSG27)—Offset 1678h ......
2258
20.441Inbound Inter Processor Messages 28 Gfx to ISH (GFX2ISH_MSG28)—Offset 167Ch ......
2258
20.442Inbound Inter Processor Messages 29 Gfx to ISH (GFX2ISH_MSG29)—Offset 1680h ......
2259
20.443Inbound Inter Processor Messages 30 Gfx to ISH (GFX2ISH_MSG30)—Offset 1684h ......
2259
20.444Inbound Inter Processor Messages 31 Gfx to ISH (GFX2ISH_MSG31)—Offset 1688h ......
2260
20.445Inbound Inter Processor Messages 32 Gfx to ISH (GFX2ISH_MSG32)—Offset 168Ch ......
2260
20.446Inbound Doorbell ISP to ISH (ISP2ISH_DOORBELL)—Offset 1690h .......................2261
20.447Outbound Doorbell ISH to ISP (ISH2ISP_DOORBELL)—Offset 1694h .....................2261
20.448Inbound Doorbell Audio to ISH (AUDIO2ISH_DOORBELL)—Offset 1698h ...............2261
20.449Outbound Doorbell ISH to Audio (ISH2AUDIO_DOORBELL)—Offset 169Ch .............2262
20.450Inbound Doorbell GFX to ISH (GFX2ISH_DOORBELL)—Offset 16A0h .....................2262
20.451Outbound Doorbell ISH to GFx (ISH2GFX_DOORBELL)—Offset 16A4h ...................2263
20.452CSME to ISH Control and Status (CSME2ISH_CTRL_STATUS)—Offset 16A8h..........2263
20.453ISH IPC D0I3 Control (IPC_d0i3C_reg)—Offset 16D0h ........................................2264
20.454PMC to ISH Control and Status (ipc_pmc2ish_csr_reg)—Offset 16D4h...................2264
20.455ISP to ISH Control and Status (ipc_isp2ish_csr_reg)—Offset 16D8h......................2265
20.456Audio to ISH Control and Status (ipc_audio2ish_csr_reg)—Offset 16DCh ...............2265
20.457Peripheral Interrupt Status (PISR)—Offset 0h ....................................................2265
20.458Peripheral Interrupt Mask (PIMR)—Offset 4h .....................................................2267
20.459Host Peripheral Interrupt Mask (HOST_PIMR)—Offset 8h.....................................2269
20.460HOST Peripheral Interrupt Status (HOST_PISR)—Offset Ch..................................2269
Datasheet Volume 2 of 2 75
20.461Reserved (RESERVED2)—Offset 10h ................................................................ 2270
20.462Reserved (RESERVED3)—Offset 14h ................................................................ 2270
20.463Reserved (RESERVED4)—Offset 18h ................................................................ 2270
20.464Reserved (RESERVED5)—Offset 1Ch ................................................................ 2271
20.465Reserved (RESERVED6)—Offset 20h ................................................................ 2271
20.466Reserved (RESERVED7)—Offset 24h ................................................................ 2271
20.467Reserved (RESERVED8)—Offset 28h ................................................................ 2272
20.468Reserved (RESERVED9)—Offset 2Ch ................................................................ 2272
20.469Reserved (RESERVED10)—Offset 30h .............................................................. 2272
20.470ISH Host Firmware Status (ISH_HOST_FWSTS)—Offset 34h ............................... 2273
20.471Host Communication (HOST_COMM)—Offset 38h............................................... 2273
20.472ISH SEC Firmware Status (ISH_SEC_FWSTS)—Offset 3Ch .................................. 2273
20.473SEC Communication (SEC_COMM)—Offset 40h.................................................. 2274
20.474ISH Reset (ISH_RST)—Offset 44h ................................................................... 2274
20.475Inbound Doorbell HOST to ISH (HOST2ISH_DOORBELL)—Offset 48h.................... 2274
20.476Inbound Doorbell PMC to ISH (PMC2ISH_DOORBELL)—Offset 4Ch ....................... 2275
20.477Inbound Doorbell SEC to ISH (SEC2ISH_DOORBELL)—Offset 50h ........................ 2275
20.478Outbound Doorbell ISH to Host (ISH2HOST_DOORBELL)—Offset 54h ................... 2276
20.479Outbound Doorbell ISH to PMC (ISH2PMC_DOORBELL)—Offset 58h ..................... 2276
20.480Outbound Doorbell ISH to SEC (ISH2SEC_DOORBELL)—Offset 5Ch ...................... 2276
20.481Outbound Inter-processor Messages 1 ISH to Host (ISH2HOST_MSG1)—Offset 60h 2277
20.482Outbound Inter-processor Messages 2 ISH to Host (ISH2HOST_MSG2)—Offset 64h 2277
20.483Outbound Inter-processor Messages 3 ISH to Host (ISH2HOST_MSG3)—Offset 68h 2278
20.484Outbound Inter-processor Messages 4 ISH to Host (ISH2HOST_MSG4)—Offset 6Ch2278
20.485Outbound Inter-processor Messages 5 ISH to Host (ISH2HOST_MSG5)—Offset 70h 2278
20.486Outbound Inter-processor Messages 6 ISH to Host (ISH2HOST_MSG6)—Offset 74h 2279
20.487Outbound Inter-processor Messages 7 ISH to Host (ISH2HOST_MSG7)—Offset 78h 2279
20.488Outbound Inter-processor Messages 8 ISH to Host (ISH2HOST_MSG8)—Offset 7Ch2280
20.489Outbound Inter-processor Messages 9 ISH to Host (ISH2HOST_MSG9)—Offset 80h 2280
20.490Outbound Inter-processor Messages 10 ISH to Host (ISH2HOST_MSG10)—Offset 84h ...
2280
20.491Outbound Inter-processor Messages 11 ISH to Host (ISH2HOST_MSG11)—Offset 88h ...
2281
20.492Outbound Inter-processor Messages 12 ISH to Host (ISH2HOST_MSG12)—Offset 8Ch...
2281
20.493Outbound Inter-processor Messages 13 ISH to Host (ISH2HOST_MSG13)—Offset 90h ...
2282
20.494Outbound Inter-processor Messages 14 ISH to Host (ISH2HOST_MSG14)—Offset 94h ...
2282
20.495Outbound Inter-processor Messages 15 ISH to Host (ISH2HOST_MSG15)—Offset 98h ...
2282
20.496Outbound Inter-processor Messages 16 ISH to Host (ISH2HOST_MSG16)—Offset 9Ch...
2283
20.497Outbound Inter-processor Messages 17 ISH to Host (ISH2HOST_MSG17)—Offset A0h...
2283
20.498Outbound Inter-processor Messages 18 ISH to Host (ISH2HOST_MSG18)—Offset A4h...
2284
20.499Outbound Inter-processor Messages 19 ISH to Host (ISH2HOST_MSG19)—Offset A8h...
2284
20.500Outbound Inter-processor Messages 20 ISH to Host (ISH2HOST_MSG20)—Offset ACh ..
2284
20.501Outbound Inter-processor Messages 21 ISH to Host (ISH2HOST_MSG21)—Offset B0h...
2285
20.502Outbound Inter-processor Messages 22 ISH to Host (ISH2HOST_MSG22)—Offset B4h...
2285
20.503Outbound Inter-processor Messages 23 ISH to Host (ISH2HOST_MSG23)—Offset B8h...
76 Datasheet Volume 2 of 2
2286
20.504Outbound Inter-processor Messages 24 ISH to Host (ISH2HOST_MSG24)—Offset BCh ...
2286
20.505Outbound Inter-processor Messages 25 ISH to Host (ISH2HOST_MSG25)—Offset C0h ...
2286
20.506Outbound Inter-processor Messages 26 ISH to Host (ISH2HOST_MSG26)—Offset C4h ...
2287
20.507Outbound Inter-processor Messages 27 ISH to Host (ISH2HOST_MSG27)—Offset C8h ...
2287
20.508Outbound Inter-processor Messages 28 ISH to Host (ISH2HOST_MSG28)—Offset CCh ...
2288
20.509Outbound Inter-processor Messages 29 ISH to Host (ISH2HOST_MSG29)—Offset D0h ...
2288
20.510Outbound Inter-processor Messages 30 ISH to Host (ISH2HOST_MSG30)—Offset D4h ...
2288
20.511Outbound Inter-processor Messages 31 ISH to Host (ISH2HOST_MSG31)—Offset D8h ...
2289
20.512Outbound Inter-processor Messages 32 ISH to Host (ISH2HOST_MSG32)—Offset DCh ...
2289
20.513Inbound Inter-processor Messages 1 Host to ISH (HOST2ISH_MSG1)—Offset E0h ..2290
20.514Inbound Inter-processor Messages 2 Host to ISH (HOST2ISH_MSG2)—Offset E4h ..2290
20.515Inbound Inter-processor Messages 3 Host to ISH (HOST2ISH_MSG3)—Offset E8h ..2290
20.516Inbound Inter-processor Messages 4 Host to ISH (HOST2ISH_MSG4)—Offset ECh..2291
20.517Inbound Inter-processor Messages 5 Host to ISH (HOST2ISH_MSG5)—Offset F0h ..2291
20.518Inbound Inter-processor Messages 6 Host to ISH (HOST2ISH_MSG6)—Offset F4h ..2292
20.519Inbound Inter-processor Messages 7 Host to ISH (HOST2ISH_MSG7)—Offset F8h ..2292
20.520Inbound Inter-processor Messages 8 Host to ISH (HOST2ISH_MSG8)—Offset FCh ..2292
20.521Inbound Inter-processor Messages 9 Host to ISH (HOST2ISH_MSG9)—Offset 100h 2293
20.522Inbound Inter-processor Messages 10 Host to ISH (HOST2ISH_MSG10)—Offset 104h....
2293
20.523Inbound Inter-processor Messages 11 Host to ISH (HOST2ISH_MSG11)—Offset 108h....
2294
20.524Inbound Inter-processor Messages 12 Host to ISH (HOST2ISH_MSG12)—Offset 10Ch....
2294
20.525Inbound Inter-processor Messages 13 Host to ISH (HOST2ISH_MSG13)—Offset 110h....
2294
20.526Inbound Inter-processor Messages 14 Host to ISH (HOST2ISH_MSG14)—Offset 114h....
2295
20.527Inbound Inter-processor Messages 15 Host to ISH (HOST2ISH_MSG15)—Offset 118h....
2295
20.528Inbound Inter-processor Messages 16 Host to ISH (HOST2ISH_MSG16)—Offset 11Ch....
2296
20.529Inbound Inter-processor Messages 17 Host to ISH (HOST2ISH_MSG17)—Offset 120h....
2296
20.530Inbound Inter-processor Messages 18 Host to ISH (HOST2ISH_MSG18)—Offset 124h....
2296
20.531Inbound Inter-processor Messages 19 Host to ISH (HOST2ISH_MSG19)—Offset 128h....
2297
20.532Inbound Inter-processor Messages 20 Host to ISH (HOST2ISH_MSG20)—Offset 12Ch....
2297
20.533Inbound Inter-processor Messages 21 Host to ISH (HOST2ISH_MSG21)—Offset 130h....
2298
20.534Inbound Inter-processor Messages 22 Host to ISH (HOST2ISH_MSG22)—Offset 134h....
2298
20.535Inbound Inter-processor Messages 23 Host to ISH (HOST2ISH_MSG23)—Offset 138h....
2298
20.536Inbound Inter-processor Messages 24 Host to ISH (HOST2ISH_MSG24)—Offset 13Ch....
Datasheet Volume 2 of 2 77
2299
20.537Inbound Inter-processor Messages 25 Host to ISH (HOST2ISH_MSG25)—Offset 140h ...
2299
20.538Inbound Inter-processor Messages 26 Host to ISH (HOST2ISH_MSG26)—Offset 144h ...
2300
20.539Inbound Inter-processor Messages 27 Host to ISH (HOST2ISH_MSG27)—Offset 148h ...
2300
20.540Inbound Inter-processor Messages 28 Host to ISH (HOST2ISH_MSG28)—Offset 14Ch ...
2300
20.541Inbound Inter-processor Messages 29 Host to ISH (HOST2ISH_MSG29)—Offset 150h ...
2301
20.542Inbound Inter-processor Messages 30 Host to ISH (HOST2ISH_MSG30)—Offset 154h ...
2301
20.543Inbound Inter-processor Messages 31 Host to ISH (HOST2ISH_MSG31)—Offset 158h ...
2302
20.544Inbound Inter-processor Messages 32 Host to ISH (HOST2ISH_MSG32)—Offset 15Ch ...
2302
20.545Outbound Inter-processor Messages 1 ISH to SEC (ISH2SEC_MSG1)—Offset 160h. 2302
20.546Outbound Inter-processor Messages 2 ISH to SEC (ISH2SEC_MSG2)—Offset 164h. 2303
20.547Outbound Inter-processor Messages 3 ISH to SEC (ISH2SEC_MSG3)—Offset 168h. 2303
20.548Outbound Inter-processor Messages 4 ISH to SEC (ISH2SEC_MSG4)—Offset 16Ch 2304
20.549Outbound Inter-processor Messages 5 ISH to SEC (ISH2SEC_MSG5)—Offset 170h. 2304
20.550Outbound Inter-processor Messages 6 ISH to SEC (ISH2SEC_MSG6)—Offset 174h. 2304
20.551Outbound Inter-processor Messages 7 ISH to SEC (ISH2SEC_MSG7)—Offset 178h. 2305
20.552Outbound Inter-processor Messages 8 ISH to SEC (ISH2SEC_MSG8)—Offset 17Ch 2305
20.553Outbound Inter-processor Messages 9 ISH to SEC (ISH2SEC_MSG9)—Offset 180h. 2306
20.554Outbound Inter-processor Messages 10 ISH to SEC (ISH2SEC_MSG10)—Offset 184h ....
2306
20.555Outbound Inter-processor Messages 11 ISH to SEC (ISH2SEC_MSG11)—Offset 188h ....
2306
20.556Outbound Inter-processor Messages 12 ISH to SEC (ISH2SEC_MSG12)—Offset 18Ch ....
2307
20.557Outbound Inter-processor Messages 13 ISH to SEC (ISH2SEC_MSG13)—Offset 190h ....
2307
20.558Outbound Inter-processor Messages 14 ISH to SEC (ISH2SEC_MSG14)—Offset 194h ....
2308
20.559Outbound Inter-processor Messages 15 ISH to SEC (ISH2SEC_MSG15)—Offset 198h ....
2308
20.560Outbound Inter-processor Messages 16 ISH to SEC (ISH2SEC_MSG16)—Offset 19Ch ....
2308
20.561Outbound Inter-processor Messages 17 ISH to SEC (ISH2SEC_MSG17)—Offset 1A0h ....
2309
20.562Outbound Inter-processor Messages 18 ISH to SEC (ISH2SEC_MSG18)—Offset 1A4h ....
2309
20.563Outbound Inter-processor Messages 19 ISH to SEC (ISH2SEC_MSG19)—Offset 1A8h ....
2310
20.564Outbound Inter-processor Messages 20 ISH to SEC (ISH2SEC_MSG20)—Offset 1ACh....
2310
20.565Outbound Inter-processor Messages 21 ISH to SEC (ISH2SEC_MSG21)—Offset 1B0h ....
2310
20.566Outbound Inter-processor Messages 22 ISH to SEC (ISH2SEC_MSG22)—Offset 1B4h ....
2311
20.567Outbound Inter-processor Messages 23 ISH to SEC (ISH2SEC_MSG23)—Offset 1B8h ....
2311
20.568Outbound Inter-processor Messages 24 ISH to SEC (ISH2SEC_MSG24)—Offset 1BCh....
2312
20.569Outbound Inter-processor Messages 25 ISH to SEC (ISH2SEC_MSG25)—Offset 1C0h ....
78 Datasheet Volume 2 of 2
2312
20.570Outbound Inter-processor Messages 26 ISH to SEC (ISH2SEC_MSG26)—Offset 1C4h ....
2312
20.571Outbound Inter-processor Messages 27 ISH to SEC (ISH2SEC_MSG27)—Offset 1C8h ....
2313
20.572Outbound Inter-processor Messages 28 ISH to SEC (ISH2SEC_MSG28)—Offset 1CCh ....
2313
20.573Outbound Inter-processor Messages 29 ISH to SEC (ISH2SEC_MSG29)—Offset 1D0h ....
2314
20.574Outbound Inter-processor Messages 30 ISH to SEC (ISH2SEC_MSG30)—Offset 1D4h ....
2314
20.575Outbound Inter-processor Messages 31 ISH to SEC (ISH2SEC_MSG31)—Offset 1D8h ....
2314
20.576Outbound Inter-processor Messages 32 ISH to SEC (ISH2SEC_MSG32)—Offset 1DCh ....
2315
20.577Inbound Inter-processor Messages 1 SEC to ISH (SEC2ISH_MSG1)—Offset 1E0h ...2315
20.578Inbound Inter-processor Messages 2 SEC to ISH (SEC2ISH_MSG2)—Offset 1E4h ...2316
20.579Inbound Inter-processor Messages 3 SEC to ISH (SEC2ISH_MSG3)—Offset 1E8h ...2316
20.580Inbound Inter-processor Messages 4 SEC to ISH (SEC2ISH_MSG4)—Offset 1ECh ...2316
20.581Inbound Inter-processor Messages 5 SEC to ISH (SEC2ISH_MSG5)—Offset 1F0h ...2317
20.582Inbound Inter-processor Messages 6 SEC to ISH (SEC2ISH_MSG6)—Offset 1F4h ...2317
20.583Inbound Inter-processor Messages 7 SEC to ISH (SEC2ISH_MSG7)—Offset 1F8h ...2318
20.584Inbound Inter-processor Messages 8 SEC to ISH (SEC2ISH_MSG8)—Offset 1FCh ...2318
20.585Inbound Inter-processor Messages 9 SEC to ISH (SEC2ISH_MSG9)—Offset 200h ...2318
20.586Inbound Inter-processor Messages 10 SEC to ISH (SEC2ISH_MSG10)—Offset 204h2319
20.587Inbound Inter-processor Messages 11 SEC to ISH (SEC2ISH_MSG11)—Offset 208h2319
20.588Inbound Inter-processor Messages 12 SEC to ISH (SEC2ISH_MSG12)—Offset 20Ch2320
20.589Inbound Inter-processor Messages 13 SEC to ISH (SEC2ISH_MSG13)—Offset 210h2320
20.590Inbound Inter-processor Messages 14 SEC to ISH (SEC2ISH_MSG14)—Offset 214h2320
20.591Inbound Inter-processor Messages 15 SEC to ISH (SEC2ISH_MSG15)—Offset 218h2321
20.592Inbound Inter-processor Messages 16 SEC to ISH (SEC2ISH_MSG16)—Offset 21Ch2321
20.593Inbound Inter-processor Messages 17 SEC to ISH (SEC2ISH_MSG17)—Offset 220h2322
20.594Inbound Inter-processor Messages 18 SEC to ISH (SEC2ISH_MSG18)—Offset 224h2322
20.595Inbound Inter-processor Messages 19 SEC to ISH (SEC2ISH_MSG19)—Offset 228h2322
20.596Inbound Inter-processor Messages 20 SEC to ISH (SEC2ISH_MSG20)—Offset 22Ch2323
20.597Inbound Inter-processor Messages 21 SEC to ISH (SEC2ISH_MSG21)—Offset 230h2323
20.598Inbound Inter-processor Messages 22 SEC to ISH (SEC2ISH_MSG22)—Offset 234h2324
20.599Inbound Inter-processor Messages 23 SEC to ISH (SEC2ISH_MSG23)—Offset 238h2324
20.600Inbound Inter-processor Messages 24 SEC to ISH (SEC2ISH_MSG24)—Offset 23Ch2324
20.601Inbound Inter-processor Messages 25 SEC to ISH (SEC2ISH_MSG25)—Offset 240h2325
20.602Inbound Inter-processor Messages 26 SEC to ISH (SEC2ISH_MSG26)—Offset 244h2325
20.603Inbound Inter-processor Messages 27 SEC to ISH (SEC2ISH_MSG27)—Offset 248h2326
20.604Inbound Inter-processor Messages 28 SEC to ISH (SEC2ISH_MSG28)—Offset 24Ch2326
20.605Inbound Inter-processor Messages 29 SEC to ISH (SEC2ISH_MSG29)—Offset 250h2326
20.606Inbound Inter-processor Messages 30 SEC to ISH (SEC2ISH_MSG30)—Offset 254h2327
20.607Inbound Inter-processor Messages 31 SEC to ISH (SEC2ISH_MSG31)—Offset 258h2327
20.608Inbound Inter-processor Messages 32 SEC to ISH (SEC2ISH_MSG32)—Offset 25Ch2328
20.609Outbound Inter-processor Messages 1 ISH to PMC (ISH2PMC_MSG1)—Offset 260h 2328
20.610Outbound Inter-processor Messages 2 ISH to PMC (ISH2PMC_MSG2)—Offset 264h 2328
20.611Outbound Inter-processor Messages 3 ISH to PMC (ISH2PMC_MSG3)—Offset 268h 2329
20.612Outbound Inter-processor Messages 4 ISH to PMC (ISH2PMC_MSG4)—Offset 26Ch 2329
20.613Outbound Inter-processor Messages 5 ISH to PMC (ISH2PMC_MSG5)—Offset 270h 2330
20.614Outbound Inter-processor Messages 6 ISH to PMC (ISH2PMC_MSG6)—Offset 274h 2330
20.615Outbound Inter-processor Messages 7 ISH to PMC (ISH2PMC_MSG7)—Offset 278h 2330
20.616Outbound Inter-processor Messages 8 ISH to PMC (ISH2PMC_MSG8)—Offset 27Ch 2331
Datasheet Volume 2 of 2 79
20.617Outbound Inter-processor Messages 9 ISH to PMC (ISH2PMC_MSG9)—Offset 280h 2331
20.618Outbound Inter-processor Messages 10 ISH to PMC (ISH2PMC_MSG10)—Offset 284h ...
2332
20.619Outbound Inter-processor Messages 11 ISH to PMC (ISH2PMC_MSG11)—Offset 288h ...
2332
20.620Outbound Inter-processor Messages 12 ISH to PMC (ISH2PMC_MSG12)—Offset 28Ch ...
2332
20.621Outbound Inter-processor Messages 13 ISH to PMC (ISH2PMC_MSG13)—Offset 290h ...
2333
20.622Outbound Inter-processor Messages 14 ISH to PMC (ISH2PMC_MSG14)—Offset 294h ...
2333
20.623Outbound Inter-processor Messages 15 ISH to PMC (ISH2PMC_MSG15)—Offset 298h ...
2334
20.624Outbound Inter-processor Messages 16 ISH to PMC (ISH2PMC_MSG16)—Offset 29Ch ...
2334
20.625Outbound Inter-processor Messages 17 ISH to PMC (ISH2PMC_MSG17)—Offset 2A0h ...
2334
20.626Outbound Inter-processor Messages 18 ISH to PMC (ISH2PMC_MSG18)—Offset 2A4h ...
2335
20.627Outbound Inter-processor Messages 19 ISH to PMC (ISH2PMC_MSG19)—Offset 2A8h ...
2335
20.628Outbound Inter-processor Messages 20 ISH to PMC (ISH2PMC_MSG20)—Offset 2ACh ...
2336
20.629Outbound Inter-processor Messages 21 ISH to PMC (ISH2PMC_MSG21)—Offset 2B0h ...
2336
20.630Outbound Inter-processor Messages 22 ISH to PMC (ISH2PMC_MSG22)—Offset 2B4h ...
2336
20.631Outbound Inter-processor Messages 23 ISH to PMC (ISH2PMC_MSG23)—Offset 2B8h ...
2337
20.632Outbound Inter-processor Messages 24 ISH to PMC (ISH2PMC_MSG24)—Offset 2BCh ...
2337
20.633Outbound Inter-processor Messages 25 ISH to PMC (ISH2PMC_MSG25)—Offset 2C0h ...
2338
20.634Outbound Inter-processor Messages 26 ISH to PMC (ISH2PMC_MSG26)—Offset 2C4h ...
2338
20.635Outbound Inter-processor Messages 27 ISH to PMC (ISH2PMC_MSG27)—Offset 2C8h ...
2338
20.636Outbound Inter-processor Messages 28 ISH to PMC (ISH2PMC_MSG28)—Offset 2CCh ...
2339
20.637Outbound Inter-processor Messages 29 ISH to PMC (ISH2PMC_MSG29)—Offset 2D0h ...
2339
20.638Outbound Inter-processor Messages 30 ISH to PMC (ISH2PMC_MSG30)—Offset 2D4h ...
2340
20.639Outbound Inter-processor Messages 31 ISH to PMC (ISH2PMC_MSG31)—Offset 2D8h ...
2340
20.640Outbound Inter-processor Messages 32 ISH to PMC (ISH2PMC_MSG32)—Offset 2DCh...
2340
20.641Inbound Inter-processor Messages 1 PMC to ISH (PMC2ISH_MSG1)—Offset 2E0h .. 2341
20.642Inbound Inter-processor Messages 2 PMC to ISH (PMC2ISH_MSG2)—Offset 2E4h .. 2341
20.643Inbound Inter-processor Messages 3 PMC to ISH (PMC2ISH_MSG3)—Offset 2E8h .. 2342
20.644Inbound Inter-processor Messages 4 PMC to ISH (PMC2ISH_MSG4)—Offset 2ECh.. 2342
20.645Inbound Inter-processor Messages 5 PMC to ISH (PMC2ISH_MSG5)—Offset 2F0h .. 2342
20.646Inbound Inter-processor Messages 6 PMC to ISH (PMC2ISH_MSG6)—Offset 2F4h .. 2343
20.647Inbound Inter-processor Messages 7 PMC to ISH (PMC2ISH_MSG7)—Offset 2F8h .. 2343
20.648Inbound Inter-processor Messages 8 PMC to ISH (PMC2ISH_MSG8)—Offset 2FCh .. 2344
20.649Inbound Inter-processor Messages 9 PMC to ISH (PMC2ISH_MSG9)—Offset 300h .. 2344
20.650Inbound Inter-processor Messages 10 PMC to ISH (PMC2ISH_MSG10)—Offset 304h .....
80 Datasheet Volume 2 of 2
2344
20.651Inbound Inter-processor Messages 11 PMC to ISH (PMC2ISH_MSG11)—Offset 308h ......
2345
20.652Inbound Inter-processor Messages 12 PMC to ISH (PMC2ISH_MSG12)—Offset 30Ch......
2345
20.653Inbound Inter-processor Messages 13 PMC to ISH (PMC2ISH_MSG13)—Offset 310h ......
2346
20.654Inbound Inter-processor Messages 14 PMC to ISH (PMC2ISH_MSG14)—Offset 314h ......
2346
20.655Inbound Inter-processor Messages 15 PMC to ISH (PMC2ISH_MSG15)—Offset 318h ......
2346
20.656Inbound Inter-processor Messages 16 PMC to ISH (PMC2ISH_MSG16)—Offset 31Ch......
2347
20.657Inbound Inter-processor Messages 17 PMC to ISH (PMC2ISH_MSG17)—Offset 320h ......
2347
20.658Inbound Inter-processor Messages 18 PMC to ISH (PMC2ISH_MSG18)—Offset 324h ......
2348
20.659Inbound Inter-processor Messages 19 PMC to ISH (PMC2ISH_MSG19)—Offset 328h ......
2348
20.660Inbound Inter-processor Messages 20 PMC to ISH (PMC2ISH_MSG20)—Offset 32Ch......
2348
20.661Inbound Inter-processor Messages 21 PMC to ISH (PMC2ISH_MSG21)—Offset 330h ......
2349
20.662Inbound Inter-processor Messages 22 PMC to ISH (PMC2ISH_MSG22)—Offset 334h ......
2349
20.663Inbound Inter-processor Messages 23 PMC to ISH (PMC2ISH_MSG23)—Offset 338h ......
2350
20.664Inbound Inter-processor Messages 24 PMC to ISH (PMC2ISH_MSG24)—Offset 33Ch......
2350
20.665Inbound Inter-processor Messages 25 PMC to ISH (PMC2ISH_MSG25)—Offset 340h ......
2350
20.666Inbound Inter-processor Messages 26 PMC to ISH (PMC2ISH_MSG26)—Offset 344h ......
2351
20.667Inbound Inter-processor Messages 27 PMC to ISH (PMC2ISH_MSG27)—Offset 348h ......
2351
20.668Inbound Inter-processor Messages 28 PMC to ISH (PMC2ISH_MSG28)—Offset 34Ch......
2352
20.669Inbound Inter-processor Messages 29 PMC to ISH (PMC2ISH_MSG29)—Offset 350h ......
2352
20.670Inbound Inter-processor Messages 30 PMC to ISH (PMC2ISH_MSG30)—Offset 354h ......
2352
20.671Inbound Inter-processor Messages 31 PMC to ISH (PMC2ISH_MSG31)—Offset 358h ......
2353
20.672Inbound Inter-processor Messages 32 PMC to ISH (PMC2ISH_MSG32)—Offset 35Ch......
2353
20.673Remap 0 (REMAP0)—Offset 360h .....................................................................2353
20.674Remap 1 (REMAP1)—Offset 364h .....................................................................2354
20.675Remap 2 (REMAP2)—Offset 368h .....................................................................2354
20.676Remap 3 (REMAP3)—Offset 36Ch.....................................................................2354
20.677Remap 4 (REMAP4)—Offset 370h .....................................................................2355
20.678Remap 5 (REMAP5)—Offset 374h .....................................................................2355
20.679ISH IPC Busy Clear (ISH_IPC_BUSY_CLEAR)—Offset 378h ..................................2355
20.680ISH Fuse (ISH_FUSE)—Offset 37Ch..................................................................2356
20.681UMA Base Address LSB (UMA_RANGE_LOWER_0)—Offset 380h ...........................2357
20.682UMA Base Address MSB (UMA_RANGE_LOWER_1)—Offset 384h...........................2357
20.683UMA Limit Address LSB (UMA_RANGE_UPPER_0)—Offset 388h ............................2357
20.684UMA Base Address MSB (UMA_RANGE_UPPER_1)—Offset 38Ch............................2358
Datasheet Volume 2 of 2 81
20.685Outbound Inter-processor Messages 1 ISH to ISP (ISH2ISP_MSG1)—Offset 390h .. 2358
20.686Outbound Inter-processor Messages 2 ISH to ISP (ISH2ISP_MSG2)—Offset 394h .. 2359
20.687Outbound Inter-processor Messages 3 ISH to ISP (ISH2ISP_MSG3)—Offset 398h .. 2359
20.688Outbound Inter-processor Messages 4 ISH to ISP (ISH2ISP_MSG4)—Offset 39Ch .. 2360
20.689Outbound Inter-processor Messages 5 ISH to ISP (ISH2ISP_MSG5)—Offset 3A0h .. 2360
20.690Outbound Inter-processor Messages 6 ISH to ISP (ISH2ISP_MSG6)—Offset 3A4h .. 2360
20.691Outbound Inter-processor Messages 7 ISH to ISP (ISH2ISP_MSG7)—Offset 3A8h .. 2361
20.692Outbound Inter-processor Messages 8 ISH to ISP (ISH2ISP_MSG8)—Offset 3ACh .. 2361
20.693Outbound Inter-processor Messages 9 ISH to ISP (ISH2ISP_MSG9)—Offset 3B0h .. 2362
20.694Outbound Inter-processor Messages 10 ISH to ISP (ISH2ISP_MSG10)—Offset 3B4h......
2362
20.695Outbound Inter-processor Messages 11 ISH to ISP (ISH2ISP_MSG11)—Offset 3B8h......
2363
20.696Outbound Inter-processor Messages 12 ISH to ISP (ISH2ISP_MSG12)—Offset 3BCh .....
2363
20.697Outbound Inter-processor Messages 13 ISH to ISP (ISH2ISP_MSG13)—Offset 3C0h......
2363
20.698Outbound Inter-processor Messages 14 ISH to ISP (ISH2ISP_MSG14)—Offset 3C4h......
2364
20.699Outbound Inter-processor Messages 15 ISH to ISP (ISH2ISP_MSG15)—Offset 3C8h......
2364
20.700Outbound Inter-processor Messages 16 ISH to ISP (ISH2ISP_MSG16)—Offset 3CCh .....
2365
20.701Outbound Inter-processor Messages 17 ISH to ISP (ISH2ISP_MSG17)—Offset 3D0h .....
2365
20.702Outbound Inter-processor Messages 18 ISH to ISP (ISH2ISP_MSG18)—Offset 3D4h .....
2366
20.703Outbound Inter-processor Messages 19 ISH to ISP (ISH2ISP_MSG19)—Offset 3D8h .....
2366
20.704Outbound Inter-processor Messages 20 ISH to ISP (ISH2ISP_MSG20)—Offset 3DCh .....
2366
20.705Outbound Inter-processor Messages 21 ISH to ISP (ISH2ISP_MSG21)—Offset 3E0h......
2367
20.706Outbound Inter-processor Messages 22 ISH to ISP (ISH2ISP_MSG22)—Offset 3E4h......
2367
20.707Outbound Inter-processor Messages 23 ISH to ISP (ISH2ISP_MSG23)—Offset 3E8h......
2368
20.708Outbound Inter-processor Messages 24 ISH to ISP (ISH2ISP_MSG24)—Offset 3ECh......
2368
20.709Outbound Inter-processor Messages 25 ISH to ISP (ISH2ISP_MSG25)—Offset 3F0h ......
2369
20.710Outbound Inter-processor Messages 26 ISH to ISP (ISH2ISP_MSG26)—Offset 3F4h ......
2369
20.711Outbound Inter-processor Messages 27 ISH to ISP (ISH2ISP_MSG27)—Offset 3F8h ......
2369
20.712Outbound Inter-processor Messages 28 ISH to ISP (ISH2ISP_MSG28)—Offset 3FCh......
2370
20.713Outbound Inter-processor Messages 29 ISH to ISP (ISH2ISP_MSG29)—Offset 400h......
2370
20.714Outbound Inter-processor Messages 30 ISH to ISP (ISH2ISP_MSG30)—Offset 404h......
2371
20.715Outbound Inter-processor Messages 31 ISH to ISP (ISH2ISP_MSG31)—Offset 408h......
2371
20.716Outbound Inter-processor Messages 32 ISH to ISP (ISH2ISP_MSG32)—Offset 40Ch......
2372
20.717Inbound Inter-processor Messages 1 ISP to ISH (ISP2ISH_MSG1)—Offset 410h .... 2372
20.718Inbound Inter-processor Messages2 ISP to ISH (ISP2ISH_MSG2)—Offset 414h ..... 2372
82 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 83
20.762Outbound Inter-processor Messages 14 ISH to Audio (ISH2AUDIO_MSG14)—Offset 4C4h
2391
20.763Outbound Inter-processor Messages 15 ISH to Audio (ISH2AUDIO_MSG15)—Offset 4C8h
2392
20.764Outbound Inter-processor Messages 16 ISH to Audio (ISH2AUDIO_MSG16)—Offset 4CCh
2392
20.765Outbound Inter-processor Messages 17 ISH to Audio (ISH2AUDIO_MSG17)—Offset 4D0h
2393
20.766Outbound Inter-processor Messages 18 ISH to Audio (ISH2AUDIO_MSG18)—Offset 4D4h
2393
20.767Outbound Inter-processor Messages 19 ISH to Audio (ISH2AUDIO_MSG19)—Offset 4D8h
2393
20.768Outbound Inter-processor Messages 20 ISH to Audio (ISH2AUDIO_MSG20)—Offset 4DCh
2394
20.769Outbound Inter-processor Messages 21 ISH to Audio (ISH2AUDIO_MSG21)—Offset 4E0h
2394
20.770Outbound Inter-processor Messages 22 ISH to Audio (ISH2AUDIO_MSG22)—Offset 4E4h
2395
20.771Outbound Inter-processor Messages 23 ISH to Audio (ISH2AUDIO_MSG23)—Offset 4E8h
2395
20.772Outbound Inter-processor Messages 24 ISH to Audio (ISH2AUDIO_MSG24)—Offset 4ECh
2396
20.773Outbound Inter-processor Messages 25 ISH to Audio (ISH2AUDIO_MSG25)—Offset 4F0h
2396
20.774Outbound Inter-processor Messages 26 ISH to Audio (ISH2AUDIO_MSG26)—Offset 4F4h
2396
20.775Outbound Inter-processor Messages 27 ISH to Audio (ISH2AUDIO_MSG27)—Offset 4F8h
2397
20.776Outbound Inter-processor Messages 28 ISH to Audio (ISH2AUDIO_MSG28)—Offset 4FCh
2397
20.777Outbound Inter-processor Messages 29 ISH to Audio (ISH2AUDIO_MSG29)—Offset 500h
2398
20.778Outbound Inter-processor Messages 30 ISH to Audio (ISH2AUDIO_MSG30)—Offset 504h
2398
20.779Outbound Inter-processor Messages 31 ISH to Audio (ISH2AUDIO_MSG31)—Offset 508h
2399
20.780Outbound Inter-processor Messages 32 ISH to Audio (ISH2AUDIO_MSG32)—Offset 50Ch
2399
20.781Inbound Inter-processor Messages 1 Audio to ISH (AUDIO2ISH_MSG1)—Offset 510h....
2399
20.782Inbound Inter-processor Messages 2 Audio to ISH (AUDIO2ISH_MSG2)—Offset 514h....
2400
20.783Inbound Inter-processor Messages 3 Audio to ISH (AUDIO2ISH_MSG3)—Offset 518h....
2400
20.784Inbound Inter-processor Messages 4 Audio to ISH (AUDIO2ISH_MSG4)—Offset 51Ch ...
2401
20.785Inbound Inter-processor Messages 5 Audio to ISH (AUDIO2ISH_MSG5)—Offset 520h....
2401
20.786Inbound Inter-processor Messages 6 Audio to ISH (AUDIO2ISH_MSG6)—Offset 524h....
2402
20.787Inbound Inter-processor Messages 7 Audio to ISH (AUDIO2ISH_MSG7)—Offset 528h....
2402
20.788Inbound Inter-processor Messages 8 Audio to ISH (AUDIO2ISH_MSG8)—Offset 52Ch ...
2402
20.789Inbound Inter-processor Messages 9 Audio to ISH (AUDIO2ISH_MSG9)—Offset 530h....
2403
20.790Inbound Inter-processor Messages 10 Audio to ISH (AUDIO2ISH_MSG10)—Offset 534h
84 Datasheet Volume 2 of 2
2403
20.791Inbound Inter-processor Messages 11 Audio to ISH (AUDIO2ISH_MSG11)—Offset 538h.
2404
20.792Inbound Inter-processor Messages 12 Audio to ISH (AUDIO2ISH_MSG12)—Offset 53Ch
2404
20.793Inbound Inter-processor Messages 13 Audio to ISH (AUDIO2ISH_MSG13)—Offset 540h.
2405
20.794Inbound Inter-processor Messages 14 Audio to ISH (AUDIO2ISH_MSG14)—Offset 544h.
2405
20.795Inbound Inter-processor Messages 15 Audio to ISH (AUDIO2ISH_MSG15)—Offset 548h.
2405
20.796Inbound Inter-processor Messages 16 Audio to ISH (AUDIO2ISH_MSG16)—Offset 54Ch
2406
20.797Inbound Inter-processor Messages 17 Audio to ISH (AUDIO2ISH_MSG17)—Offset 550h.
2406
20.798Inbound Inter-processor Messages 18 Audio to ISH (AUDIO2ISH_MSG18)—Offset 554h.
2407
20.799Inbound Inter-processor Messages 19 Audio to ISH (AUDIO2ISH_MSG19)—Offset 558h.
2407
20.800Inbound Inter-processor Messages 20 Audio to ISH (AUDIO2ISH_MSG20)—Offset 55Ch
2408
20.801Inbound Inter-processor Messages 21 Audio to ISH (AUDIO2ISH_MSG21)—Offset 560h.
2408
20.802Inbound Inter-processor Messages 22 Audio to ISH (AUDIO2ISH_MSG22)—Offset 564h.
2408
20.803Inbound Inter-processor Messages 23 Audio to ISH (AUDIO2ISH_MSG23)—Offset 568h.
2409
20.804Inbound Inter-processor Messages 24 Audio to ISH (AUDIO2ISH_MSG24)—Offset 56Ch
2409
20.805Inbound Inter-processor Messages 25 Audio to ISH (AUDIO2ISH_MSG25)—Offset 570h.
2410
20.806Inbound Inter-processor Messages 26 Audio to ISH (AUDIO2ISH_MSG26)—Offset 574h.
2410
20.807Inbound Inter-processor Messages 27 Audio to ISH (AUDIO2ISH_MSG27)—Offset 578h.
2411
20.808Inbound Inter-processor Messages 28 Audio to ISH (AUDIO2ISH_MSG28)—Offset 57Ch
2411
20.809Inbound Inter-processor Messages 29 Audio to ISH (AUDIO2ISH_MSG29)—Offset 580h.
2411
20.810Inbound Inter-processor Messages 30 Audio to ISH (AUDIO2ISH_MSG30)—Offset 584h.
2412
20.811Inbound Inter-processor Messages 31 Audio to ISH (AUDIO2ISH_MSG31)—Offset 588h.
2412
20.812Inbound Inter-processor Messages 32 Audio to ISH (AUDIO2ISH_MSG32)—Offset 58Ch
2413
20.813Outbound Inter-processor Messages 1 ISH to GFX (ISH2GFX_MSG1)—Offset 590h .2413
20.814Outbound Inter-processor Messages 2 ISH to GFX (ISH2GFX_MSG2)—Offset 594h .2414
20.815Outbound Inter-processor Messages 3 ISH to GFX (ISH2GFX_MSG3)—Offset 598h .2414
20.816Outbound Inter-processor Messages 4 ISH to GFX (ISH2GFX_MSG4)—Offset 59Ch.2414
20.817Outbound Inter-processor Messages 5 ISH to GFX (ISH2GFX_MSG5)—Offset 5A0h .2415
20.818Outbound Inter-processor Messages 6 ISH to GFX (ISH2GFX_MSG6)—Offset 5A4h .2415
20.819Outbound Inter-processor Messages 7 ISH to GFX (ISH2GFX_MSG7)—Offset 5A8h .2416
20.820Outbound Inter-processor Messages 8 ISH to GFX (ISH2GFX_MSG8)—Offset 5ACh.2416
20.821Outbound Inter-processor Messages 9 ISH to GFX (ISH2GFX_MSG9)—Offset 5B0h .2417
20.822Outbound Inter-processor Messages 10 ISH to GFX (ISH2GFX_MSG10)—Offset 5B4h ....
2417
20.823Outbound Inter-processor Messages 11 ISH to GFX (ISH2GFX_MSG11)—Offset 5B8h ....
Datasheet Volume 2 of 2 85
2417
20.824Outbound Inter-processor Messages 12 ISH to GFX (ISH2GFX_MSG12)—Offset 5BCh....
2418
20.825Outbound Inter-processor Messages 13 ISH to GFX (ISH2GFX_MSG13)—Offset 5C0h....
2418
20.826Outbound Inter-processor Messages 14 ISH to GFX (ISH2GFX_MSG14)—Offset 5C4h....
2419
20.827Outbound Inter-processor Messages 15 ISH to GFX (ISH2GFX_MSG15)—Offset 5C8h....
2419
20.828Outbound Inter-processor Messages 16 ISH to GFX (ISH2GFX_MSG16)—Offset 5CCh....
2420
20.829Outbound Inter-processor Messages 17 ISH to GFX (ISH2GFX_MSG17)—Offset 5D0h....
2420
20.830Outbound Inter-processor Messages 18 ISH to GFX (ISH2GFX_MSG18)—Offset 5D4h....
2420
20.831Outbound Inter-processor Messages 19 ISH to GFX (ISH2GFX_MSG19)—Offset 5D8h....
2421
20.832Outbound Inter-processor Messages 20 ISH to GFX (ISH2GFX_MSG20)—Offset 5DCh ...
2421
20.833Outbound Inter-processor Messages 21 ISH to GFX (ISH2GFX_MSG21)—Offset 5E0h ....
2422
20.834Outbound Inter-processor Messages 22 ISH to GFX (ISH2GFX_MSG22)—Offset 5E4h ....
2422
20.835Outbound Inter-processor Messages 23 ISH to GFX (ISH2GFX_MSG23)—Offset 5E8h ....
2423
20.836Outbound Inter-processor Messages 24 ISH to GFX (ISH2GFX_MSG24)—Offset 5ECh....
2423
20.837Outbound Inter-processor Messages 25 ISH to GFX (ISH2GFX_MSG25)—Offset 5F0h ....
2423
20.838Outbound Inter-processor Messages 26 ISH to GFX (ISH2GFX_MSG26)—Offset 5F4h ....
2424
20.839Outbound Inter-processor Messages 27 ISH to GFX (ISH2GFX_MSG27)—Offset 5F8h ....
2424
20.840Outbound Inter-processor Messages 28 ISH to GFX (ISH2GFX_MSG28)—Offset 5FCh ....
2425
20.841Outbound Inter-processor Messages 29 ISH to GFX (ISH2GFX_MSG29)—Offset 600h ....
2425
20.842Outbound Inter-processor Messages 30 ISH to GFX (ISH2GFX_MSG30)—Offset 604h ....
2426
20.843Outbound Inter-processor Messages 31 ISH to GFX (ISH2GFX_MSG31)—Offset 608h ....
2426
20.844Outbound Inter-processor Messages 32 ISH to GFX (ISH2GFX_MSG32)—Offset 60Ch....
2426
20.845Inbound Inter-processor Messages 1 GFX to ISH (GFX2ISH_MSG1)—Offset 610h .. 2427
20.846Inbound Inter-processor Messages 2 GFX to ISH (GFX2ISH_MSG2)—Offset 614h .. 2427
20.847Inbound Inter-processor Messages 3 GFX to ISH (GFX2ISH_MSG3)—Offset 618h .. 2428
20.848Inbound Inter-processor Messages 4 GFX to ISH (GFX2ISH_MSG4)—Offset 61Ch .. 2428
20.849Inbound Inter-processor Messages 5 GFX to ISH (GFX2ISH_MSG5)—Offset 620h .. 2429
20.850Inbound Inter-processor Messages 6 GFX to ISH (GFX2ISH_MSG6)—Offset 624h .. 2429
20.851Inbound Inter-processor Messages 7 GFX to ISH (GFX2ISH_MSG7)—Offset 628h .. 2429
20.852Inbound Inter-processor Messages 8 GFX to ISH (GFX2ISH_MSG8)—Offset 62Ch .. 2430
20.853Inbound Inter-processor Messages 9 GFX to ISH (GFX2ISH_MSG9)—Offset 630h .. 2430
20.854Inbound Inter-processor Messages 10 GFX to ISH (GFX2ISH_MSG10)—Offset 634h2431
20.855Inbound Inter-processor Messages 11 GFX to ISH (GFX2ISH_MSG11)—Offset 638h2431
20.856Inbound Inter-processor Messages 12 GFX to ISH (GFX2ISH_MSG12)—Offset 63Ch ......
2432
20.857Inbound Inter-processor Messages 13 GFX to ISH (GFX2ISH_MSG13)—Offset 640h2432
86 Datasheet Volume 2 of 2
Datasheet Volume 2 of 2 87
21.15 Maximum Latency (HECI1_MLAT) — Offset 3Fh ................................................. 2453
21.16 Host Firmware Status (HECI1_HFS) — Offset 40h .............................................. 2454
21.17 Miscellaneous Shadow (HECI1_MISC_SHDW) — Offset 44h ................................. 2454
21.18 General Status Shadow 1 (HECI1_GS_SHDW1) — Offset 48h .............................. 2454
21.19 Host General Status (HECI1_H_GS1) — Offset 4Ch ............................................ 2455
21.20 PCI Power Management Capability ID (HECI1_PID) — Offset 50h ......................... 2455
21.21 PCI Power Management Capabilities (HECI1_PC) — Offset 52h............................. 2455
21.22 PCI Power Management Control And Status (HECI1_PMCS) — Offset 54h .............. 2456
21.23 General Status Shadow 2 (HECI1_GS_SHDW2) — Offset 60h .............................. 2457
21.24 General Status Shadow 3 (HECI1_GS_SHDW3) — Offset 64h .............................. 2457
21.25 General Status Shadow 4 (HECI1_GS_SHDW4) — Offset 68h .............................. 2457
21.26 General Status Shadow 5 (HECI1_GS_SHDW5) — Offset 6Ch .............................. 2457
21.27 Host General Status 2 (HECI1_H_GS2) — Offset 70h.......................................... 2458
21.28 Host General Status 3 (HECI1_H_GS3) — Offset 74h.......................................... 2458
21.29 Message Signaled Interrupt Identifiers (HECI1_MID) — Offset 8Ch ....................... 2458
21.30 Message Signaled Interrupt Message Control (HECI1_MC) — Offset 8Eh ................ 2459
21.31 Message Signaled Interrupt Message Address (HECI1_MA) — Offset 90h ............... 2459
21.32 Message Signaled Interrupt Upper Address (HECI1_MUA) — Offset 94h ................ 2459
21.33 Message Signaled Interrupt Message Data (HECI1_MD) — Offset 98h ................... 2460
21.34 HECI Interrupt Delivery Mode (HECI1_HIDM) — Offset A0h ................................. 2460
21.35 Vendor Specific Capability Register (HECI1_VSCR) — Offset A4h .......................... 2460
21.36 Vendor Specific Extended Capability Register (HECI1_VSEC) — Offset A8h ............ 2461
21.37 SW LTR Pointer Register (HECI1_SWLTRPTR) — Offset ACh ................................. 2461
21.38 Device Idle Pointer Register (HECI1_DEVIDLEPTR) — Offset B0h.......................... 2462
21.39 Device Idle Power On Latency (HECI1_DEVIDLEPOL) — Offset B4h....................... 2462
21.40 DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN) — Offset B6h ......... 2462
21.41 Host Extend Register Status (HECI1_HERS) — Offset BCh ................................... 2463
21.42 Host Extend Register DW1 (HECI1_HER1) — Offset C0h...................................... 2463
21.43 Host Extend Register DW2 (HECI1_HER2) — Offset C4h...................................... 2464
21.44 Host Extend Register DW3 (HECI1_HER3) — Offset C8h...................................... 2464
21.45 Host Extend Register DW4 (HECI1_HER4) — Offset CCh ..................................... 2464
21.46 Host Extend Register DW5 (HECI1_HER5) — Offset D0h ..................................... 2464
21.47 Host Extend Register DW6 (HECI1_HER6) — Offset D4h ..................................... 2465
21.48 Host Extend Register DW7 (HECI1_HER7) — Offset D8h ..................................... 2465
21.49 Host Extend Register DW8 (HECI1_HER8) — Offset DCh ..................................... 2465
21.50 Manufacturer's ID (HECI1_MANID) — Offset F8h................................................ 2465
22 HECI1 Registers ...................................................................................................2467
22.1 Identifiers (HECI1_ID) — Offset 0h .................................................................. 2467
22.2 Command (HECI1_CMD) — Offset 4h ............................................................... 2467
22.3 Status (HECI1_STS) — Offset 6h ..................................................................... 2468
22.4 Revision ID And Class Code (HECI1_RID_CC) — Offset 8h................................... 2469
22.5 Cache Line Size (HECI1_CLS) — Offset Ch ........................................................ 2469
22.6 Master Latency Timer (HECI1_MLT) — Offset Dh ................................................ 2469
22.7 Header Type (HECI1_HTYPE) — Offset Eh ......................................................... 2469
22.8 Built In Self-Test (HECI1_BIST) — Offset Fh...................................................... 2470
22.9 HECI MMIO Base Address Low (HECI1_MMIO_MBAR_LO) — Offset 10h ................. 2470
22.10 HECI MMIO Base Address High (HECI1_MMIO_MBAR_HI) — Offset 14h................. 2471
22.11 BAR1 — Offset 18h ........................................................................................ 2471
22.12 BAR1_HIGH — Offset 1Ch ............................................................................... 2471
22.13 Sub System Identifiers (HECI1_SS) — Offset 2Ch .............................................. 2471
22.14 EXPANSION_ROM_BASEADDR — Offset 30h ...................................................... 2472
22.15 Capabilities Pointer (HECI1_CAP) — Offset 34h .................................................. 2472
22.16 Interrupt Information (HECI1_INTR) — Offset 3Ch ............................................. 2472
22.17 Minimum Grant (HECI1_MGNT) — Offset 3Eh .................................................... 2473
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Datasheet Volume 2 of 2 89
23.14 Minimum Grant (HECI2_MGNT) — Offset 3Eh .................................................... 2493
23.15 Maximum Latency (HECI2_MLAT) — Offset 3Fh ................................................. 2493
23.16 Host Firmware Status (HECI2_HFS) — Offset 40h .............................................. 2493
23.17 General Status Shadow 1 (HECI2_GS_SHDW1) — Offset 48h .............................. 2494
23.18 Host General Status (HECI2_H_GS1) — Offset 4Ch ............................................ 2494
23.19 PCI Power Management Capability ID (HECI2_PID) — Offset 50h ......................... 2494
23.20 PCI Power Management Capabilities (HECI2_PC) — Offset 52h............................. 2494
23.21 PCI Power Management Control And Status (HECI2_PMCS) — Offset 54h .............. 2495
23.22 General Status Shadow 2 (HECI2_GS_SHDW2) — Offset 60h .............................. 2496
23.23 General Status Shadow 3 (HECI2_GS_SHDW3) — Offset 64h .............................. 2496
23.24 General Status Shadow 4 (HECI2_GS_SHDW4) — Offset 68h .............................. 2496
23.25 General Status Shadow 5 (HECI2_GS_SHDW5) — Offset 6Ch .............................. 2497
23.26 Host General Status 2 (HECI2_H_GS2) — Offset 70h.......................................... 2497
23.27 Host General Status 3 (HECI2_H_GS3) — Offset 74h.......................................... 2497
23.28 Message Signaled Interrupt Identifiers (HECI2_MID) — Offset 8Ch ....................... 2497
23.29 Message Signaled Interrupt Message Control (HECI2_MC) — Offset 8Eh ................ 2498
23.30 Message Signaled Interrupt Message Address (HECI2_MA) — Offset 90h ............... 2498
23.31 Message Signaled Interrupt Upper Address (HECI2_MUA) — Offset 94h ................ 2499
23.32 Message Signaled Interrupt Message Data (HECI2_MD) — Offset 98h ................... 2499
23.33 HECI Interrupt Delivery Mode (HECI2_HIDM) — Offset A0h ................................. 2499
23.34 Vendor Specific Capability Register (HECI2_VSCR) — Offset A4h .......................... 2500
23.35 Vendor Specific Extended Capability Register (HECI2_VSEC) — Offset A8h ............ 2500
23.36 SW LTR Pointer Register (HECI2_SWLTRPTR) — Offset ACh ................................. 2500
23.37 Device Idle Pointer Register (HECI2_DEVIDLEPTR) — Offset B0h.......................... 2501
23.38 Device Idle Power On Latency (HECI2_DEVIDLEPOL) — Offset B4h....................... 2501
23.39 DevIdle Power Control Enabled Register (HECI2_PWRCTRLEN) — Offset B6h ......... 2502
23.40 Manufacturer's ID (HECI2_MANID) — Offset F8h................................................ 2502
24 HECI3 Registers ...................................................................................................2504
24.1 Identifiers (HECI3_ID) — Offset 0h .................................................................. 2504
24.2 Command (HECI3_CMD) — Offset 4h ............................................................... 2504
24.3 Status (HECI3_STS) — Offset 6h ..................................................................... 2505
24.4 Revision ID And Class Code (HECI3_RID_CC) — Offset 8h................................... 2506
24.5 Cache Line Size (HECI3_CLS) — Offset Ch ........................................................ 2506
24.6 Master Latency Timer (HECI3_MLT) — Offset Dh ................................................ 2506
24.7 Header Type (HECI3_HTYPE) — Offset Eh ......................................................... 2506
24.8 Built In Self-Test (HECI3_BIST) — Offset Fh...................................................... 2507
24.9 HECI MMIO Base Address Low (HECI3_MMIO_MBAR_LO) — Offset 10h ................. 2507
24.10 HECI MMIO Base Address High (HECI3_MMIO_MBAR_HI) — Offset 14h................. 2508
24.11 Sub System Identifiers (HECI3_SS) — Offset 2Ch .............................................. 2508
24.12 Capabilities Pointer (HECI3_CAP) — Offset 34h .................................................. 2508
24.13 Interrupt Information (HECI3_INTR) — Offset 3Ch ............................................. 2508
24.14 Minimum Grant (HECI3_MGNT) — Offset 3Eh .................................................... 2509
24.15 Maximum Latency (HECI3_MLAT) — Offset 3Fh ................................................. 2509
24.16 Host Firmware Status (HECI3_HFS) — Offset 40h .............................................. 2509
24.17 General Status Shadow 1 (HECI3_GS_SHDW1) — Offset 48h .............................. 2510
24.18 Host General Status (HECI3_H_GS1) — Offset 4Ch ............................................ 2510
24.19 PCI Power Management Capability ID (HECI3_PID) — Offset 50h ......................... 2510
24.20 PCI Power Management Capabilities (HECI3_PC) — Offset 52h............................. 2510
24.21 PCI Power Management Control And Status (HECI3_PMCS) — Offset 54h .............. 2511
24.22 General Status Shadow 2 (HECI3_GS_SHDW2) — Offset 60h .............................. 2512
24.23 General Status Shadow 3 (HECI3_GS_SHDW3) — Offset 64h .............................. 2512
24.24 General Status Shadow 4 (HECI3_GS_SHDW4) — Offset 68h .............................. 2512
24.25 General Status Shadow 5 (HECI3_GS_SHDW5) — Offset 6Ch .............................. 2513
24.26 Host General Status 2 (HECI3_H_GS2) — Offset 70h.......................................... 2513
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25.40 Immediate Command Status (ICS)—Offset 68h ................................................. 2544
25.41 DMA Position Lower Base Address (DPLBASE)—Offset 70h................................... 2545
25.42 DMA Position Upper Base Address (DPUBASE)—Offset 74h .................................. 2545
25.43 (ISD0CTL_ISD0STS)—Offset 80h .................................................................... 2545
25.44 Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)—Offset 84h ... 2548
25.45 Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)—Offset 88h ...... 2549
25.46 (ISD0LVI_ISD0FIFOW)—Offset 8Ch................................................................. 2549
26 SRAM Registers ....................................................................................................2550
26.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID) — Offset 0h . 2550
26.2 STATUSCOMMAND — Offset 4h........................................................................ 2550
26.3 REVCLASSCODE — Offset 8h ........................................................................... 2551
26.4 CLLATHEADERBIST — Offset Ch....................................................................... 2551
26.5 BAR — Offset 10h .......................................................................................... 2552
26.6 BAR -Base Address Register High (BAR_HIGH) — Offset 14h ............................... 2552
26.7 BAR1 — Offset 18h ........................................................................................ 2553
26.8 BAR1 -Base Address Register1 High (BAR1_HIGH) — Offset 1Ch .......................... 2553
26.9 BAR2 — Offset 20h ........................................................................................ 2554
26.10 SUBSYSTEMID — Offset 2Ch ........................................................................... 2554
26.11 EXPANSION ROM base address (EXPANSION_ROM_BASEADDR) — Offset 30h ....... 2554
26.12 CAPABILITYPTR — Offset 34h .......................................................................... 2555
26.13 INTERRUPTREG — Offset 3Ch .......................................................................... 2555
26.14 POWERCAPID — Offset 80h............................................................................. 2555
26.15 PMECTRLSTATUS — Offset 84h ........................................................................ 2556
26.16 PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD) — Offset 90h. 2556
26.17 DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) — Offset 94h ......... 2557
26.18 D0I3_CONTROL_SW_LTR_MMIO_REG — Offset 98h ........................................... 2557
26.19 DEVICE_IDLE_POINTER_REG — Offset 9Ch ....................................................... 2558
26.20 D0I3_MAX_POW_LAT_PG_CONFIG — Offset A0h ............................................... 2558
26.21 GEN_REGRW1 - General Purpose Read Write Register1 (GEN_REGRW1) — Offset B0h ...
2559
26.22 GEN_REGRW2 — Offset B4h............................................................................ 2559
26.23 GEN_REGRW3 — Offset B8h............................................................................ 2559
26.24 GEN_REGRW4 — Offset BCh............................................................................ 2560
26.25 GEN_INPUT_REG — Offset C0h........................................................................ 2560
26.26 Manufacturers ID (MANID) — Offset F8h ........................................................... 2560
27 SPI Controller Registers .......................................................................................2562
27.1 Device ID and Vendor ID (BIOS_SPI_DID_VID) — Offset 0h ................................ 2562
27.2 Status and Command (BIOS_SPI_STS_CMD) — Offset 4h ................................... 2562
27.3 Revision ID and Class Code (BIOS_SPI_CC_RID) — Offset 8h .............................. 2563
27.4 BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS) —
Offset Ch ...................................................................................................... 2564
27.5 SPI BAR0 MMIO (BIOS_SPI_BAR0) — Offset 10h ............................................... 2564
27.6 CSXE BAR1 Direct Reads (CSXE_SPI_BAR1) — Offset 14h ................................... 2565
27.7 CSXE BAR2 Huffman Decompression (CSXE_SPI_BAR2) — Offset 18h................... 2565
27.8 CSXE BAR3 Touch BAR (CSXE_SPI_BAR3) — Offset 1Ch ..................................... 2566
27.9 CSXE BAR4 BIOS Direct Reads (CSXE_SPI_BAR4) — Offset 20h ........................... 2566
27.10 Cardbus CIS Pointer (CSXE_SPI_CCP) — Offset 28h ........................................... 2567
27.11 Subsystem and Vendor ID (BIOS_SPI_SID_SVID) — Offset 2Ch........................... 2567
27.12 Expansion ROM Base Address (CSXE_SPI_XRBAR) — Offset 30h .......................... 2567
27.13 Capabilities List Pointer (CSXE_SPI_CAPP) — Offset 34h ..................................... 2568
27.14 Maximum Latency, Minimum Grant, Interrupt Pin and Interrupt Line (CSXE_SPI_MAX-
L_MING_INTP_INTL) — Offset 3Ch ................................................................... 2568
27.15 CSXE Capabilities List Pointer (CSXE_SPI_CCAPP) — Offset 40h ........................... 2568
27.16 MSI Message Control, Next Pointer and Capability ID (CSXE_SPI_MSIMC_MSINP_MSICID)
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27.69 Flash Region 2 (CSXE_FREG2)—Offset 5Ch ....................................................... 2596
27.70 Flash Region 3 (CSXE_FREG3)—Offset 60h........................................................ 2596
27.71 Flash Region 4 (CSXE_FREG4)—Offset 64h........................................................ 2597
27.72 Flash Region 5 (CSXE_FREG5)—Offset 68h........................................................ 2597
27.73 Flash Region 6 (CSXE_FREG6)—Offset 6Ch ....................................................... 2598
27.74 Flash Region 7 (CSXE_FREG7)—Offset 70h........................................................ 2598
27.75 Flash Region 8 (CSXE_FREG8)—Offset 74h........................................................ 2599
27.76 Flash Region 9 (CSXE_FREG9)—Offset 78h........................................................ 2599
27.77 Flash Region 10 (CSXE_FREG10)—Offset 7Ch .................................................... 2600
27.78 Flash Region 11 (CSXE_FREG11)—Offset 80h .................................................... 2600
27.79 Flash Protected Range 0 (CSXE_FPR0)—Offset 84h............................................. 2601
27.80 Flash Protected Range 1 (CSXE_FPR1)—Offset 88h............................................. 2601
27.81 Flash Protected Range 2 (CSXE_FPR2)—Offset 8Ch ............................................ 2602
27.82 Flash Protected Range 3 (CSXE_FPR3)—Offset 90h............................................. 2603
27.83 Flash Protected Range 4 (CSXE_FPR4)—Offset 94h............................................. 2603
27.84 Write Protected Range 0 (CSXE_WPR0)—Offset 98h ........................................... 2604
27.85 Software Sequencing Flash Status and Control (CSXE_SSFSTS_CTL)—Offset A0h ... 2605
27.86 Prefix Opcode and Opcode Type Configuration (CSXE_PREOP_OPTYPE)—Offset A4h 2608
27.87 Opcode Menu0 Configuration (CSXE_OPMENU0)—Offset A8h ............................... 2609
27.88 Opcode Menu1 Configuration (CSXE_OPMENU1)—Offset ACh ............................... 2610
27.89 Vendor Specific Component Capabilities for Component 0 (CSXE_SFDP0_VSCC0)—Offset
C4h ............................................................................................................. 2610
27.90 Vendor Specific Component Capabilities for Component 1 (CSXE_SFDP1_VSCC1)—Offset
C8h ............................................................................................................. 2611
27.91 Parameter Table Index (CSXE_PTINX)—Offset CCh............................................. 2612
27.92 Parameter Table Data (CSXE_PTDATA)—Offset D0h ........................................... 2613
27.93 SPI Bus Requester Status (CSXE_SBRS)—Offset D4h.......................................... 2613
27.94 Huffman Decompression Compressed Page Offset (CSXE_HDCOMPOFF)—Offset D8h .....
2614
27.95 Touch Controller Configuration Register (CSXE_TCCR)—Offset DCh ...................... 2615
27.96 Flash Region 12 (CSXE_FREG12)—Offset E0h .................................................... 2615
27.97 Flash Region 13 (CSXE_FREG13)—Offset E4h .................................................... 2616
27.98 Flash Region 14 (CSXE_FREG14)—Offset E8h .................................................... 2616
27.99 Flash Region 15 (CSXE_FREG15)—Offset ECh .................................................... 2617
27.100Interrupt Cause Enable (CSXE_ICE)—Offset F0h................................................ 2617
27.101Interrupt Cause Status (CSXE_ICS)—Offset F4h ................................................ 2618
27.102Device 0 Write/Erase Count (CSXE_D0WEC)—Offset FCh .................................... 2619
27.103Device 1 Write/Erase Count (CSXE_D1WEC)—Offset 100h .................................. 2619
27.104Write/Erase Count Threshold (CSXE_WECTHR)—Offset 104h............................... 2620
27.105RPMC SFDP Table (CSXE_RPMC0_D0)—Offset 108h ........................................... 2620
27.106RPMC SFDP Table (CSXE_RPMC1_D0)—Offset 10Ch ........................................... 2621
27.107RPMC SFDP Table (CSXE_RPMC0_D1)—Offset 110h ........................................... 2621
27.108RPMC SFDP Table (CSXE_RPMC1_D1)—Offset 114h ........................................... 2622
27.109CSME Master Read Access Permissions (CSXE_CM_RAP)—Offset 118h.................. 2622
27.110CSME Master Write Access Permissions (CSXE_CM_WAP)—Offset 11Ch ................ 2622
27.111Host Flash Protected Range 0 (CSXE_HOST_PR0)—Offset 184h ........................... 2623
27.112Host Flash Protected Range 1 (CSXE_HOST_PR1)—Offset 188h ........................... 2623
27.113Host Flash Protected Range 2 (CSXE_HOST_PR2)—Offset 18Ch ........................... 2624
27.114Host Flash Protected Range 3 (CSXE_HOST_PR3)—Offset 190h ........................... 2624
27.115Host Flash Protected Range 4 (CSXE_HOST_PR4)—Offset 194h ........................... 2625
27.116Host Global Protected Range 0 (CSXE_HOST_GPR0)—Offset 198h ....................... 2625
27.117IE Flash Protected Range 0 (CSXE_IE_PR0)—Offset 1B0h ................................... 2626
27.118IE Flash Protected Range 1 (CSXE_IE_PR1)—Offset 1B4h ................................... 2626
27.119IE Flash Protected Range 2 (CSXE_IE_PR2)—Offset 1B8h ................................... 2627
27.120IE Flash Protected Range 3 (CSXE_IE_PR3)—Offset 1BCh ................................... 2627
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27.174Flash Region 12 (BIOS_FREG12)—Offset E0h .................................................... 2662
27.175Flash Region 13 (BIOS_FREG13)—Offset E4h .................................................... 2663
27.176Flash Region 14 (BIOS_FREG14)—Offset E8h .................................................... 2663
27.177Flash Region 15 (BIOS_FREG15)—Offset ECh.................................................... 2664
27.178RPMC SFDP Table (BIOS_RPMC0_D0)—Offset 108h ........................................... 2664
27.179RPMC SFDP Table (BIOS_RPMC1_D0)—Offset 10Ch ........................................... 2664
27.180RPMC SFDP Table (BIOS_RPMC0_D1)—Offset 110h ........................................... 2665
27.181RPMC SFDP Table (BIOS_RPMC1_D1)—Offset 114h ........................................... 2665
27.182BIOS Master Read Access Permissions (BIOS_BM_RAP)—Offset 118h ................... 2665
27.183BIOS Master Write Access Permissions (BIOS_BM_WAP)—Offset 11Ch ................. 2666
27.184CSXE Flash Protected Range 0 (BIOS_CSXE_PR0)—Offset 184h........................... 2666
27.185CSXE Flash Protected Range 1 (BIOS_CSXE_PR1)—Offset 188h........................... 2667
27.186CSXE Flash Protected Range 2 (BIOS_CSXE_PR2)—Offset 18Ch .......................... 2667
27.187CSXE Flash Protected Range 3 (BIOS_CSXE_PR3)—Offset 190h........................... 2668
27.188CSXE Flash Protected Range 4 (BIOS_CSXE_PR4)—Offset 194h........................... 2668
27.189Write Protected Range 0 (BIOS_CSXE_WPR0)—Offset 198h ................................ 2669
27.190IE Flash Protected Range 0 (BIOS_IE_PR0)—Offset 1B0h ................................... 2670
27.191IE Flash Protected Range 1 (BIOS_IE_PR1)—Offset 1B4h ................................... 2670
27.192IE Flash Protected Range 2 (BIOS_IE_PR2)—Offset 1B8h ................................... 2671
27.193IE Flash Protected Range 3 (BIOS_IE_PR3)—Offset 1BCh ................................... 2671
27.194IE Flash Protected Range 4 (BIOS_IE_PR4)—Offset 1C0h ................................... 2672
27.195eSPI Controller HW Status 1 (ESPI_HW_STS_2)—Offset 18h............................... 2672
27.196 (EC_FLASH_WR_DATA_0)—Offset 1A0h .......................................................... 2673
27.197 (EC_FLASH_WR_DATA_1)—Offset 1A4h .......................................................... 2673
27.198 (EC_FLASH_WR_DATA_2)—Offset 1A8h .......................................................... 2674
27.199 (EC_FLASH_WR_DATA_3)—Offset 1ACh .......................................................... 2674
27.200 (EC_FLASH_WR_DATA_4)—Offset 1B0h .......................................................... 2674
27.201 (EC_FLASH_WR_DATA_5)—Offset 1B4h .......................................................... 2675
27.202 (EC_FLASH_WR_DATA_6)—Offset 1B8h .......................................................... 2675
27.203 (EC_FLASH_WR_DATA_7)—Offset 1BCh .......................................................... 2675
27.204 (EC_FLASH_WR_DATA_8)—Offset 1C0h .......................................................... 2675
27.205 (EC_FLASH_WR_DATA_9)—Offset 1C4h .......................................................... 2676
27.206 (EC_FLASH_WR_DATA_10)—Offset 1C8h ........................................................ 2676
27.207 (EC_FLASH_WR_DATA_11)—Offset 1CCh ........................................................ 2676
27.208 (EC_FLASH_WR_DATA_12)—Offset 1D0h ........................................................ 2676
27.209 (EC_FLASH_WR_DATA_13)—Offset 1D4h ........................................................ 2677
27.210 (EC_FLASH_WR_DATA_14)—Offset 1D8h ........................................................ 2677
27.211 (EC_FLASH_WR_DATA_15)—Offset 1DCh ........................................................ 2677
27.212 (EC_FLASH_REQ_ADDR)—Offset 1E0h ............................................................ 2678
27.213 (EC_FLASH_CPL_CTL)—Offset 1E4h................................................................ 2678
27.214(EC_FLASH_CPL_STS)—Offset 1E8h ................................................................ 2678
27.215 (EC_FLASH_RD_DATA_0)—Offset 200h ........................................................... 2679
27.216 (EC_FLASH_RD_DATA_1)—Offset 204h ........................................................... 2679
27.217 (EC_FLASH_RD_DATA_2)—Offset 208h ........................................................... 2679
27.218 (EC_FLASH_RD_DATA_3)—Offset 20Ch........................................................... 2680
27.219 (EC_FLASH_RD_DATA_4)—Offset 210h ........................................................... 2680
27.220 (EC_FLASH_RD_DATA_5)—Offset 214h ........................................................... 2680
27.221 (EC_FLASH_RD_DATA_6)—Offset 218h ........................................................... 2680
27.222 (EC_FLASH_RD_DATA_7)—Offset 21Ch........................................................... 2681
27.223 (EC_FLASH_RD_DATA_8)—Offset 220h ........................................................... 2681
27.224 (EC_FLASH_RD_DATA_9)—Offset 224h ........................................................... 2681
27.225 (EC_FLASH_RD_DATA_10)—Offset 228h ......................................................... 2681
27.226 (EC_FLASH_RD_DATA_11)—Offset 22Ch ......................................................... 2682
27.227 (EC_FLASH_RD_DATA_12)—Offset 230h ......................................................... 2682
27.228 (EC_FLASH_RD_DATA_13)—Offset 234h ......................................................... 2682
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27.280(CSXE_ESPI_OOB_SMBUS_RX_DATA_13)—Offset 184h ..................................... 2709
27.281(CSXE_ESPI_OOB_SMBUS_RX_DATA_14)—Offset 188h ..................................... 2709
27.282(CSXE_ESPI_OOB_SMBUS_RX_DATA_15)—Offset 18Ch ..................................... 2709
27.283(CSXE_ESPI_OOB_SMBUS_RX_DATA_16)—Offset 190h ..................................... 2709
27.284(CSXE_ESPI_OOB_SMBUS_RX_DATA_17)—Offset 194h ..................................... 2710
27.285(CSXE_ESPI_OOB_SMBUS_RX_DATA_18)—Offset 198h ..................................... 2710
28 CNVi Registers......................................................................................................2711
28.1 CNVI_WIFI_VEN_DEV_ID — Offset 0h .............................................................. 2711
28.2 CNVI_WIFI_PCI_COM_STAT — Offset 4h........................................................... 2711
28.3 CNVI_WIFI_PCI_CLASS_CODE — Offset 8h ....................................................... 2712
28.4 CNVI_WIFI_PCI_BUS_COM — Offset Ch............................................................ 2713
28.5 CNVI_WIFI_BAR0 — Offset 10h ....................................................................... 2713
28.6 CNVI_WIFI_BAR1 — Offset 14h ....................................................................... 2714
28.7 CNVI_WIFI_BAR2 — Offset 18h ....................................................................... 2714
28.8 CNVI_WIFI_BAR3 — Offset 1Ch ....................................................................... 2714
28.9 CNVI_WIFI_BAR4 — Offset 20h ....................................................................... 2715
28.10 CNVI_WIFI_BAR5 — Offset 24h ....................................................................... 2715
28.11 CNVI_WIFI_CIS_PTR — Offset 28h................................................................... 2715
28.12 CNVI_WIFI_SUBSYS_ID — Offset 2Ch .............................................................. 2716
28.13 CNVI_WIFI_ROM_BAR — Offset 30h................................................................. 2716
28.14 CNVI_WIFI_CAP_PTR — Offset 34h .................................................................. 2716
28.15 CNVI_WIFI_RES_ADDRESS — Offset 38h.......................................................... 2717
28.16 CNVI_WIFI_INTERRUPT — Offset 3Ch............................................................... 2717
28.17 CNVI_WIFI_GIO_CAP — Offset 40h .................................................................. 2717
28.18 CNVI_WIFI_GIO_DEV_CAP — Offset 44h .......................................................... 2718
28.19 CNVI_WIFI_GIO_DEV — Offset 48h.................................................................. 2719
28.20 CNVI_WIFI_GIO_LNK_CAP — Offset 4Ch .......................................................... 2720
28.21 CNVI_WIFI_GIO_LINK — Offset 50h................................................................. 2720
28.22 CNVI_WIFI_GIO_DEV_CAP_2 — Offset 64h ....................................................... 2720
28.23 CNVI_WIFI_GIO_DEV_2 — Offset 68h .............................................................. 2721
28.24 CNVI_WIFI_GIO_LINK_2 — Offset 70h ............................................................. 2722
28.25 CNVI_WIFI_MSIX_CAP_HEAD — Offset 80h....................................................... 2722
28.26 CNVI_WIFI_MSIX_TABLE_OFFSET — Offset 84h ................................................ 2722
28.27 CNVI_WIFI_MSIX_PBA_OFFSET — Offset 88h.................................................... 2723
28.28 CNVI_WIFI_PMC — Offset C8h ........................................................................ 2723
28.29 CNVI_WIFI_PMCSR — Offset CCh..................................................................... 2724
28.30 CNVI_WIFI_MSI_MSG_CTRL — Offset D0h ........................................................ 2725
28.31 CNVI_WIFI_MSI_LOW_ADD — Offset D4h ......................................................... 2725
28.32 CNVI_WIFI_MSI_HIGH_ADD — Offset D8h ........................................................ 2725
28.33 CNVI_WIFI_MSI_DATA — Offset DCh ............................................................... 2726
28.34 CNVI_WIFI_GIO_SERIAL_CAP — Offset 100h .................................................... 2726
28.35 CNVI_WIFI_GIO_SERIAL_LOW — Offset 104h ................................................... 2726
28.36 CNVI_WIFI_GIO_SERIAL_UP — Offset 108h ...................................................... 2727
28.37 CNVI_WIFI_UNCORRECT_ERR_SEV — Offset 10Ch............................................. 2727
28.38 CNVI_WIFI_CORRECT_ERR_STAT — Offset 110h ............................................... 2728
28.39 CNVI_WIFI_CORRECT_ERR_MASK — Offset 114h............................................... 2729
28.40 CNVI_WIFI_ADVANCED_ERR_CAP — Offset 118h............................................... 2730
28.41 CNVI_WIFI_HEADER_LOG1 — Offset 11Ch ........................................................ 2730
28.42 CNVI_WIFI_HEADER_LOG2 — Offset 120h ........................................................ 2731
28.43 CNVI_WIFI_HEADER_LOG3 — Offset 124h ........................................................ 2731
28.44 CNVI_WIFI_HEADER_LOG4 — Offset 128h ........................................................ 2731
28.45 CNVI_WIFI_LTR_EXTND_CAP_HEAD — Offset 14Ch ........................................... 2731
28.46 CNVI_WIFI_LTR_MAX_SNOOP_NOSNOOP_LAT — Offset 150h ............................. 2732
28.47 CNVI_WIFI_L1PM_SUB_EXTND_CAP_HEAD — Offset 154h .................................. 2732
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29.45 Host Software Pad Ownership (HOSTSW_OWN_audio_0)—Offset B0h ................... 2801
29.46 Reserved (RSVD4[0])—Offset B4h ................................................................... 2807
29.47 Reserved (RSVD4[1])—Offset B8h ................................................................... 2807
29.48 Reserved (RSVD4[2])—Offset BCh ................................................................... 2807
29.49 Reserved (RSVD4[3])—Offset C0h ................................................................... 2808
29.50 Reserved (RSVD4[4])—Offset C4h ................................................................... 2808
29.51 Reserved (RSVD4[5])—Offset C8h ................................................................... 2808
29.52 Reserved (RSVD4[6])—Offset CCh ................................................................... 2809
29.53 Reserved (RSVD4[7])—Offset D0h ................................................................... 2809
29.54 Reserved (RSVD4[8])—Offset D4h ................................................................... 2809
29.55 Reserved (RSVD4[9])—Offset D8h ................................................................... 2809
29.56 Reserved (RSVD4[10])—Offset DCh ................................................................. 2810
29.57 Reserved (RSVD4[11])—Offset E0h .................................................................. 2810
29.58 Reserved (RSVD4[12])—Offset E4h .................................................................. 2810
29.59 Reserved (RSVD4[13])—Offset E8h .................................................................. 2810
29.60 Reserved (RSVD4[14])—Offset ECh.................................................................. 2811
29.61 Reserved (RSVD4[15])—Offset F0h .................................................................. 2811
29.62 Reserved (RSVD4[16])—Offset F4h .................................................................. 2811
29.63 Reserved (RSVD4[17])—Offset F8h .................................................................. 2812
29.64 Reserved (RSVD4[18])—Offset FCh .................................................................. 2812
29.65 GPI Interrupt Status (GPI_IS_audio_0)—Offset 100h.......................................... 2812
29.66 Reserved (RSVD5[0])—Offset 104h .................................................................. 2819
29.67 Reserved (RSVD5[1])—Offset 108h .................................................................. 2820
29.68 Reserved (RSVD5[2])—Offset 10Ch.................................................................. 2820
29.69 GPI Interrupt Enable (GPI_IE_audio_0)—Offset 110h ......................................... 2820
29.70 Reserved (RSVD6[0])—Offset 114h .................................................................. 2825
29.71 Reserved (RSVD6[1])—Offset 118h .................................................................. 2825
29.72 Reserved (RSVD6[2])—Offset 11Ch.................................................................. 2826
29.73 Reserved (RSVD6[3])—Offset 120h .................................................................. 2826
29.74 Reserved (RSVD6[4])—Offset 124h .................................................................. 2826
29.75 Reserved (RSVD6[5])—Offset 128h .................................................................. 2826
29.76 Reserved (RSVD6[6])—Offset 12Ch.................................................................. 2827
29.77 GPI General Purpose Events Status (GPI_GPE_STS_audio_0)—Offset 130h............ 2827
29.78 Reserved (RSVD7[0])—Offset 134h .................................................................. 2834
29.79 Reserved (RSVD7[1])—Offset 138h .................................................................. 2835
29.80 Reserved (RSVD7[2])—Offset 13Ch.................................................................. 2835
29.81 Reserved (RSVD7[3])—Offset 140h .................................................................. 2835
29.82 Reserved (RSVD7[4])—Offset 144h .................................................................. 2835
29.83 Reserved (RSVD7[5])—Offset 148h .................................................................. 2836
29.84 Reserved (RSVD7[6])—Offset 14Ch.................................................................. 2836
29.85 GPI General Purpose Events Enable (GPI_GPE_EN_audio_0)—Offset 150h ............. 2836
29.86 Reserved (RSVD8[0])—Offset 154h .................................................................. 2842
29.87 Reserved (RSVD8[1])—Offset 158h .................................................................. 2842
29.88 Reserved (RSVD8[2])—Offset 15Ch.................................................................. 2843
29.89 Reserved (RSVD8[3])—Offset 160h .................................................................. 2843
29.90 Reserved (RSVD8[4])—Offset 164h .................................................................. 2843
29.91 Reserved (RSVD8[5])—Offset 168h .................................................................. 2844
29.92 Reserved (RSVD8[6])—Offset 16Ch.................................................................. 2844
29.93 SMI Status (GPI_SMI_STS_audio_0)—Offset 170h ............................................. 2844
29.94 Reserved (RSVD9[0])—Offset 174h .................................................................. 2854
29.95 Reserved (RSVD9[1])—Offset 178h .................................................................. 2854
29.96 Reserved (RSVD9[2])—Offset 17Ch.................................................................. 2854
29.97 Reserved (RSVD9[3])—Offset 180h .................................................................. 2855
29.98 Reserved (RSVD9[4])—Offset 184h .................................................................. 2855
29.99 Reserved (RSVD9[5])—Offset 188h .................................................................. 2855
Revision History
Document Revision
Description Revision Date
Number Number
§§
This is Volume 2 of the Intel® Pentium® Silver and Intel® Celeron® Processors
Datasheet. Volume 2 provides register information for the SoC.
Refer to document #336560 for the Intel® Pentium® Silver and Intel® Celeron®
Processors Datasheet, Volume 1.
Throughout this document Intel® Pentium® Silver and Intel® Celeron® Processors
is referred as SoC.
Throughout this document Intel® Pentium® Silver and Intel® Celeron® Processors
families refer to:
§§
8086h
15:0 Vendor ID (VENDOR_ID): Hardwired to Intel's Vendor ID value.
RO
600h Class Code 1 (CLASS_CODE1): Hardwired 16'h0600, indicating this device is a Host
31:16
RO Bridge.
0h
31:24 Reserved (RESERVED_1): Reserved
RO
Header Type (HEADER_TYPE): This field identifies the layout of the second part of
80h the predefined header (beginning at byte 10h in the Configuration Space) and also
23:16
RO whether or not the device contains multiple functions. Hardwired to 8'h80, indicating
this is a multi-function device.
0h
7:0 Reserved (RESERVED_0): Reserved
RO
Reserved
0h
31:8 Reserved (RESERVED_0): Reserved
RO
E0h Base Address of First Capability Register (BASE_ADDR): This pointer is an 8-bit
7:0 address to an offset within this device's Configuration Space that holds the first
RO Capability Register (CAPID0_CAPCTRL).
0h
3:1 Reserved (RESERVED_0): Reserved
RO
0h
31:7 Reserved (RESERVED_0): Reserved
RO
Graphics Memory Select (GMS): This field is used to select the amount of Main
Memory that is preallocated to support the Internal Graphics device in VGA nonlinear
and Native linear modes. The BIOS ensures that memory is preallocated only when
Internal graphics is enabled. This register is also Intel TXT lockable. Hardware does not
clear or set any of these bits automatically based on IGD being disabled/enabled. BIOS
Requirement: BIOS must not set this field to 0h if IVD bit 1 of this register is 0.
• 00h:0MB
• 01h:32MB
• 02h:64MB
• 03h:96MB
• 04h:128MB
• 05h:160MB
• 06h:192MB
0h • 07h:224MB
15:8
RW • 08h:256MB
• 09h:288MB
• 0Ah:320MB
• 0Bh:352MB
• 0Ch:384MB
• 0Dh:416MB
• 0Eh:448MB
• 0Fh:480MB
• 10h:512MB
• 20h:...1024MB...
• 30h:...1536MB...
• 3Fh:...2016MB
• 40h-FFh:Illegal value
Size of Graphics Translation Table Memory (GGMS): This field is used to select
the amount of Main Memory that is preallocated to support the Internal Graphics
Translation Table. The BIOS ensures that memory is preallocated only when Internal
0h graphics is enabled. GSM is assumed to be a contiguous physical DRAM space with
7:6 DSM and BIOS needs to allocate a contiguous memory chunk. Hardware will derive the
RW base of GSM from DSM only using the GSM size programmed in the register. Hardware
functionality in case of programming this value to Reserved is not guaranteed. 0x0:No
Preallocated Memory 0x1:2MB of Preallocated Memory 0x2:4MB of Preallocated
Memory 0x3:8MB of Preallocated Memory
0h
5:3 Reserved (RESERVED_0): Reserved
RO
Versatile Acceleration Mode Enable (VAMEN): Enables the use of the iGFX
engines for Versatile Acceleration.
0h
2 • 1: iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is
RW
048000h.
• 0: iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h.
0h
0 GGCLCK: Reserved. Unused by the B-Unit.
RW
0h
31:6 Reserved (RESERVED_1): Reserved
RO
0h
3:2 Reserved (RESERVED_0): Reserved
RO
Base of Protected Content Memory (PCMBASE): 1M, 2M, 4M, and 8M. Base value
0h programmed from Top of Stolen Memory itself defines the size of the Write Only
31:20
RW Protected Content Memory (WOPCM). Separate WOPCM size programming is
redundant information and not required. Default 1M size programming.
0h
19:7 Reserved (RSVD2): Reserved
RO
0h
5 Reserved (RSVD1): Reserved
RO
Heavy Mode Select (HVYMODSEL): This bit is applicable only for PAVP2 operation
mode with a bit also set or for PAVP3 mode only if the perApp memory config is
disabled due to the clearing of an additional bit 9 in the Crypto Function Control_1
0h register address 0x320F0.
3
RW • 0: Lite Mode NonSerpent mode
• 1: Serpent Mode
Note that PAVP2 or PAVP3 mode selection is done by programming bit 8 of the
MFX_MODE Video Mode register.
PAVP Register Lock (PAVPLCK): This lock bit only impacts the Display copy of this
register. In the C-Unit, all register protection is implemented with SAI policy groups.
0h This bit is maintained in the C-Unit for software observability. Display description: This
2
RW bit locks all writeable contents in this register when set, including itself. Only a
hardware reset can unlock the register again. This lock bit needs to be set only if PAVP
is enabled (bit 1 of this register is asserted.)
Protected Content Memory Enable (PCME): This field enables Protected Content
Memory within Graphics Stolen Memory. This memory is the same as the Write Only
Protected Content Memory area whose size is defined by bit 5 of this register. This
register is locked when PAVPLCK is set.
• 0: Protected Content Memory is disabled and cannot be programmed in this
manner when PAVP is enabled.
0h • 1: Protected Content Memory is enabled and is the only programming option
0
RW available when PAVP is enabled.
For non-PAVP3 Mode even for Lite mode configuration this bit should be programmed
to 1'b1 and HVYMODESEL to 1'b0. This bit should always be programmed to 1'b1 if bits
1 and 2 (PAVPE and PAVP lock bits) are both set. With perApp Memory configuration
support the range check for the Write Only Protected Content Memory area should
always happen when this bit is set regardless of Lite or Serpent mode or PAVP2 or
PAVP3 mode programming.
0h
25:3 Reserved (RESERVED_1): Reserved
RO
0h
2:1 LENGTH: Reserved and set to 0 indicating a fixed 256 MB region.
RO
0h
31:7 Reserved (RESERVED_0): Reserved
RO
Reserved
Reserved
Reserved
Reserved
Reserved
0h
19:1 Reserved (RESERVED_1): Reserved
RO
0h LOCK: Reserved. Lock is unused by B-Unit. Register overwrites are protected via SAI
0
RW access control policy registers.
0h
31:7 Reserved (RESERVED_0): Reserved
RO
Base of Data Stolen Memory (BDSM): This register contains the base address of
the Data Stolen Memory. The limit for the Data Stolen Memory is TOLUD-1. This range
is not decoded by the system agent, but is a sub-region of BGSM decoded by the
0h Integrated Graphics Device. Incoming Request Address[31:20] is compared against
31:20
RW BDSM[31:20] and TOLUD[31:20] to determine if the address falls in the range. The
comparison check is as follows: BDSM[31:20]<=Address[31:20] &&
Address[31:20]<TOLUD[31:20] and Address[38:32]==0. Request SAI is then
checked against the allowed SAIs to determine if access is allowed.
0h
19:1 Reserved (RESERVED_0): Reserved
RO
BDSM Register Lock (LOCK): This lock bit only impacts the Display copy of this
0h register. In the C-Unit all register protection is implemented with SAI policy groups.
0
RW This bit is maintained in the C-Unit for software observability. Display description: This
bit will lock all writeable settings in this register, including itself.
Base of Graphics Stolen Memory (BGSM): This register contains the base address
of the Graphics Stolen Memory. The limit for the Graphics Stolen Memory is TOLUD-1.
7B8h Incoming Request Address[31:20] is compared against BGSM[31:20] and
31:20 TOLUD[31:20] to determine if the address falls in the range. The comparison check is
RW as follows: BGSM[31:20]<=Address[31:20] && Address[31:20]<TOLUD[31:20]
and Address[38:32]==0. Request SAI is then checked against the allowed SAIs to
determine if access is allowed.
0h
19:1 Reserved (RESERVED_0): Reserved
RO
0h LOCK: Reserved. Lock is unused by B-Unit. Register overwrites are protected via SAI
0
RW access control policy registers.
Base address of TSEG DRAM Memory (TSEGMB): BIOS determines the base of
TSEG memory which must be at or below Graphics Base of GTT Stolen Memory BGSM.
SMM range starts at this base and ends at BGSM1. Incoming Request Address [31:20]
7B0h will be compared with TSEGMB[31:20] and BGSM[31:20] to determine if the request
31:20 targets the SMM range. The comparison check is as follows:
RW Address[31:20]>=TSEGMB[31:20] && Address[31:20]<BGSM[31:20] and
Address[38:32]==0. If the check passes, the request targets the SMM range. If the
protection for the range is enabled, then the request SAI is compared against allowed
SAIs specified by BSMRRAC and BSMRWAC registers to determine if access is allowed.
0h
19:1 Reserved (RESERVED_0): Reserved
RO
0h LOCK: Reserved. Lock is unused by B-Unit. Register overwrites are protected via SAI
0
RW access control policy registers.
Top of Lower Usable DRAM (TOLUD): Defines the top of lower usable DRAM, which
ends at the preceding byte. Lower MMIO Address range starts at this address and
800h continues up to the 4GB Address 0xFFFF_FFFF. Bits 31:20 are compared with incoming
31:20 request Address[31:20] to determine whether the request targets lower usable DRAM
RW range or the lower MMIO range. If Request Address[31:20]>=TOLUD[31:20] and
Request Address[38:32]==0 then the Request Address falls in the Lower MMIO
Address range.
0h
19:1 Reserved (RESERVED_0): Reserved
RO
0h LOCK: Reserved. Lock is unused by B-Unit. Register overwrites are protected via SAI
0
RW access control policy registers.
0h
3:1 Reserved (RESERVED_0): Reserved
RO
0h
31:7 Reserved (RESERVED_0): Reserved
RO
Reserved
0h
31:0 Scratchpad (SKPD): 1 DWORD of data storage.
RW
0h
31:28 Reserved (RESERVED_0): Reserved
RO
1h Capability ID Version (CAPID_VER): This field has the value 0001b to identify the
27:24
RO first revision of the CAPID register definition.
Ch Capability ID0 Structure Length (CAPIDLEN): This field has the value 0Ch to
23:16 indicate the structure length 12 bytes. This is the total size of this CAPCTRL and the
RO CAPID0_A and CAPID0_B registers in the following bytes.
9h Capability ID (CAP_ID): This field has the value 1001b to identify the CAP_ID
7:0
RO assigned by the PCI SIG for vendor dependent capability pointers.
0h
31:24 Spare 31-24 (SPARE31_24): Reserved for future capabilities.
RW
0h
22 Fuse Spare 22 (FUSE_SPARE22): Fuse backed spare.
RW
0h
21 Fuse Spare 21 (FUSE_SPARE21): Fuse backed spare.
RW
0h
20 Fuse Spare 20 (FUSE_SPARE20): Fuse backed spare.
RW
0h
19 Fuse Spare 19 (FUSE_SPARE19): Fuse backed spare.
RW
0h
18 Fuse Spare 18 (FUSE_SPARE18): Fuse backed spare.
RW
0h
17:16 Reserved (RSVD): Reserved
RO
0h
14 Fuse Spare 14 (FUSE_SPARE14): Fuse backed spare.
RW
0h
13 Fuse Spare 13 (FUSE_SPARE13): Fuse backed spare.
RW
0h
12 Fuse Spare 12 (FUSE_SPARE12): Fuse backed spare.
RW
Control Device ID Value (CDID): Controls the value of Dev2 GFX device ID.
Hardwired to 2b00. Identifier assigned to the core/primary PCI device.The
corresponding two bit capability ID programming is:
0h
9:8 • 00: Desktop
RO
• 01: Mobile
• 10: Server
• 11: Marketing Spare
0h
7:0 Spare 7-0 (SPARE7_0): Reserved for future capabilities.
RW
0h
30 Fuse Spare 30 (FUSE_SPARE30): Fuse backed spare.
RW
0h
23:0 Spare 23-0 (SPARE23_0): Reserved for future capabilities.
RW
0h
31:0 Spare bits[31:0] (SPARE_RW): Spare RW bits for future usage.
RW
0h
31:0 Spare bits[31:0] (SPARE_RW): Spare RW bits for future usage.
RW
§§
0h
18:17 Reserved (RSVD18_17): Reserved
RO
Fine Bank Group Interleaving Enable (FBGINTEN): When enabled, D-unit will use
a lower order address bit in the bank hashing function (DDR4 Only).
0h
16 • 0: Bank Group Interleave disabled.
RW
• 1: Bank Group Interleave enabled.
Note: BAHEN must be set for this bit to take effect.
0h
13:9 Reserved (RSVD13_9): Reserved
RO
DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h
8:6 • 010: 8 Gb.
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.
DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
0h • 00: x8.
5:4
RW • 01: x16.
• 10: x32.
• 11: x64.
0h
3 Reserved (RSVD3): Reserved
RO
0h
1 Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to enable use of this rank.
RW
0h Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to enable use of this rank.
0
RW Note: Setting this bit to 0 is not a functional mode.
0h
31:23 Reserved (RSVD31_23): Reserved
RO
5h Write to Write DQ Delay Same Bank Group Same Rank (TWWSR_L): Specifies
22:18 the delay from a DRAM Write to another Write command within the same bank group of
RW the same rank (in DRAM clocks). DDR4 Equation: tWWSR_L = tCCD_L.
5h Read to Read DQ Delay Same Bank Group Same Rank (TRRSR_L): Specifies the
17:13 delay from a DRAM Read to another Read command within the same bank group of the
RW same rank (in DRAM clocks). DDR4 Equation: tRRSR_L = tCCD_L.
Write to Read DQ Delay Same Bank Group Same Rank (TWRSR_L): Specifies
15h the delay from a DRAM Read to Write command within the same bank group of the
12:6 same rank (in DRAM clocks).
RW
• DDR4 Equation: tWRSR_L = CWL + tDQSSmax + BL/2 + tWPST + tWTR_L.
Bh Activate RAS to CAS Command Delay [tRCD] (TRCD): Specifies the delay
11:6 between a DRAM Activate command and a DRAM Read or Write command to the same
RW bank (in DRAM clocks). Note: Derating adds 1.875ns to this timing.
Exit Power Down to Next Command Delay [tXP] (TXP): Specifies the delay from
6h the DRAM Power Down Exit (PDX) command to any valid command (in DRAM clocks).
31:27
RW Note: The value in this field must be programmed to tXPDLL when Slow Exit Mode
Power-down is enabled for DDR3L.
0h
26 Reserved (RSVD26): Reserved
RO
18h ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay between the DRAM ZQ
5:0
RW Calibration Latch command and any DRAM command (in DRAM clocks). LPDDR4 only.
118h All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies the delay between the
31:22
RW REFab command to the next valid command. (in DRAM clocks)
0h
21 Reserved (RSVD21): Reserved
RO
4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the minimum time from CKEL
20:17
RW to CKEH (in DRAM clocks).
0h
16 Reserved (RSVD16): Reserved
RO
C30h Refresh Interval Time [tREFI] (NREFI): Specifies the average time between
15:0 refresh commands. JEDEC Base Refresh Interval time (in DRAM clocks). Note: D-Unit
RW will ignore the 2 LSBs of this field.
Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay between
the DRAM Read and Precharge commands to the same bank (in DRAM clocks).
6h • LPDDR3 Equation: = NA.
31:27
RW • LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• WIO2 Equation: = NA.
• DDR3L/DDR4 Equation: = tRTP.
CAS to CAS Command Delay Adder (TCCD_INC): Specifies the number of clocks
0h to be added to turnaround times (for Stretch Mode). It increases delay between Read
26:20
RW to Read or Read to Write commands by the amount programmed in this field (in 4 x
DRAM clocks).
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
1h • 0h: Reserved.
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L/DDR4 only. tCMD must be set to 1N for LPDDR3/LPDDR4/WIO2.
8h Write Latency [WL/CWL] (TCWL): The delay between the internal write command
10:6
RW and the availability of the first word of DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW + 8 (BL32).
RW
• WIO2 Equation: NA.
Note: Masked Write operation in LPDDR4 is always BL16 and in WIO2 is always BL4.
D-Unit applies this timing for same rank as well as same bank.
30h Four Bank Activate Window [tFAW] (TFAW): A rolling timeframe in which a
31:24 maximum of four Activate commands can be issued to the same rank. This is to limit
RW the peak current draw from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 - (RL + tDQSCKmin -
8h
23:18 tRPRE).
RW
• LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 - tDQSCKmin.
• DDR3L/DDR4 Equation: tWRDR = CWL + tDQSSmax + BL/2 - (CL + tDQSCKmin -
tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
9h
17:12 • LPDDR3/LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL - tWPRE).
RW
• DDR3L/DDR4 Equation: tRWDR = CL + tDQSCKmax + BL/2 - (CWL - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.
Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Write data burst of a different
rank (in DRAM clocks).
5h
11:6 • LPDDR3/DDR3L/DDR4 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
RW tWPRE.
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
9h start of a Read data burst of one rank to the Start of a Read data burst of a different
5:0 rank (in DRAM clocks).
RW
• Equation: tRRDR = BL/2 + tDQSCKmax - tDQSCKmin + tRPRE.
Row Activation to Row Activation Delay [tRRD] (TRRD): Specifies the minimum
6h delay in DRAM clocks between two DRAM Activate commands to the same rank but
31:27
RW different banks (tRC is the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.
0h
26 Reserved (RSVD26): Reserved
RO
10h Write to Write DQ Delay Same Rank (TWWSR): Specifies the delay from a DRAM
22:18 Write to another Write command of the same rank (in DRAM clocks). Equation: tWWSR
RW = tCCD.
10h Read to Read DQ Delay Same Rank (TRRSR): Specifies the delay from a DRAM
17:13 Read to another Read command of the same rank (in DRAM clocks). Equation: tRRSR =
RW tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).
3h
12:6 • LPDDR3/LPDDR4/WIO2 Equation: tWRSR = WL + tDQSSmax + BL/2 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR.
• DDR4 Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR_S.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle period that defines an
31:24
RW opportunity for refresh (in DRAM clocks).
0h
18:15 Reserved (RSVD18_15): Reserved
RW
Mode Register Read to Any Command Delay (TPSTMRRBLK): Specifies the quiet
time after issuing MRR command (in DRAM Clocks). This is the channel block time for
0h the MR19 command issued as part of LPDDR4 DQS Retraining flow. For all other MR
14:8 commands this is the rank block time. Note: D-Unit treats MRR as a read and always
RW applies relevant turnaround times, any value programmed in this CR must be greater
than those turnaround times for D-Unit to enforce any additional time from MRR to the
next read/write.
0h
7 Reserved (RSVD7): Reserved
RO
All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies the
delay between a DRAM Precharge All Bank command and a DRAM Activate command
3h (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4 in LP3 and
31:26 minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L, DDR4 and WIO2 8ch tRPpb = tRPab = tRP.
0h
8:7 Reserved (RSVD8_7): Reserved
RO
6h Row Activation Period [tRAS] (TRAS): Specifies the minimum delay between the
6:0 DRAM Activate and Precharge commands to the same bank (in DRAM clocks). Note:
RW Derating adds 1.875ns to this timing.
6h Minimum Low Power Mode Residency (LPMDRES): Specifies the minimum time
25:21
RW that PHY should remain in LPMode (in DRAM clocks).
Low Power Mode Exit to Clock Enable Delay (LPMDTOCKEDLY): Specifies the
Ah minimum time between the LP Mode exit to the CK stop/tristate deassertion and
20:15
RW powerdown exit (in DRAM clocks). Note: Must be equal to t_idle_latency published in
the DDRIO PHY and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY): Specifies the time
Ah between CK stop/tristate to the Low Power Mode entry. This timing parameter is used
14:8
RW to delay Low Power Mode entry (in DRAM clocks). Note: Must be at least equal to
t_idle_length parameter published in the DDRIO PHY and less than 0x7C.
18h Power Down Idle Timer (PWDDLY): This is a non-JEDEC timing parameter used to
7:0
RW delay powerdown entry (in DRAM clocks).
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Rank 1 Read ODT Control (R1RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 1. 0 - Read ODT is disabled for Rank 1 1 -
29
RW Assert ODT to for Rank 0 (non-targeted Rank) Note: This register should be set to 0 for
LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 0. 0 - Read ODT is disabled for Rank 0 1 -
28
RW Assert ODT to for Rank 1 (non-targeted Rank) Note: This register is reserved for
LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 1. 00 - Write ODT is disabled 01 - Assert ODT
27:26
RW to Rank 0 (non-targeted Rank) 10 - Assert ODT to Rank 1 (targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
Rank 0 Write ODT Control (R0WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 0. 00 - Write ODT is disabled 01 - Assert ODT
25:24
RW to Rank 0 (targeted Rank) 10 - Assert ODT to Rank 1 (non-targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
0h
23:18 Reserved (RSVD23_18): Reserved
RO
0h
13 Reserved (RSVD13): Reserved
RO
0h
4 Reserved (RSVD4): Reserved
RO
0h
31:29 Reserved (RSVD31_29): Reserved
RO
0h
23 Reserved (RSVD23): Reserved
RO
PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to deassert
before sending a PM message on SR entry.
0h
22 • 0: D-Unit will not wait for SPID_clk to deassert before sending the PM message to
RW PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.
Self-Refresh Entry Delay (SREDLY): Specifies the minimum time the D-Unit will
0h wait before it enters Dynamic Self-Refresh mode when idle (in 16x DRAM Clocks).
15:0
RW Note: The value in this field needs to be minimum of 4 in functional mode and
minimum of 50 in PSMI mode.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS): Setting this bit to 0 allows
majority of the repeaters between D-Unit and PHY to clock gate when there is no
activity in order to save power.
0h
29 • 0 - Enable Repeaters clock gating.
RW
• 1 - Disable Repeaters clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS): Setting this bit to 0
enables the clock gating of IOSF-SB End Points in D-Unit and CPGC when there is no
IOSF-SB activity in order to save power.
1h
28 • 0 - Enable IOSF-SB EP clock gating.
RW
• 1 - Disable IOSF-SB clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power. When
set to 1, D-Unit clockgating is disabled.
0h
27 • 0: Enable.
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
0h Partial Array Self-Refresh Segment Mask (PASR): This is the Segment Mask used
23:16
RW for the MRW to enable PASR during SUSPENDP (Partial Array Self Refresh entry).
0h Page Close Timeout Period (PCLSTO): Specifies the time from the last access of a
15:8 DRAM page until that page is scheduled to close by sending a Precharge command to
RW DRAM (in 16 x DRAM clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
0h the DRAM page when idle.
7
RW • 0: Enable page close timer.
• 1: Disable page close timer (Used during DRAM init and DDRIO training).
0h
6 Reserved (RSVD6): Reserved
RO
Low Power Mode Opcode (LPMODEOP): D-Unit will send the value in this register
0h after it has entered Powerdown Mode and has stopped/tristated the clock. 00: Disable
2:1
RW LPMode. Note: LPMODE entry is not possible when global tristate flow is disabled
(DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0 for
normal operation.
0h • 0: The D-Unit dynamically controls the CKE pins to place the DRAM devices in
0
RW Power Down mode and bring them out of Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the DRAM devices from
entering Power Down mode when ranks are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior on
SR entry/exit.
0h
24:22 Reserved (RSVD24_22): Reserved
RO
Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:
0h
21 • 0: D-Unit sends all postponed REF commands to DRAM before it enters Self
RW
Refresh.
• 1: D-Unit enters SR without clearing the Refresh Debt (for Debug only).
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h
17:16 Reserved (RSVD17_16): Reserved
RO
0h Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit adds one extra
15
RW refresh debit (for a total of two) on Self-refresh exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Stop issuing refresh commands and accumulating refresh debits. (does not
stop tREFI counter).
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h
14:12 • 010: 0.5x refresh rate (i.e. 2x tREFI).
RW
• 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh counter per rank is
7h greater than this value, the D-Unit will send a REF command to the rank regardless of
11:8 pending requests. Note: REFWMPNC must be greater than or equal to REFWMHI and
RW greater than 2, Max Value must be less than 8 to not violate 9xtREFI JEDEC
requirement.
Refresh High Watermark (REFWMHI): When the Refresh counter per rank is
5h greater than this value, the D-Unit will send a REF command to the rank if there is no
7:4
RW critical priority requests in the pending queues. Note: Value must be greater or equal
to 1 and less than or equal to REFWMPNC.
0h
3:1 Reserved (RSVD3_1): Reserved
RO
0h • 0: D-Unit will send a REF command only if there is no pending request to that
0 rank.
RW
• 1: D-Unit will not send any opportunistic refreshes. Refresh commands are only
sent when the refresh counter is greater than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.
0h Early Write DQ Enable (EARLY_DQ_EN): Enables D-unit to send the write data to
31 the PHY one clock earlier than WL value (WL - 1). Note: Applicable to DDR3L and DDR4
RW only.
1Ch Write Pending Queue Count (WPQCOUNT): Used to limit the number of available
26:21 slots in Write Pending Queue/ Write Data Buffer. WPQCOUNT will only recognize
RW changes when PMI ISM is not active.
10h Read Pending Queue Count (RPQCOUNT): Used to limit the number of entries in
20:16 Read Pending Queue. RPQCOUNT will only recognize changes when PMI ISM is not
RW active.
0h
15 Reserved (RSVD15): Reserved
RO
Idle Bypass Mode Enable (BYPASSEN): When set new page hit/empty read
0h requests will bypass D-Unit pipeline stages to save latency 0 - Disable Idle Bypass 1 -
7
RW Enable Idle Bypass Note: Only applies to WIO2, this bit is reserved for other
technologies
0h Block When RDB Full (BLKRDBF): When set D-Unit stops scheduling new read
6
RW commands to DRAM when the read data buffer (RDB) is full.
0h
28:23 Reserved (RSVD28_23): Reserved
RO
0h
20:18 Reserved (RSVD20_18): Reserved
RO
0h
15:14 Reserved (RSVD15_14): Reserved
RO
1057h ZQ Calibration Interval (ZQINT): Specifies the time interval between two ZQCS
13:0 (LPDDR3/DDR3L/DDR4) or ZQ Start (LPDDR4) commands to a DRAM device. (in RTC
RW 32.8KHz clocks)
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h MR Value 2 (MR_VALUE2): MR3 Shadow Register (DDR4): BIOS writes the correct
29:16 value of MR3 register in DDR4 into this field at boot time. D-Unit modifies one bit and
RW rewrites the MR3 into DDR4 to enter and exit MPR mode.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
MR Value (MR_VALUE): MR3 Shadow Register (WIO2): BIOS sets the value of this
field at boot time based on the DRAM device configuration. D-Unit merges the value in
MR3_THERM_OFFSET with this field and writes the result into DRAM MR3 MR2 Shadow
0h Register (DDR3L): BIOS writes the correct value of MR2 register in DDR3L into this
13:0
RW field at boot time. D-Unit modifies one bit and rewrites the MR2 into DDR3L DRAM
before SR entry. MR4 Shadow Register (DDR4): BIOS writes the correct value of MR4
register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the
MR4 into DDR4 DRAM after temperature read out.
0h
30:12 Reserved (RSVD30_12): Reserved
RO
0h
11:0 VNN Timer Time (VNN_TIMER_TIME): The final timer value (in 16 x DRAM clocks).
RW
3h TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value will remain zero. This
31:29 field contains the data of the last temperature sensor read from Rank 1 DRAM Mode
RW/V Register. It is overwritten with each command.
3h TQ Data Rank 0 (TQDATAR0): This field contains the data of the last temperature
28:26
RW/V sensor read from Rank 0 DRAM Mode Register. It is overwritten with each command.
0h
25:22 Reserved (RSVD25_22): Reserved
RO
0h TQ Poll Period (TQPOLLPER): This sets the frequency by which the D-Unit initiates
21:8 temperature sensor read from DRAM mode register to determine required refresh rate
RW (in 4x tREFI units).
Self Refresh Temperature Range Enable (DDR3 Only) (SRTEN): When set,
0h before every Self refresh entry, D-Unit writes a 1 to bit 7 of MR_SHADOW.MR_VALUE
4
RW when TQDATA for that rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3 for each enabled rank.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-Unit pushes the data
2
RW form the last temperature sensor read to a punit register.
0h Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic TQ Poll. If disabled,
0
RW D-Unit will not read the DRAM's temperature sensor value periodically.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
0h
15:11 Reserved (RSVD15_11): Reserved
RO
0h MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to TQDATA read from
10:8
RW MR4 the resulting value is used to control refresh rate and AC timing derating.
0h
7:3 Reserved (RSVD7_3): Reserved
RO
0h MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-Unit writes the merged
2 value of MR3_VALUE and MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this
RW/V bit once the value is written.
Initialization Complete (IC): Indicates that initialization of the D-Unit has been
completed. Memory accesses are permitted and maintenance operation begins. Until
0h this bit is set to a 1, the memory controller will not accept DRAM requests from the
31
RW/V Bunit/GSA/2LM (PMI ISMs will not leave idle). Note: Set this bit to 1 only when all
other D-Unit registers have been configured. Usually set at the last configuration step
by BIOS on cold/warm reset. D-Unit hardware sets this bit on SR exit.
0h DDRIO PHY Initialization Complete (DIOIC): Status indication that the DDRIO
30
RO/V PHY initialization is complete reflects the status spid_init_complete signal.
0h
29 Reserved (RSVD29): Reserved
RO
0h
27:8 Reserved (RSVD27_8): Reserved
RO
0h
7:4 Reserved (RSVD7_4): Reserved
RO
Enable PSMI Mode (PSMIEN): When enabled, D-Unit will synchronize clock crossing
signals.
0h
3 • 0: PSMI Mode is disabled.
RW
• 1: PSMI Mode is enabled.
Note: Change only allowed when D-Unit is idle.
0h
0 Reserved (RSVD0): Reserved
RO
0h
30 Reserved (RSVD30): Reserved
RO
Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
0h • 00: Clock gate disabled.
29:28
RW • 01: Clock Gate every 2 cycles.
• 10: Clock Gate every 3 cycles.
• 11: Clock Gate every 4 cycles.
0h
27:16 Reserved (RSVD27_16): Reserved
RO
0h Scrambling Key (KEY): Sets the key for the scrambler. The key should be a random
15:0
RW value that is set following each cold boot.
0h
31 Reserved (RSVD31): Reserved
RO
0h Error Injection Target Address (ADDRESS): Specifies the PMI address of the write
30:1 transaction to be injected with the error. Only applicable to Write transactions. Read/
RW under-fill read of the partial write operation is not affected.
0h
0 Reserved (RSVD0): Reserved
RO
0h
31:4 Reserved (RSVD31_4): Reserved
RO
Error Injection Type Higher 32B (SEL_HI): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
3 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Higher 32B (EN_HI): When set the error injection is
2 continuously armed for higher 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
1 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Lower 32B (EN_LO): When set, the error injection is
0 continuously armed for lower 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
0h
31 CLEAR: Setting this bit to one clears all fields in this register, including itself.
RW/V
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a correctable single-bit
0h error occurs on a memory read data transfer. When this bit is set, the address that
28 caused the error and the error syndrome are also logged and they are locked to further
RW/V single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is
set will override the address/error syndrome information.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of the error within a
26:25
RW/V chunk.
0h Error Chunk Number (ERR_CHUNK): Chunk number of the error. 0 - lower 32B
24 chunk has error if MERR/CERR is set 1 - higher 32B chunk has the error if MERR/CERR
RW/V is set
0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome for a QW (64 bit)
23:16
RW/V within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI Request Tag which
15:0
RW/V triggered the error log.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
D-Unit Fuse Status (FUSESTAT): D-Unit fuse bits are captured into this register and
are available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V • [5:5]: fus_dun_lpddr4_dis.
• [6:6]: fus_dun_wio2_dis.
• [7:7]: fus_dun_ddr3l_dis.
• [8:8]: fus_dun_ddr4_dis.
• [15:9]: reserved.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
RAW Conflict Read Priority for WMM Transition (RAW_WMM): If a conflict read
5h reaches this priority (or greater depending on access class occupancy), WMM will be
29:27 triggered to unblock the corresponding write. D-Unit will stay in WMM until
RW corresponding write is issued. Note: The value in this bit must not be higher than
lowest terminal priority level of each access class.
0h
26 Reserved (RSVD26): Reserved
RO
6h Read Isoch Trigger Priority (RIMPRIO): If any read in the RPQ is at this
25:23
RW programmable priority, RIM is triggered.
0h
22:18 Reserved (RSVD22_18): Reserved
RO
1Ah Write Isoch Threshold (WIMTHRS): When the number of entries in WPQ is greater
17:12 than or equal to this value (higher than WMM entry watermark, less than WPQ size), it
RW triggers write isoch mode (WIM).
14h Write Major Mode Exit Watermark (WMMEXIT): When the number of entries in
11:6
RW WPQ is less than this value, the D-Unit will switch back to read major mode.
18h Write Major Mode Entry Watermark (WMMENTRY): When the number of entries
5:0 in WPQ is greater than or equal to this value, the D-Unit will switch to write major
RW mode (WMM). Note: the value must not be set to 0.
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes B (MAXWRB): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set B).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes A (MAXWRA): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set A).
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes D (MAXWRD): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set D).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes C (MAXWRC): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set C).
0h
31:15 Reserved (RSVD31_15): Reserved
RO
1h Access Class 4 Initial Priority (AC4IP): Initial priority level of read requests
14:12
RW coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of read requests
11:9
RW coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of read requests
8:6
RW coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of read requests
5:3
RW coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of read requests
2:0
RW coming with access class 0.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Ah Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:11 Reserved (RSVD31_11): Reserved
RO
0h
31:25 Reserved (RSVD31_25): Reserved
RO
0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe write page hits block
24
RW safe write page misses same bank.
0h
23:20 Reserved (RSVD23_20): Reserved
RO
WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe priority 1 read miss
0h block write hit to same bank. Note: This rule does not block the bank that is being
19
RW blocked by WMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe priority 1 write hit
0h block write miss to same bank. Note: This rule does not block the bank that is being
18
RW blocked by WMM_PRIO_R1. Priority rules 1,3 and 4 should be enabled/disabled
together.
0h
17 WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS block rule.
RW
0h WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe top priority 1 write
16 miss block write hit same bank. Priority rules 1, 3 and 4 should be enabled/disabled
RW together.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe write page hits block
13
RW safe write page misses same bank.
1h RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe read page miss block
12 all safe and unsafe write page hit to the same bank. Note: This field must not be set to
RW 0 (enabled) if RMM_REG_R4 is also 0.
1h RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe write page hit block
11 safe read page miss same bank. Note: This field must not be set to 0 (enabled) if
RW RMM_REG_R5 is also 0.
0h RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe read page hit block safe
10 read and write page miss same bank. Note: This rule does not block the bank that is
RW being blocked by RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe read page empty block
9
RW safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe read page hit block safe
8
RW write page hit same rank.
0h
7:4 Reserved (RSVD7_4): Reserved
RO
RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe critical read miss block
0h read and write hit to same bank. Note: This rule does not block the bank that is being
3
RW blocked by RMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe critical read hit block
0h read and write miss to same bank. Note: This rule does not block the bank that is being
2
RW blocked by RMM_PRIO_R1. Priority rules 1, 3 and 4 should be enabled/disabled
together.
0h
1 RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block rule.
RW
0h RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe top critical read miss
0 block read and write hit same bank. Note: Priority rules 1, 3 and 4 should be enabled/
RW disabled together.
0h
31:4 Reserved (RSVD31_4): Reserved
RO
SUSPENDP: A SUSPENDP message will put the DRAM into self-refresh mode. The D-
Unit will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in self refresh mode. Finally, a PM
3 message will be sent to the PHY. The bit is cleared by hardware after the PHY indicates
RW/V the transition requested in the PM message has been completed. D-Unit will perform an
MRW to MR17 with an opcode as defined by DPMC0.PASR before it places the DRAM
into Self-Refresh.
SUSPEND: A SUSPEND message will put the DRAM into self-refresh mode. The D-Unit
will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in Self Refresh mode. Finally, a PM
2
RW/V message will be sent to the PHY. The bit is cleared by hardware only after the PHY
indicates the transition requested in the PM message has been completed. Note: When
COLDWAKE is set prior of setting this bit the DRAM will not be placed in SR.
0h
1 Reserved (RSVD1): Reserved
RO
WAKE: Take PHY out of PM states and wakes the DRAM out of self refresh mode. The
0h bit is cleared by hardware only when the DRAM has exited out of self refresh mode and
0
RW/V is accessible. Note: When COLDWAKE is set prior of setting this bit the D-Unit will not
send SR exit command and will not set the DCO.IC bit.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts DQS oscillator, it must
0h wait this amount of time before being able to read the value in MR18 and MR19 (in 16x
13:4
RW DRAM clocks). Value in this register must be at least equal to DRAM's MR23 value. +
tOSCO.
0h
31 Reserved (RSVD31): Reserved
RO
0h
30:28 MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of MR4 data.
RW
0h
27 Reserved (RSVD27): Reserved
RO
0h
26:24 MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of MR4 data
RW
0h
23 Reserved (RSVD23): Reserved
RO
0h
22:20 MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of MR4 data.
RW
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of the MR4 data for
17:16
RW second device.
0h
15 Reserved (RSVD15): Reserved
RO
0h
14:12 MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW
0h
11 Reserved (RSVD11): Reserved
RO
0h
10:8 MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW
0h
7 Reserved (RSVD7): Reserved
RO
0h
6:4 MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW
0h
3:2 Reserved (RSVD3_2): Reserved
RO
0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of the MR4 data first
1:0
RW device.
0h
18:17 Reserved (RSVD18_17): Reserved
RO
Fine Bank Group Interleaving Enable (FBGINTEN): When enabled, D-unit will use
a lower order address bit in the bank hashing function (DDR4 Only).
0h
16 • 0: Bank Group Interleave disabled.
RW
• 1: Bank Group Interleave enabled.
Note: BAHEN must be set for this bit to take effect.
0h
13:9 Reserved (RSVD13_9): Reserved
RO
DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h
8:6 • 010: 8 Gb.
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.
DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
0h • 00: x8.
5:4
RW • 01: x16.
• 10: x32.
• 11: x64.
0h
3 Reserved (RSVD3): Reserved
RO
0h
1 Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to enable use of this rank.
RW
0h Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to enable use of this rank.
0
RW Note: Setting this bit to 0 is not a functional mode.
0h
31:23 Reserved (RSVD31_23): Reserved
RO
5h Write to Write DQ Delay Same Bank Group Same Rank (TWWSR_L): Specifies
22:18 the delay from a DRAM Write to another Write command within the same bank group of
RW the same rank (in DRAM clocks). DDR4 Equation: tWWSR_L = tCCD_L.
5h Read to Read DQ Delay Same Bank Group Same Rank (TRRSR_L): Specifies the
17:13 delay from a DRAM Read to another Read command within the same bank group of the
RW same rank (in DRAM clocks). DDR4 Equation: tRRSR_L = tCCD_L.
Write to Read DQ Delay Same Bank Group Same Rank (TWRSR_L): Specifies
15h the delay from a DRAM Read to Write command within the same bank group of the
12:6 same rank (in DRAM clocks).
RW
• DDR4 Equation: tWRSR_L = CWL + tDQSSmax + BL/2 + tWPST + tWTR_L.
Bh Activate RAS to CAS Command Delay [tRCD] (TRCD): Specifies the delay
11:6 between a DRAM Activate command and a DRAM Read or Write command to the same
RW bank (in DRAM clocks). Note: Derating adds 1.875ns to this timing.
Exit Power Down to Next Command Delay [tXP] (TXP): Specifies the delay from
6h the DRAM Power Down Exit (PDX) command to any valid command (in DRAM clocks).
31:27
RW Note: The value in this field must be programmed to tXPDLL when Slow Exit Mode
Power-down is enabled for DDR3L.
0h
26 Reserved (RSVD26): Reserved
RO
18h ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay between the DRAM ZQ
5:0 Calibration Latch command and any DRAM command (in DRAM clocks). LPDDR4 only.
RW Not used in DDR3L/DDR4/LPDDR3/WIO2.
118h All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies the delay between the
31:22
RW REFab command to the next valid command. (in DRAM clocks)
0h
21 Reserved (RSVD21): Reserved
RO
4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the minimum time from CKEL
20:17
RW to CKEH (in DRAM clocks).
0h
16 Reserved (RSVD16): Reserved
RO
C30h Refresh Interval Time [tREFI] (NREFI): Specifies the average time between
15:0 refresh commands. JEDEC Base Refresh Interval time (in DRAM clocks). Note: D-Unit
RW will ignore the 2 LSBs of this field.
Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay between
the DRAM Read and Precharge commands to the same bank (in DRAM clocks).
6h • LPDDR3 Equation: = BL/2 + tRTP - 4.
31:27
RW • LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• WIO2 Equation: = NA.
• DDR3L/DDR4 Equation: = tRTP.
CAS to CAS Command Delay Adder (TCCD_INC): Specifies the number of clocks
0h to be added to turnaround times (for Stretch Mode). It increases delay between Read
26:20
RW to Read or Read to Write commands by the amount programmed in this field (in 4 x
DRAM clocks).
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
1h • 0h: Reserved.
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L/DDR4 only. tCMD must be set to 1N for LPDDR3/LPDDR4/WIO2.
8h Write Latency [WL/CWL] (TCWL): The delay between the internal write command
10:6
RW and the availability of the first word of DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW + 8 (BL32).
RW
• WIO2 Equation: NA.
Note: Masked Write operation in LPDDR4 is always BL16 and in WIO2 is always BL4.
D-Unit applies this timing for same rank as well as same bank.
30h Four Bank Activate Window [tFAW] (TFAW): A rolling timeframe in which a
31:24 maximum of four Activate commands can be issued to the same rank. This is to limit
RW the peak current draw from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 - (RL + tDQSCKmin -
8h
23:18 tRPRE).
RW
• LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 - tDQSCKmin.
• DDR3L/DDR4 Equation: tWRDR = CWL + tDQSSmax + BL/2 - (CL + tDQSCKmin -
tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
9h
17:12 • LPDDR3/LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL - tWPRE).
RW
• DDR3L/DDR4 Equation: tRWDR = CL + tDQSCKmax + BL/2 - (CWL - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.
Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Write data burst of a different
rank (in DRAM clocks).
5h
11:6 • LPDDR3/DDR3L/DDR4 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
RW tWPRE.
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
9h start of a Read data burst of one rank to the Start of a Read data burst of a different
5:0 rank (in DRAM clocks).
RW
• Equation: tRRDR = BL/2 + tDQSCKmax - tDQSCKmin + tRPRE.
Row Activation to Row Activation Delay [tRRD] (TRRD): Specifies the minimum
6h delay in DRAM clocks between two DRAM Activate commands to the same rank but
31:27
RW different banks (tRC is the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.
0h
26 Reserved (RSVD26): Reserved
RO
10h Write to Write DQ Delay Same Rank (TWWSR): Specifies the delay from a DRAM
22:18 Write to another Write command of the same rank (in DRAM clocks). Equation: tWWSR
RW = tCCD.
10h Read to Read DQ Delay Same Rank (TRRSR): Specifies the delay from a DRAM
17:13 Read to another Read command of the same rank (in DRAM clocks). Equation: tRRSR =
RW tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).
3h
12:6 • LPDDR3/LPDDR4/WIO2 Equation: tWRSR = WL + tDQSSmax + BL/2 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR.
• DDR4 Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR_S.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle period that defines an
31:24
RW opportunity for refresh (in DRAM clocks).
0h
18:15 Reserved (RSVD18_15): Reserved
RW
Mode Register Read to Any Command Delay (TPSTMRRBLK): Specifies the quiet
time after issuing MRR command (in DRAM Clocks). This is the channel block time for
0h the MR19 command issued as part of LPDDR4 DQS Retraining flow. For all other MR
14:8 commands this is the rank block time. Note: D-Unit treats MRR as a read and always
RW applies relevant turnaround times, any value programmed in this CR must be greater
than those turnaround times for D-Unit to enforce any additional time from MRR to the
next read/write.
0h
7 Reserved (RSVD7): Reserved
RO
All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies the
delay between a DRAM Precharge All Bank command and a DRAM Activate command
3h (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4 in LP3 and
31:26 minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L, DDR4 and WIO2 8ch tRPpb = tRPab = tRP.
0h
8:7 Reserved (RSVD8_7): Reserved
RO
6h Row Activation Period [tRAS] (TRAS): Specifies the minimum delay between the
6:0 DRAM Activate and Precharge commands to the same bank (in DRAM clocks). Note:
RW Derating adds 1.875ns to this timing.
6h Minimum Low Power Mode Residency (LPMDRES): Specifies the minimum time
25:21
RW that PHY should remain in LPMode (in DRAM clocks).
Low Power Mode Exit to Clock Enable Delay (LPMDTOCKEDLY): Specifies the
Ah minimum time between the LP Mode exit to the CK stop/tristate deassertion and
20:15
RW powerdown exit (in DRAM clocks). Note: Must be equal to t_idle_latency published in
the DDRIO PHY and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY): Specifies the time
Ah between CK stop/tristate to the Low Power Mode entry. This timing parameter is used
14:8
RW to delay Low Power Mode entry (in DRAM clocks). Note: Must be at least equal to
t_idle_length parameter published in the DDRIO PHY and less than 0x7C.
18h Power Down Idle Timer (PWDDLY): This is a non-JEDEC timing parameter used to
7:0
RW delay powerdown entry (in DRAM clocks).
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Rank 1 Read ODT Control (R1RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 1. 0 - Read ODT is disabled for Rank 1 1 -
29
RW Assert ODT to for Rank 0 (non-targeted Rank) Note: This register should be set to 0 for
LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 0. 0 - Read ODT is disabled for Rank 0 1 -
28
RW Assert ODT to for Rank 1 (non-targeted Rank) Note: This register is reserved for
LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 1. 00 - Write ODT is disabled 01 - Assert ODT
27:26
RW to Rank 0 (non-targeted Rank) 10 - Assert ODT to Rank 1 (targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
Rank 0 Write ODT Control (R0WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 0. 00 - Write ODT is disabled 01 - Assert ODT
25:24
RW to Rank 0 (targeted Rank) 10 - Assert ODT to Rank 1 (non-targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
0h
23:18 Reserved (RSVD23_18): Reserved
RO
0h
13 Reserved (RSVD13): Reserved
RO
0h
4 Reserved (RSVD4): Reserved
RO
0h
31:29 Reserved (RSVD31_29): Reserved
RO
0h
23 Reserved (RSVD23): Reserved
RO
PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to deassert
before sending a PM message on SR entry.
0h
22 • 0: D-Unit will not wait for SPID_clk to deassert before sending the PM message to
RW PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.
Self-Refresh Entry Delay (SREDLY): Specifies the minimum time the D-Unit will
0h wait before it enters Dynamic Self-Refresh mode when idle (in 16x DRAM Clocks).
15:0
RW Note: The value in this field needs to be minimum of 4 in functional mode and
minimum of 50 in PSMI mode.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS): Setting this bit to 0 allows
majority of the repeaters between D-Unit and PHY to clock gate when there is no
activity in order to save power.
0h
29 • 0 - Enable Repeaters clock gating.
RW
• 1 - Disable Repeaters clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS): Setting this bit to 0
enables the clock gating of IOSF-SB End Points in D-Unit and CPGC when there is no
IOSF-SB activity in order to save power.
1h
28 • 0 - Enable IOSF-SB EP clock gating.
RW
• 1 - Disable IOSF-SB clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power. When
set to 1, D-Unit clockgating is disabled.
0h
27 • 0: Enable.
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
0h Partial Array Self-Refresh Segment Mask (PASR): This is the Segment Mask used
23:16
RW for the MRW to enable PASR during SUSPENDP (Partial Array Self Refresh entry).
0h Page Close Timeout Period (PCLSTO): Specifies the time from the last access of a
15:8 DRAM page until that page is scheduled to close by sending a Precharge command to
RW DRAM (in 16 x DRAM clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
0h the DRAM page when idle.
7
RW • 0: Enable page close timer.
• 1: Disable page close timer (Used during DRAM init and DDRIO training).
0h
6 Reserved (RSVD6): Reserved
RO
Low Power Mode Opcode (LPMODEOP): D-Unit will send the value in this register
0h after it has entered Powerdown Mode and has stopped/tristated the clock. 00: Disable
2:1
RW LPMode. Note: LPMODE entry is not possible when global tristate flow is disabled
(DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0 for
normal operation.
0h • 0: The D-Unit dynamically controls the CKE pins to place the DRAM devices in
0
RW Power Down mode and bring them out of Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the DRAM devices from
entering Power Down mode when ranks are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior on
SR entry/exit.
0h
24:22 Reserved (RSVD24_22): Reserved
RO
Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:
0h
21 • 0: D-Unit sends all postponed REF commands to DRAM before it enters Self
RW
Refresh.
• 1: D-Unit enters SR without clearing the Refresh Debt (for Debug only).
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h
17:16 Reserved (RSVD17_16): Reserved
RO
0h Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit adds one extra
15
RW refresh debit (for a total of two) on Self-refresh exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Stop issuing refresh commands and accumulating refresh debits. (does not
stop tREFI counter).
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h
14:12 • 010: 0.5x refresh rate (i.e. 2x tREFI).
RW
• 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh counter per rank is
7h greater than this value, the D-Unit will send a REF command to the rank regardless of
11:8 pending requests. Note: REFWMPNC must be greater than or equal to REFWMHI and
RW greater than 2, Max Value must be less than 8 to not violate 9xtREFI JEDEC
requirement.
Refresh High Watermark (REFWMHI): When the Refresh counter per rank is
5h greater than this value, the D-Unit will send a REF command to the rank if there is no
7:4
RW critical priority requests in the pending queues. Note: Value must be greater or equal
to 1 and less than or equal to REFWMPNC.
0h
3:1 Reserved (RSVD3_1): Reserved
RO
0h • 0: D-Unit will send a REF command only if there is no pending request to that
0 rank.
RW
• 1: D-Unit will not send any opportunistic refreshes. Refresh commands are only
sent when the refresh counter is greater than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.
0h Early Write DQ Enable (EARLY_DQ_EN): Enables D-unit to send the write data to
31 the PHY one clock earlier than WL value (WL - 1). Note: Applicable to DDR3L and DDR4
RW only.
1Ch Write Pending Queue Count (WPQCOUNT): Used to limit the number of available
26:21 slots in Write Pending Queue/ Write Data Buffer. WPQCOUNT will only recognize
RW changes when PMI ISM is not active.
10h Read Pending Queue Count (RPQCOUNT): Used to limit the number of entries in
20:16 Read Pending Queue. RPQCOUNT will only recognize changes when PMI ISM is not
RW active.
0h
15 Reserved (RSVD15): Reserved
RO
Idle Bypass Mode Enable (BYPASSEN): When set new page hit/empty read
0h requests will bypass D-Unit pipeline stages to save latency 0 - Disable Idle Bypass 1 -
7
RW Enable Idle Bypass Note: Only applies to WIO2, this bit is reserved for other
technologies
0h Block When RDB Full (BLKRDBF): When set D-Unit stops scheduling new read
6
RW commands to DRAM when the read data buffer (RDB) is full.
0h
28:23 Reserved (RSVD28_23): Reserved
RO
0h
20:18 Reserved (RSVD20_18): Reserved
RO
0h
15:14 Reserved (RSVD15_14): Reserved
RO
1057h ZQ Calibration Interval (ZQINT): Specifies the time interval between two ZQCS
13:0 (LPDDR3/DDR3L/DDR4) or ZQ Start (LPDDR4) commands to a DRAM device. (in RTC
RW 32.8KHz clocks)
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h MR Value 2 (MR_VALUE2): MR3 Shadow Register (DDR4): BIOS writes the correct
29:16 value of MR3 register in DDR4 into this field at boot time. D-Unit modifies one bit and
RW rewrites the MR3 into DDR4 to enter and exit MPR mode.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
MR Value (MR_VALUE): MR3 Shadow Register (WIO2): BIOS sets the value of this
field at boot time based on the DRAM device configuration. D-Unit merges the value in
MR3_THERM_OFFSET with this field and writes the result into DRAM MR3 MR2 Shadow
0h Register (DDR3L): BIOS writes the correct value of MR2 register in DDR3L into this
13:0
RW field at boot time. D-Unit modifies one bit and rewrites the MR2 into DDR3L DRAM
before SR entry. MR4 Shadow Register (DDR4): BIOS writes the correct value of MR4
register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the
MR4 into DDR4 DRAM after temperature read out.
0h
30:12 Reserved (RSVD30_12): Reserved
RO
0h
11:0 VNN Timer Time (VNN_TIMER_TIME): The final timer value (in 16 x DRAM clocks).
RW
3h TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value will remain zero. This
31:29 field contains the data of the last temperature sensor read from Rank 1 DRAM Mode
RW/V Register. It is overwritten with each command.
3h TQ Data Rank 0 (TQDATAR0): This field contains the data of the last temperature
28:26
RW/V sensor read from Rank 0 DRAM Mode Register. It is overwritten with each command.
0h
25:22 Reserved (RSVD25_22): Reserved
RO
0h TQ Poll Period (TQPOLLPER): This sets the frequency by which the D-Unit initiates
21:8 RW temperature sensor read from DRAM mode register to determine required refresh rate
(in 4x tREFI units).
Self Refresh Temperature Range Enable (DDR3 Only) (SRTEN): When set,
0h before every Self refresh entry, D-Unit writes a 1 to bit 7 of MR_SHADOW.MR_VALUE
4
RW when TQDATA for that rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3 for each enabled rank.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-Unit pushes the data
2
RW form the last temperature sensor read to a punit register.
0h Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic TQ Poll. If disabled,
0
RW D-Unit will not read the DRAM's temperature sensor value periodically.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
0h
15:11 Reserved (RSVD15_11): Reserved
RO
0h MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to TQDATA read from
10:8
RW MR4 the resulting value is used to control refresh rate and AC timing derating.
0h
7:3 Reserved (RSVD7_3): Reserved
RO
0h MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-Unit writes the merged
2 value of MR3_VALUE and MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this
RW/V bit once the value is written.
Initialization Complete (IC): Indicates that initialization of the D-Unit has been
completed. Memory accesses are permitted and maintenance operation begins. Until
0h this bit is set to a 1, the memory controller will not accept DRAM requests from the
31
RW/V Bunit/GSA/2LM (PMI ISMs will not leave idle). Note: Set this bit to 1 only when all
other D-Unit registers have been configured. Usually set at the last configuration step
by BIOS on cold/warm reset. D-Unit hardware sets this bit on SR exit.
0h DDRIO PHY Initialization Complete (DIOIC): Status indication that the DDRIO
30
RO/V PHY initialization is complete reflects the status spid_init_complete signal.
0h
29 Reserved (RSVD29): Reserved
RO
0h
27:8 Reserved (RSVD27_8): Reserved
RO
0h
7:4 Reserved (RSVD7_4): Reserved
RO
Enable PSMI Mode (PSMIEN): When enabled, D-Unit will synchronize clock crossing
signals.
0h
3 • 0: PSMI Mode is disabled.
RW
• 1: PSMI Mode is enabled.
Note: Change only allowed when D-Unit is idle.
0h
0 Reserved (RSVD0): Reserved
RO
0h
30 Reserved (RSVD30): Reserved
RO
Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
0h • 00: Clock gate disabled.
29:28
RW • 01: Clock Gate every 2 cycles.
• 10: Clock Gate every 3 cycles.
• 11: Clock Gate every 4 cycles.
0h
27:16 Reserved (RSVD27_16): Reserved
RO
0h Scrambling Key (KEY): Sets the key for the scrambler. The key should be a random
15:0
RW value that is set following each cold boot.
0h
31 Reserved (RSVD31): Reserved
RO
0h Error Injection Target Address (ADDRESS): Specifies the PMI address of the write
30:1 transaction to be injected with the error. Only applicable to Write transactions. Read/
RW under-fill read of the partial write operation is not affected.
0h
0 Reserved (RSVD0): Reserved
RO
0h
31:4 Reserved (RSVD31_4): Reserved
RO
Error Injection Type Higher 32B (SEL_HI): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
3 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Higher 32B (EN_HI): When set the error injection is
2 continuously armed for higher 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
1 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Lower 32B (EN_LO): When set, the error injection is
0 continuously armed for lower 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
0h
31 CLEAR: Setting this bit to one clears all fields in this register, including itself.
RW/V
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a correctable single-bit
0h error occurs on a memory read data transfer. When this bit is set, the address that
28 caused the error and the error syndrome are also logged and they are locked to further
RW/V single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is
set will override the address/error syndrome information.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of the error within a
26:25
RW/V chunk.
0h Error Chunk Number (ERR_CHUNK): Chunk number of the error. 0 - lower 32B
24 chunk has error if MERR/CERR is set 1 - higher 32B chunk has the error if MERR/CERR
RW/V is set
0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome for a QW (64 bit)
23:16
RW/V within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI Request Tag which
15:0
RW/V triggered the error log.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
D-Unit Fuse Status (FUSESTAT): D-Unit fuse bits are captured into this register and
are available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V • [5:5]: fus_dun_lpddr4_dis.
• [6:6]: fus_dun_wio2_dis.
• [7:7]: fus_dun_ddr3l_dis.
• [8:8]: fus_dun_ddr4_dis.
• [15:9]: reserved.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
RAW Conflict Read Priority for WMM Transition (RAW_WMM): If a conflict read
5h reaches this priority (or greater depending on access class occupancy), WMM will be
29:27 triggered to unblock the corresponding write. D-Unit will stay in WMM until
RW corresponding write is issued. Note: The value in this bit must not be higher than
lowest terminal priority level of each access class.
0h
26 Reserved (RSVD26): Reserved
RO
6h Read Isoch Trigger Priority (RIMPRIO): If any read in the RPQ is at this
25:23
RW programmable priority, RIM is triggered.
0h
22:18 Reserved (RSVD22_18): Reserved
RO
1Ah Write Isoch Threshold (WIMTHRS): When the number of entries in WPQ is greater
17:12 than or equal to this value (higher than WMM entry watermark, less than WPQ size), it
RW triggers write isoch mode (WIM).
14h Write Major Mode Exit Watermark (WMMEXIT): When the number of entries in
11:6
RW WPQ is less than this value, the D-Unit will switch back to read major mode.
18h Write Major Mode Entry Watermark (WMMENTRY): When the number of entries
5:0 in WPQ is greater than or equal to this value, the D-Unit will switch to write major
RW mode (WMM). Note: the value must not be set to 0.
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes B (MAXWRB): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set B).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes A (MAXWRA): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set A).
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes D (MAXWRD): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set D).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes C (MAXWRC): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set C).
0h
31:15 Reserved (RSVD31_15): Reserved
RO
1h Access Class 4 Initial Priority (AC4IP): Initial priority level of read requests
14:12
RW coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of read requests
11:9
RW coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of read requests
8:6
RW coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of read requests
5:3
RW coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of read requests
2:0
RW coming with access class 0.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Ah Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:11 Reserved (RSVD31_11): Reserved
RO
0h
31:25 Reserved (RSVD31_25): Reserved
RO
0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe write page hits block
24
RW safe write page misses same bank.
0h
23:20 Reserved (RSVD23_20): Reserved
RO
WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe priority 1 read miss
0h block write hit to same bank. Note: This rule does not block the bank that is being
19
RW blocked by WMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe priority 1 write hit
0h block write miss to same bank. Note: This rule does not block the bank that is being
18
RW blocked by WMM_PRIO_R1. Priority rules 1,3 and 4 should be enabled/disabled
together.
0h
17 WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS block rule.
RW
0h WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe top priority 1 write
16 miss block write hit same bank. Priority rules 1, 3 and 4 should be enabled/disabled
RW together.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe write page hits block
13
RW safe write page misses same bank.
1h RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe read page miss block
12 all safe and unsafe write page hit to the same bank. Note: This field must not be set to
RW 0 (enabled) if RMM_REG_R4 is also 0.
1h RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe write page hit block
11 safe read page miss same bank. Note: This field must not be set to 0 (enabled) if
RW RMM_REG_R5 is also 0.
0h RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe read page hit block safe
10 read and write page miss same bank. Note: This rule does not block the bank that is
RW being blocked by RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe read page empty block
9
RW safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe read page hit block safe
8
RW write page hit same rank.
0h
7:4 Reserved (RSVD7_4): Reserved
RO
RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe critical read miss block
0h read and write hit to same bank. Note: This rule does not block the bank that is being
3
RW blocked by RMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe critical read hit block
0h read and write miss to same bank. Note: This rule does not block the bank that is being
2
RW blocked by RMM_PRIO_R1. Priority rules 1, 3 and 4 should be enabled/disabled
together.
0h
1 RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block rule.
RW
0h RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe top critical read miss
0 block read and write hit same bank. Note: Priority rules 1, 3 and 4 should be enabled/
RW disabled together.
0h
31:4 Reserved (RSVD31_4): Reserved
RO
SUSPENDP: A SUSPENDP message will put the DRAM into self-refresh mode. The D-
Unit will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in self refresh mode. Finally, a PM
3 message will be sent to the PHY. The bit is cleared by hardware after the PHY indicates
RW/V the transition requested in the PM message has been completed. D-Unit will perform an
MRW to MR17 with an opcode as defined by DPMC0.PASR before it places the DRAM
into Self-Refresh.
SUSPEND: A SUSPEND message will put the DRAM into self-refresh mode. The D-Unit
will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in Self Refresh mode. Finally, a PM
2
RW/V message will be sent to the PHY. The bit is cleared by hardware only after the PHY
indicates the transition requested in the PM message has been completed. Note: When
COLDWAKE is set prior of setting this bit the DRAM will not be placed in SR.
0h
1 Reserved (RSVD1): Reserved
RO
WAKE: Take PHY out of PM states and wakes the DRAM out of self refresh mode. The
0h bit is cleared by hardware only when the DRAM has exited out of self refresh mode and
0
RW/V is accessible. Note: When COLDWAKE is set prior of setting this bit the D-Unit will not
send SR exit command and will not set the DCO.IC bit.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts DQS oscillator, it must
0h wait this amount of time before being able to read the value in MR18 and MR19 (in 16x
13:4
RW DRAM clocks). Value in this register must be at least equal to DRAM's MR23 value. +
tOSCO.
0h
31 Reserved (RSVD31): Reserved
RO
0h
30:28 MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of MR4 data.
RW
0h
27 Reserved (RSVD27): Reserved
RO
0h
26:24 MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of MR4 data
RW
0h
23 Reserved (RSVD23): Reserved
RO
0h
22:20 MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of MR4 data.
RW
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of the MR4 data for
17:16
RW second device.
0h
15 Reserved (RSVD15): Reserved
RO
0h
14:12 MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW
0h
11 Reserved (RSVD11): Reserved
RO
0h
10:8 MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW
0h
7 Reserved (RSVD7): Reserved
RO
0h
6:4 MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW
0h
3:2 Reserved (RSVD3_2): Reserved
RO
0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of the MR4 data first
1:0
RW device.
0h
18:17 Reserved (RSVD18_17): Reserved
RO
Fine Bank Group Interleaving Enable (FBGINTEN): When enabled, D-unit will use
a lower order address bit in the bank hashing function (DDR4 Only).
0h
16 • 0: Bank Group Interleave disabled.
RW
• 1: Bank Group Interleave enabled.
Note: BAHEN must be set for this bit to take effect.
0h
13:9 Reserved (RSVD13_9): Reserved
RO
DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h
8:6 • 010: 8 Gb.
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.
DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
0h • 00: x8.
5:4
RW • 01: x16.
• 10: x32.
• 11: x64.
0h
3 Reserved (RSVD3): Reserved
RO
0h
1 Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to enable use of this rank.
RW
0h Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to enable use of this rank.
0
RW Note: Setting this bit to 0 is not a functional mode.
0h
31:23 Reserved (RSVD31_23): Reserved
RO
5h Write to Write DQ Delay Same Bank Group Same Rank (TWWSR_L): Specifies
22:18 the delay from a DRAM Write to another Write command within the same bank group of
RW the same rank (in DRAM clocks). DDR4 Equation: tWWSR_L = tCCD_L.
5h Read to Read DQ Delay Same Bank Group Same Rank (TRRSR_L): Specifies the
17:13 delay from a DRAM Read to another Read command within the same bank group of the
RW same rank (in DRAM clocks). DDR4 Equation: tRRSR_L = tCCD_L.
Write to Read DQ Delay Same Bank Group Same Rank (TWRSR_L): Specifies
15h the delay from a DRAM Read to Write command within the same bank group of the
12:6 same rank (in DRAM clocks).
RW
• DDR4 Equation: tWRSR_L = CWL + tDQSSmax + BL/2 + tWPST + tWTR_L.
Bh Activate RAS to CAS Command Delay [tRCD] (TRCD): Specifies the delay
11:6 between a DRAM Activate command and a DRAM Read or Write command to the same
RW bank (in DRAM clocks). Note: Derating adds 1.875ns to this timing.
Exit Power Down to Next Command Delay [tXP] (TXP): Specifies the delay from
6h the DRAM Power Down Exit (PDX) command to any valid command (in DRAM clocks).
31:27
RW Note: The value in this field must be programmed to tXPDLL when Slow Exit Mode
Power-down is enabled for DDR3L.
0h
26 Reserved (RSVD26): Reserved
RO
18h ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay between the DRAM ZQ
5:0 RW Calibration Latch command and any DRAM command (in DRAM clocks). LPDDR4 only.
Not used in DDR3L/DDR4/LPDDR3/WIO2.
118h All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies the delay between the
31:22
RW REFab command to the next valid command. (in DRAM clocks)
0h
21 Reserved (RSVD21): Reserved
RO
4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the minimum time from CKEL
20:17
RW to CKEH (in DRAM clocks).
0h
16 Reserved (RSVD16): Reserved
RO
C30h Refresh Interval Time [tREFI] (NREFI): Specifies the average time between
15:0 refresh commands. JEDEC Base Refresh Interval time (in DRAM clocks). Note: D-Unit
RW will ignore the 2 LSBs of this field.
Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay between
the DRAM Read and Precharge commands to the same bank (in DRAM clocks).
6h • LPDDR3 Equation: = BL/2 + tRTP - 4.
31:27
RW • LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• WIO2 Equation: NA.
• DDR3L/DDR4 Equation: = tRTP.
CAS to CAS Command Delay Adder (TCCD_INC): Specifies the number of clocks
0h to be added to turnaround times (for Stretch Mode). It increases delay between Read
26:20
RW to Read or Read to Write commands by the amount programmed in this field (in 4 x
DRAM clocks).
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
1h • 0h: Reserved.
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L/DDR4 only. tCMD must be set to 1N for LPDDR3/LPDDR4/WIO2.
8h Write Latency [WL/CWL] (TCWL): The delay between the internal write command
10:6
RW and the availability of the first word of DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW + 8 (BL32).
5:0
RW • WIO2 Equation: NA.
Note: Masked Write operation in LPDDR4 is always BL16 and in WIO2 is always BL4.
D-Unit applies this timing for same rank as well as same bank, refer to D-Unit for more
details.
30h Four Bank Activate Window [tFAW] (TFAW): A rolling timeframe in which a
31:24 maximum of four Activate commands can be issued to the same rank. This is to limit
RW the peak current draw from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 - (RL + tDQSCKmin -
8h
23:18 tRPRE).
RW
• LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 - tDQSCKmin.
• DDR3L/DDR4 Equation: tWRDR = CWL + tDQSSmax + BL/2 - (CL + tDQSCKmin -
tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
9h
17:12 • LPDDR3/LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL - tWPRE).
RW
• DDR3L/DDR4 Equation: tRWDR = CL + tDQSCKmax + BL/2 - (CWL - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.
Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Write data burst of a different
rank (in DRAM clocks).
5h
11:6 • LPDDR3/DDR3L/DDR4 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
RW tWPRE.
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
9h start of a Read data burst of one rank to the Start of a Read data burst of a different
5:0 rank (in DRAM clocks).
RW
• Equation: tRRDR = BL/2 + tDQSCKmax - tDQSCKmin + tRPRE.
Row Activation to Row Activation Delay [tRRD] (TRRD): Specifies the minimum
6h delay in DRAM clocks between two DRAM Activate commands to the same rank but
31:27
RW different banks (tRC is the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.
0h
26 Reserved (RSVD26): Reserved
RO
10h Write to Write DQ Delay Same Rank (TWWSR): Specifies the delay from a DRAM
22:18 Write to another Write command of the same rank (in DRAM clocks). Equation: tWWSR
RW = tCCD.
10h Read to Read DQ Delay Same Rank (TRRSR): Specifies the delay from a DRAM
17:13 Read to another Read command of the same rank (in DRAM clocks). Equation: tRRSR =
RW tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).
3h
12:6 • LPDDR3/LPDDR4/WIO2 Equation: tWRSR = WL + tDQSSmax + BL/2 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR.
• DDR4 Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR_S.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle period that defines an
31:24
RW opportunity for refresh (in DRAM clocks).
0h
18:15 Reserved (RSVD18_15): Reserved
RW
Mode Register Read to Any Command Delay (TPSTMRRBLK): Specifies the quiet
time after issuing MRR command (in DRAM Clocks). This is the channel block time for
0h the MR19 command issued as part of LPDDR4 DQS Retraining flow. For all other MR
14:8 commands this is the rank block time. Note: D-Unit treats MRR as a read and always
RW applies relevant turnaround times, any value programmed in this CR must be greater
than those turnaround times for D-Unit to enforce any additional time from MRR to the
next read/write.
0h
7 Reserved (RSVD7): Reserved
RO
All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies the
delay between a DRAM Precharge All Bank command and a DRAM Activate command
3h (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4 in LP3 and
31:26 minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L, DDR4 and WIO2 8ch tRPpb = tRPab = tRP.
0h
8:7 Reserved (RSVD8_7): Reserved
RO
6h Row Activation Period [tRAS] (TRAS): Specifies the minimum delay between the
6:0 DRAM Activate and Precharge commands to the same bank (in DRAM clocks). Note:
RW Derating adds 1.875ns to this timing.
6h Minimum Low Power Mode Residency (LPMDRES): Specifies the minimum time
25:21
RW that PHY should remain in LPMode (in DRAM clocks).
Low Power Mode Exit to Clock Enable Delay (LPMDTOCKEDLY): Specifies the
Ah minimum time between the LP Mode exit to the CK stop/tristate deassertion and
20:15
RW powerdown exit (in DRAM clocks). Note: Must be equal to t_idle_latency published in
the DDRIO PHY and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY): Specifies the time
Ah between CK stop/tristate to the Low Power Mode entry. This timing parameter is used
14:8
RW to delay Low Power Mode entry (in DRAM clocks). Note: Must be at least equal to
t_idle_length parameter published in the DDRIO PHY and less than 0x7C.
18h Power Down Idle Timer (PWDDLY): This is a non-JEDEC timing parameter used to
7:0
RW delay powerdown entry (in DRAM clocks).
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Rank 1 Read ODT Control (R1RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 1. 0 - Read ODT is disabled for Rank 1 1 -
29
RW Assert ODT to for Rank 0 (non-targeted Rank) Note: This register should be set to 0 for
LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 0. 0 - Read ODT is disabled for Rank 0 1 -
28
RW Assert ODT to for Rank 1 (non-targeted Rank) Note: This register is reserved for
LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 1. 00 - Write ODT is disabled 01 - Assert ODT
27:26
RW to Rank 0 (non-targeted Rank) 10 - Assert ODT to Rank 1 (targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
Rank 0 Write ODT Control (R0WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 0. 00 - Write ODT is disabled 01 - Assert ODT
25:24
RW to Rank 0 (targeted Rank) 10 - Assert ODT to Rank 1 (non-targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
0h
23:18 Reserved (RSVD23_18): Reserved
RO
0h
13 Reserved (RSVD13): Reserved
RO
0h
4 Reserved (RSVD4): Reserved
RO
0h
31:29 Reserved (RSVD31_29): Reserved
RO
0h
23 Reserved (RSVD23): Reserved
RO
PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to deassert
before sending a PM message on SR entry.
0h
22 • 0: D-Unit will not wait for SPID_clk to deassert before sending the PM message to
RW PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.
Self-Refresh Entry Delay (SREDLY): Specifies the minimum time the D-Unit will
0h wait before it enters Dynamic Self-Refresh mode when idle (in 16x DRAM Clocks).
15:0
RW Note: The value in this field needs to be minimum of 4 in functional mode and
minimum of 50 in PSMI mode.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS): Setting this bit to 0 allows
majority of the repeaters between D-Unit and PHY to clock gate when there is no
activity in order to save power.
0h
29 • 0 - Enable Repeaters clock gating.
RW
• 1 - Disable Repeaters clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS): Setting this bit to 0
enables the clock gating of IOSF-SB End Points in D-Unit and CPGC when there is no
IOSF-SB activity in order to save power.
1h
28 • 0 - Enable IOSF-SB EP clock gating.
RW
• 1 - Disable IOSF-SB clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power. When
set to 1, D-Unit clockgating is disabled.
0h
27 • 0: Enable.
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
0h Partial Array Self-Refresh Segment Mask (PASR): This is the Segment Mask used
23:16
RW for the MRW to enable PASR during SUSPENDP (Partial Array Self Refresh entry).
0h Page Close Timeout Period (PCLSTO): Specifies the time from the last access of a
15:8 DRAM page until that page is scheduled to close by sending a Precharge command to
RW DRAM (in 16 x DRAM clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
0h the DRAM page when idle.
7
RW • 0: Enable page close timer.
• 1: Disable page close timer (Used during DRAM init and DDRIO training).
0h
6 Reserved (RSVD6): Reserved
RO
Low Power Mode Opcode (LPMODEOP): D-Unit will send the value in this register
0h after it has entered Powerdown Mode and has stopped/tristated the clock. 00: Disable
2:1
RW LPMode. Note: LPMODE entry is not possible when global tristate flow is disabled
(DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0 for
normal operation.
0h • 0: The D-Unit dynamically controls the CKE pins to place the DRAM devices in
0
RW Power Down mode and bring them out of Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the DRAM devices from
entering Power Down mode when ranks are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior on
SR entry/exit.
0h
24:22 Reserved (RSVD24_22): Reserved
RO
Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:
0h
21 • 0: D-Unit sends all postponed REF commands to DRAM before it enters Self
RW
Refresh.
• 1: D-Unit enters SR without clearing the Refresh Debt (for Debug only).
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h
17:16 Reserved (RSVD17_16): Reserved
RO
0h Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit adds one extra
15
RW refresh debit (for a total of two) on Self-refresh exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Stop issuing refresh commands and accumulating refresh debits. (does not
stop tREFI counter).
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h
14:12 • 010: 0.5x refresh rate (i.e. 2x tREFI).
RW
• 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh counter per rank is
7h greater than this value, the D-Unit will send a REF command to the rank regardless of
11:8 pending requests. Note: REFWMPNC must be greater than or equal to REFWMHI and
RW greater than 2, Max Value must be less than 8 to not violate 9xtREFI JEDEC
requirement.
Refresh High Watermark (REFWMHI): When the Refresh counter per rank is
5h greater than this value, the D-Unit will send a REF command to the rank if there is no
7:4
RW critical priority requests in the pending queues. Note: Value must be greater or equal
to 1 and less than or equal to REFWMPNC.
0h
3:1 Reserved (RSVD3_1): Reserved
RO
0h • 0: D-Unit will send a REF command only if there is no pending request to that
0 rank.
RW
• 1: D-Unit will not send any opportunistic refreshes. Refresh commands are only
sent when the refresh counter is greater than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.
0h Early Write DQ Enable (EARLY_DQ_EN): Enables D-unit to send the write data to
31 the PHY one clock earlier than WL value (WL - 1). Note: Applicable to DDR3L and DDR4
RW only.
1Ch Write Pending Queue Count (WPQCOUNT): Used to limit the number of available
26:21 slots in Write Pending Queue/ Write Data Buffer. WPQCOUNT will only recognize
RW changes when PMI ISM is not active.
10h Read Pending Queue Count (RPQCOUNT): Used to limit the number of entries in
20:16 Read Pending Queue. RPQCOUNT will only recognize changes when PMI ISM is not
RW active.
0h
15 Reserved (RSVD15): Reserved
RO
Idle Bypass Mode Enable (BYPASSEN): When set new page hit/empty read
0h requests will bypass D-Unit pipeline stages to save latency 0 - Disable Idle Bypass 1 -
7
RW Enable Idle Bypass Note: Only applies to WIO2, this bit is reserved for other
technologies
0h Block When RDB Full (BLKRDBF): When set D-Unit stops scheduling new read
6
RW commands to DRAM when the read data buffer (RDB) is full.
0h
28:23 Reserved (RSVD28_23): Reserved
RO
0h
20:18 Reserved (RSVD20_18): Reserved
RO
0h
15:14 Reserved (RSVD15_14): Reserved
RO
1057h ZQ Calibration Interval (ZQINT): Specifies the time interval between two ZQCS
13:0 (LPDDR3/DDR3L/DDR4) or ZQ Start (LPDDR4) commands to a DRAM device. (in RTC
RW 32.8KHz clocks)
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h MR Value 2 (MR_VALUE2): MR3 Shadow Register (DDR4): BIOS writes the correct
29:16 value of MR3 register in DDR4 into this field at boot time. D-Unit modifies one bit and
RW rewrites the MR3 into DDR4 to enter and exit MPR mode.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
MR Value (MR_VALUE): MR3 Shadow Register (WIO2): BIOS sets the value of this
field at boot time based on the DRAM device configuration. D-Unit merges the value in
MR3_THERM_OFFSET with this field and writes the result into DRAM MR3 MR2 Shadow
0h Register (DDR3L): BIOS writes the correct value of MR2 register in DDR3L into this
13:0
RW field at boot time. D-Unit modifies one bit and rewrites the MR2 into DDR3L DRAM
before SR entry. MR4 Shadow Register (DDR4): BIOS writes the correct value of MR4
register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the
MR4 into DDR4 DRAM after temperature read out.
0h
30:12 Reserved (RSVD30_12): Reserved
RO
0h
11:0 VNN Timer Time (VNN_TIMER_TIME): The final timer value (in 16 x DRAM clocks).
RW
3h TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value will remain zero. This
31:29 field contains the data of the last temperature sensor read from Rank 1 DRAM Mode
RW/V Register. It is overwritten with each command.
3h TQ Data Rank 0 (TQDATAR0): This field contains the data of the last temperature
28:26
RW/V sensor read from Rank 0 DRAM Mode Register. It is overwritten with each command.
0h
25:22 Reserved (RSVD25_22): Reserved
RO
0h TQ Poll Period (TQPOLLPER): This sets the frequency by which the D-Unit initiates
21:8 temperature sensor read from DRAM mode register to determine required refresh rate
RW (in 4x tREFI units).
Self Refresh Temperature Range Enable (DDR3 Only) (SRTEN): When set,
0h before every Self refresh entry, D-Unit writes a 1 to bit 7 of MR_SHADOW.MR_VALUE
4
RW when TQDATA for that rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3 for each enabled rank.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-Unit pushes the data
2
RW form the last temperature sensor read to a punit register.
0h Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic TQ Poll. If disabled,
0
RW D-Unit will not read the DRAM's temperature sensor value periodically.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
0h
15:11 Reserved (RSVD15_11): Reserved
RO
0h MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to TQDATA read from
10:8
RW MR4 the resulting value is used to control refresh rate and AC timing derating.
0h
7:3 Reserved (RSVD7_3): Reserved
RO
0h MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-Unit writes the merged
2 value of MR3_VALUE and MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this
RW/V bit once the value is written.
Initialization Complete (IC): Indicates that initialization of the D-Unit has been
completed. Memory accesses are permitted and maintenance operation begins. Until
0h this bit is set to a 1, the memory controller will not accept DRAM requests from the
31
RW/V Bunit/GSA/2LM (PMI ISMs will not leave idle). Note: Set this bit to 1 only when all
other D-Unit registers have been configured. Usually set at the last configuration step
by BIOS on cold/warm reset. D-Unit hardware sets this bit on SR exit.
0h DDRIO PHY Initialization Complete (DIOIC): Status indication that the DDRIO
30
RO/V PHY initialization is complete reflects the status spid_init_complete signal.
0h
29 Reserved (RSVD29): Reserved
RO
0h
27:8 Reserved (RSVD27_8): Reserved
RO
0h
7:4 Reserved (RSVD7_4): Reserved
RO
Enable PSMI Mode (PSMIEN): When enabled, D-Unit will synchronize clock crossing
signals.
0h
3 • 0: PSMI Mode is disabled.
RW
• 1: PSMI Mode is enabled.
Note: Change only allowed when D-Unit is idle.
0h
0 Reserved (RSVD0): Reserved
RO
0h
30 Reserved (RSVD30): Reserved
RO
Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
0h • 00: Clock gate disabled.
29:28
RW • 01: Clock Gate every 2 cycles.
• 10: Clock Gate every 3 cycles.
• 11: Clock Gate every 4 cycles.
0h
27:16 Reserved (RSVD27_16): Reserved
RO
0h Scrambling Key (KEY): Sets the key for the scrambler. The key should be a random
15:0
RW value that is set following each cold boot.
0h
31 Reserved (RSVD31): Reserved
RO
0h Error Injection Target Address (ADDRESS): Specifies the PMI address of the write
30:1 transaction to be injected with the error. Only applicable to Write transactions. Read/
RW under-fill read of the partial write operation is not affected.
0h
0 Reserved (RSVD0): Reserved
RO
0h
31:4 Reserved (RSVD31_4): Reserved
RO
Error Injection Type Higher 32B (SEL_HI): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
3 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Higher 32B (EN_HI): When set the error injection is
2 continuously armed for higher 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
1 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Lower 32B (EN_LO): When set, the error injection is
0 continuously armed for lower 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
0h
31 CLEAR: Setting this bit to one clears all fields in this register, including itself.
RW/V
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a correctable single-bit
0h error occurs on a memory read data transfer. When this bit is set, the address that
28 caused the error and the error syndrome are also logged and they are locked to further
RW/V single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is
set will override the address/error syndrome information.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of the error within a
26:25
RW/V chunk.
0h Error Chunk Number (ERR_CHUNK): Chunk number of the error. 0 - lower 32B
24 chunk has error if MERR/CERR is set 1 - higher 32B chunk has the error if MERR/CERR
RW/V is set
0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome for a QW (64 bit)
23:16
RW/V within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI Request Tag which
15:0
RW/V triggered the error log.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
D-Unit Fuse Status (FUSESTAT): D-Unit fuse bits are captured into this register and
are available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V • [5:5]: fus_dun_lpddr4_dis.
• [6:6]: fus_dun_wio2_dis.
• [7:7]: fus_dun_ddr3l_dis.
• [8:8]: fus_dun_ddr4_dis.
• [15:9]: reserved.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
RAW Conflict Read Priority for WMM Transition (RAW_WMM): If a conflict read
5h reaches this priority (or greater depending on access class occupancy), WMM will be
29:27 triggered to unblock the corresponding write. D-Unit will stay in WMM until
RW corresponding write is issued. Note: The value in this bit must not be higher than
lowest terminal priority level of each access class.
0h
26 Reserved (RSVD26): Reserved
RO
6h Read Isoch Trigger Priority (RIMPRIO): If any read in the RPQ is at this
25:23
RW programmable priority, RIM is triggered.
0h
22:18 Reserved (RSVD22_18): Reserved
RO
1Ah Write Isoch Threshold (WIMTHRS): When the number of entries in WPQ is greater
17:12 RW than or equal to this value (higher than WMM entry watermark, less than WPQ size), it
triggers write isoch mode (WIM).
14h Write Major Mode Exit Watermark (WMMEXIT): When the number of entries in
11:6
RW WPQ is less than this value, the D-Unit will switch back to read major mode.
18h Write Major Mode Entry Watermark (WMMENTRY): When the number of entries
5:0 in WPQ is greater than or equal to this value, the D-Unit will switch to write major
RW mode (WMM). Note: the value must not be set to 0.
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes B (MAXWRB): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set B).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes A (MAXWRA): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set A).
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes D (MAXWRD): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set D).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes C (MAXWRC): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set C).
0h
31:15 Reserved (RSVD31_15): Reserved
RO
1h Access Class 4 Initial Priority (AC4IP): Initial priority level of read requests
14:12
RW coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of read requests
11:9
RW coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of read requests
8:6
RW coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of read requests
5:3
RW coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of read requests
2:0
RW coming with access class 0.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Ah Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h
Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
priority promotes to the next priority level.
RW
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:11 Reserved (RSVD31_11): Reserved
RO
0h
31:25 Reserved (RSVD31_25): Reserved
RO
0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe write page hits block
24
RW safe write page misses same bank.
0h
23:20 Reserved (RSVD23_20): Reserved
RO
WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe priority 1 read miss
0h block write hit to same bank. Note: This rule does not block the bank that is being
19
RW blocked by WMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe priority 1 write hit
0h block write miss to same bank. Note: This rule does not block the bank that is being
18
RW blocked by WMM_PRIO_R1. Priority rules 1,3 and 4 should be enabled/disabled
together.
0h
17 WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS block rule.
RW
0h WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe top priority 1 write
16 miss block write hit same bank. Priority rules 1, 3 and 4 should be enabled/disabled
RW together.
0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe write page hits block
13
RW safe write page misses same bank.
1h RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe read page miss block
12 all safe and unsafe write page hit to the same bank. Note: This field must not be set to
RW 0 (enabled) if RMM_REG_R4 is also 0.
1h RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe write page hit block
11 safe read page miss same bank. Note: This field must not be set to 0 (enabled) if
RW RMM_REG_R5 is also 0.
0h RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe read page hit block safe
10 read and write page miss same bank. Note: This rule does not block the bank that is
RW being blocked by RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe read page empty block
9
RW safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe read page hit block safe
8
RW write page hit same rank.
0h
7:4 Reserved (RSVD7_4): Reserved
RO
RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe critical read miss block
0h read and write hit to same bank. Note: This rule does not block the bank that is being
3
RW blocked by RMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe critical read hit block
0h read and write miss to same bank. Note: This rule does not block the bank that is being
2
RW blocked by RMM_PRIO_R1. Priority rules 1, 3 and 4 should be enabled/disabled
together.
0h
1 RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block rule.
RW
0h RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe top critical read miss
0 block read and write hit same bank. Note: Priority rules 1, 3 and 4 should be enabled/
RW disabled together.
0h
31:4 Reserved (RSVD31_4): Reserved
RO
SUSPENDP: A SUSPENDP message will put the DRAM into self-refresh mode. The D-
Unit will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in self refresh mode. Finally, a PM
3 message will be sent to the PHY. The bit is cleared by hardware after the PHY indicates
RW/V the transition requested in the PM message has been completed. D-Unit will perform an
MRW to MR17 with an opcode as defined by DPMC0.PASR before it places the DRAM
into Self-Refresh.
SUSPEND: A SUSPEND message will put the DRAM into self-refresh mode. The D-Unit
will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in Self Refresh mode. Finally, a PM
2
RW/V message will be sent to the PHY. The bit is cleared by hardware only after the PHY
indicates the transition requested in the PM message has been completed. Note: When
COLDWAKE is set prior of setting this bit the DRAM will not be placed in SR.
0h
1 Reserved (RSVD1): Reserved
RO
WAKE: Take PHY out of PM states and wakes the DRAM out of self refresh mode. The
0h bit is cleared by hardware only when the DRAM has exited out of self refresh mode and
0
RW/V is accessible. Note: When COLDWAKE is set prior of setting this bit the D-Unit will not
send SR exit command and will not set the DCO.IC bit.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts DQS oscillator, it must
0h wait this amount of time before being able to read the value in MR18 and MR19 (in 16x
13:4
RW DRAM clocks). Value in this register must be at least equal to DRAM's MR23 value. +
tOSCO.
0h
31 Reserved (RSVD31): Reserved
RO
0h
30:28 MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of MR4 data.
RW
0h
27 Reserved (RSVD27): Reserved
RO
0h
26:24 MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of MR4 data
RW
0h
23 Reserved (RSVD23): Reserved
RO
0h
22:20 MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of MR4 data.
RW
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of the MR4 data for
17:16
RW second device.
0h
15 Reserved (RSVD15): Reserved
RO
0h
14:12 MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW
0h
11 Reserved (RSVD11): Reserved
RO
0h
10:8 MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW
0h
7 Reserved (RSVD7): Reserved
RO
0h
6:4 MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW
0h
3:2 Reserved (RSVD3_2): Reserved
RO
0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of the MR4 data first
1:0
RW device.
0h
18:17 Reserved (RSVD18_17): Reserved
RO
Fine Bank Group Interleaving Enable (FBGINTEN): When enabled, D-unit will use
a lower order address bit in the bank hashing function (DDR4 Only).
0h
16 • 0: Bank Group Interleave disabled.
RW
• 1: Bank Group Interleave enabled.
Note: BAHEN must be set for this bit to take effect.
0h
13:9 Reserved (RSVD13_9): Reserved
RO
DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h
8:6 • 010: 8 Gb.
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.
DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
0h • 00: x8.
5:4
RW • 01: x16.
• 10: x32.
• 11: x64.
0h
3 Reserved (RSVD3): Reserved
RO
0h
1 Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to enable use of this rank.
RW
0h Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to enable use of this rank.
0
RW Note: Setting this bit to 0 is not a functional mode.
0h
31:23 Reserved (RSVD31_23): Reserved
RO
5h Write to Write DQ Delay Same Bank Group Same Rank (TWWSR_L): Specifies
22:18 the delay from a DRAM Write to another Write command within the same bank group of
RW the same rank (in DRAM clocks). DDR4 Equation: tWWSR_L = tCCD_L.
5h Read to Read DQ Delay Same Bank Group Same Rank (TRRSR_L): Specifies the
17:13 delay from a DRAM Read to another Read command within the same bank group of the
RW same rank (in DRAM clocks). DDR4 Equation: tRRSR_L = tCCD_L.
Write to Read DQ Delay Same Bank Group Same Rank (TWRSR_L): Specifies
15h the delay from a DRAM Read to Write command within the same bank group of the
12:6 same rank (in DRAM clocks).
RW
• DDR4 Equation: tWRSR_L = CWL + tDQSSmax + BL/2 + tWPST + tWTR_L.
Bh Activate RAS to CAS Command Delay [tRCD] (TRCD): Specifies the delay
11:6 between a DRAM Activate command and a DRAM Read or Write command to the same
RW bank (in DRAM clocks). Note: Derating adds 1.875ns to this timing.
Exit Power Down to Next Command Delay [tXP] (TXP): Specifies the delay from
6h the DRAM Power Down Exit (PDX) command to any valid command (in DRAM clocks).
31:27
RW Note: The value in this field must be programmed to tXPDLL when Slow Exit Mode
Power-down is enabled for DDR3L.
0h
26 Reserved (RSVD26): Reserved
RO
18h ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay between the DRAM ZQ
5:0 Calibration Latch command and any DRAM command (in DRAM clocks). LPDDR4 only.
RW Not used in DDR3L/DDR4/LPDDR3/WIO2.
118h All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies the delay between the
31:22
RW REFab command to the next valid command. (in DRAM clocks)
0h
21 Reserved (RSVD21): Reserved
RO
4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the minimum time from CKEL
20:17
RW to CKEH (in DRAM clocks).
0h
16 Reserved (RSVD16): Reserved
RO
C30h Refresh Interval Time [tREFI] (NREFI): Specifies the average time between
15:0 refresh commands. JEDEC Base Refresh Interval time (in DRAM clocks). Note: D-Unit
RW will ignore the 2 LSBs of this field.
Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay between
the DRAM Read and Precharge commands to the same bank (in DRAM clocks).
6h • LPDDR3 Equation: = BL/2 + tRTP - 4.
31:27
RW • LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• WIO2 Equation: = NA.
• DDR3L/DDR4 Equation: = tRTP.
CAS to CAS Command Delay Adder (TCCD_INC): Specifies the number of clocks
0h to be added to turnaround times (for Stretch Mode). It increases delay between Read
26:20
RW to Read or Read to Write commands by the amount programmed in this field (in 4 x
DRAM clocks).
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
1h • 0h: Reserved.
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L/DDR4 only. tCMD must be set to 1N for LPDDR3/LPDDR4/WIO2.
8h Write Latency [WL/CWL] (TCWL): The delay between the internal write command
10:6
RW and the availability of the first word of DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW + 8 (BL32).
RW
• WIO2 Equation: NA.
Note: Masked Write operation in LPDDR4 is always BL16 and in WIO2 is always BL4.
D-Unit applies this timing for same rank as well as same bank.
30h Four Bank Activate Window [tFAW] (TFAW): A rolling timeframe in which a
31:24 maximum of four Activate commands can be issued to the same rank. This is to limit
RW the peak current draw from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 - (RL + tDQSCKmin -
8h
23:18 tRPRE).
RW
• LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 - tDQSCKmin.
• DDR3L/DDR4 Equation: tWRDR = CWL + tDQSSmax + BL/2 - (CL + tDQSCKmin -
tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
9h
17:12 • LPDDR3/LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL - tWPRE).
RW
• DDR3L/DDR4 Equation: tRWDR = CL + tDQSCKmax + BL/2 - (CWL - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.
Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Write data burst of a different
rank (in DRAM clocks).
5h
11:6 • LPDDR3/DDR3L/DDR4 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
RW tWPRE.
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
9h start of a Read data burst of one rank to the Start of a Read data burst of a different
5:0 rank (in DRAM clocks).
RW
• Equation: tRRDR = BL/2 + tDQSCKmax - tDQSCKmin + tRPRE.
Row Activation to Row Activation Delay [tRRD] (TRRD): Specifies the minimum
6h delay in DRAM clocks between two DRAM Activate commands to the same rank but
31:27
RW different banks (tRC is the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.
0h
26 Reserved (RSVD26): Reserved
RO
10h Write to Write DQ Delay Same Rank (TWWSR): Specifies the delay from a DRAM
22:18 Write to another Write command of the same rank (in DRAM clocks). Equation: tWWSR
RW = tCCD.
10h Read to Read DQ Delay Same Rank (TRRSR): Specifies the delay from a DRAM
17:13 Read to another Read command of the same rank (in DRAM clocks). Equation: tRRSR =
RW tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).
3h
12:6 • LPDDR3/LPDDR4/WIO2 Equation: tWRSR = WL + tDQSSmax + BL/2 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR.
• DDR4 Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR_S.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle period that defines an
31:24
RW opportunity for refresh (in DRAM clocks).
0h
18:15 Reserved (RSVD18_15): Reserved
RW
Mode Register Read to Any Command Delay (TPSTMRRBLK): Specifies the quiet
time after issuing MRR command (in DRAM Clocks). This is the channel block time for
0h the MR19 command issued as part of LPDDR4 DQS Retraining flow. For all other MR
14:8 commands this is the rank block time. Note: D-Unit treats MRR as a read and always
RW applies relevant turnaround times, any value programmed in this CR must be greater
than those turnaround times for D-Unit to enforce any additional time from MRR to the
next read/write.
0h
7 Reserved (RSVD7): Reserved
RO
All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies the
delay between a DRAM Precharge All Bank command and a DRAM Activate command
3h (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4 in LP3 and
31:26 minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L, DDR4 and WIO2 8ch tRPpb = tRPab = tRP.
0h
8:7 Reserved (RSVD8_7): Reserved
RO
6h Row Activation Period [tRAS] (TRAS): Specifies the minimum delay between the
6:0 DRAM Activate and Precharge commands to the same bank (in DRAM clocks). Note:
RW Derating adds 1.875ns to this timing.
6h Minimum Low Power Mode Residency (LPMDRES): Specifies the minimum time
25:21
RW that PHY should remain in LPMode (in DRAM clocks).
Low Power Mode Exit to Clock Enable Delay (LPMDTOCKEDLY): Specifies the
Ah minimum time between the LP Mode exit to the CK stop/tristate deassertion and
20:15
RW powerdown exit (in DRAM clocks). Note: Must be equal to t_idle_latency published in
the DDRIO PHY and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY): Specifies the time
Ah between CK stop/tristate to the Low Power Mode entry. This timing parameter is used
14:8
RW to delay Low Power Mode entry (in DRAM clocks). Note: Must be at least equal to
t_idle_length parameter published in the DDRIO PHY and less than 0x7C.
18h Power Down Idle Timer (PWDDLY): This is a non-JEDEC timing parameter used to
7:0
RW delay powerdown entry (in DRAM clocks).
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Rank 1 Read ODT Control (R1RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 1. 0 - Read ODT is disabled for Rank 1 1 -
29
RW Assert ODT to for Rank 0 (non-targeted Rank) Note: This register should be set to 0 for
LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 0. 0 - Read ODT is disabled for Rank 0 1 -
28
RW Assert ODT to for Rank 1 (non-targeted Rank) Note: This register is reserved for
LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 1. 00 - Write ODT is disabled 01 - Assert ODT
27:26
RW to Rank 0 (non-targeted Rank) 10 - Assert ODT to Rank 1 (targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
Rank 0 Write ODT Control (R0WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 0. 00 - Write ODT is disabled 01 - Assert ODT
25:24
RW to Rank 0 (targeted Rank) 10 - Assert ODT to Rank 1 (non-targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
0h
23:18 Reserved (RSVD23_18): Reserved
RO
0h
13 Reserved (RSVD13): Reserved
RO
0h
4 Reserved (RSVD4): Reserved
RO
0h
31:29 Reserved (RSVD31_29): Reserved
RO
0h
23 Reserved (RSVD23): Reserved
RO
PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to deassert
before sending a PM message on SR entry.
0h
22 • 0: D-Unit will not wait for SPID_clk to deassert before sending the PM message to
RW PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.
Self-Refresh Entry Delay (SREDLY): Specifies the minimum time the D-Unit will
0h wait before it enters Dynamic Self-Refresh mode when idle (in 16x DRAM Clocks).
15:0
RW Note: The value in this field needs to be minimum of 4 in functional mode and
minimum of 50 in PSMI mode.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS): Setting this bit to 0 allows
majority of the repeaters between D-Unit and PHY to clock gate when there is no
activity in order to save power.
0h
29 • 0 - Enable Repeaters clock gating.
RW
• 1 - Disable Repeaters clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS): Setting this bit to 0
enables the clock gating of IOSF-SB End Points in D-Unit and CPGC when there is no
IOSF-SB activity in order to save power.
1h
28 • 0 - Enable IOSF-SB EP clock gating.
RW
• 1 - Disable IOSF-SB clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power. When
set to 1, D-Unit clockgating is disabled.
0h
27 • 0: Enable.
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
0h Partial Array Self-Refresh Segment Mask (PASR): This is the Segment Mask used
23:16
RW for the MRW to enable PASR during SUSPENDP (Partial Array Self Refresh entry).
0h Page Close Timeout Period (PCLSTO): Specifies the time from the last access of a
15:8 DRAM page until that page is scheduled to close by sending a Precharge command to
RW DRAM (in 16 x DRAM clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
0h the DRAM page when idle.
7
RW • 0: Enable page close timer.
• 1: Disable page close timer (Used during DRAM init and DDRIO training).
0h
6 Reserved (RSVD6): Reserved
RO
Low Power Mode Opcode (LPMODEOP): D-Unit will send the value in this register
0h after it has entered Powerdown Mode and has stopped/tristated the clock. 00: Disable
2:1
RW LPMode. Note: LPMODE entry is not possible when global tristate flow is disabled
(DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0 for
normal operation.
0h • 0: The D-Unit dynamically controls the CKE pins to place the DRAM devices in
0
RW Power Down mode and bring them out of Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the DRAM devices from
entering Power Down mode when ranks are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior on
SR entry/exit.
0h
24:22 Reserved (RSVD24_22): Reserved
RO
Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:
0h
21 • 0: D-Unit sends all postponed REF commands to DRAM before it enters Self
RW
Refresh.
• 1: D-Unit enters SR without clearing the Refresh Debt (for Debug only).
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h
17:16 Reserved (RSVD17_16): Reserved
RO
0h Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit adds one extra
15
RW refresh debit (for a total of two) on Self-refresh exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Stop issuing refresh commands and accumulating refresh debits. (does not
stop tREFI counter).
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h
14:12 • 010: 0.5x refresh rate (i.e. 2x tREFI).
RW
• 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh counter per rank is
7h greater than this value, the D-Unit will send a REF command to the rank regardless of
11:8 pending requests. Note: REFWMPNC must be greater than or equal to REFWMHI and
RW greater than 2, Max Value must be less than 8 to not violate 9xtREFI JEDEC
requirement.
Refresh High Watermark (REFWMHI): When the Refresh counter per rank is
5h greater than this value, the D-Unit will send a REF command to the rank if there is no
7:4
RW critical priority requests in the pending queues. Note: Value must be greater or equal
to 1 and less than or equal to REFWMPNC.
0h
3:1 Reserved (RSVD3_1): Reserved
RO
0h • 0: D-Unit will send a REF command only if there is no pending request to that
0 rank.
RW
• 1: D-Unit will not send any opportunistic refreshes. Refresh commands are only
sent when the refresh counter is greater than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.
0h Early Write DQ Enable (EARLY_DQ_EN): Enables D-unit to send the write data to
31 the PHY one clock earlier than WL value (WL - 1). Note: Applicable to DDR3L and DDR4
RW only.
1Ch Write Pending Queue Count (WPQCOUNT): Used to limit the number of available
26:21 slots in Write Pending Queue/ Write Data Buffer. WPQCOUNT will only recognize
RW changes when PMI ISM is not active.
10h Read Pending Queue Count (RPQCOUNT): Used to limit the number of entries in
20:16 Read Pending Queue. RPQCOUNT will only recognize changes when PMI ISM is not
RW active.
0h
15 Reserved (RSVD15): Reserved
RO
Idle Bypass Mode Enable (BYPASSEN): When set new page hit/empty read
0h requests will bypass D-Unit pipeline stages to save latency 0 - Disable Idle Bypass 1 -
7
RW Enable Idle Bypass Note: Only applies to WIO2, this bit is reserved for other
technologies
0h Block When RDB Full (BLKRDBF): When set D-Unit stops scheduling new read
6
RW commands to DRAM when the read data buffer (RDB) is full.
0h
28:23 Reserved (RSVD28_23): Reserved
RO
0h
20:18 Reserved (RSVD20_18): Reserved
RO
0h
15:14 Reserved (RSVD15_14): Reserved
RO
1057h ZQ Calibration Interval (ZQINT): Specifies the time interval between two ZQCS
13:0 (LPDDR3/DDR3L/DDR4) or ZQ Start (LPDDR4) commands to a DRAM device. (in RTC
RW 32.8KHz clocks)
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h MR Value 2 (MR_VALUE2): MR3 Shadow Register (DDR4): BIOS writes the correct
29:16 value of MR3 register in DDR4 into this field at boot time. D-Unit modifies one bit and
RW rewrites the MR3 into DDR4 to enter and exit MPR mode.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
MR Value (MR_VALUE): MR3 Shadow Register (WIO2): BIOS sets the value of this
field at boot time based on the DRAM device configuration. D-Unit merges the value in
MR3_THERM_OFFSET with this field and writes the result into DRAM MR3 MR2 Shadow
0h Register (DDR3L): BIOS writes the correct value of MR2 register in DDR3L into this
13:0
RW field at boot time. D-Unit modifies one bit and rewrites the MR2 into DDR3L DRAM
before SR entry. MR4 Shadow Register (DDR4): BIOS writes the correct value of MR4
register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the
MR4 into DDR4 DRAM after temperature read out.
0h
30:12 Reserved (RSVD30_12): Reserved
RO
0h
11:0 VNN Timer Time (VNN_TIMER_TIME): The final timer value (in 16 x DRAM clocks).
RW
3h TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value will remain zero. This
31:29 field contains the data of the last temperature sensor read from Rank 1 DRAM Mode
RW/V Register. It is overwritten with each command.
3h TQ Data Rank 0 (TQDATAR0): This field contains the data of the last temperature
28:26
RW/V sensor read from Rank 0 DRAM Mode Register. It is overwritten with each command.
0h
25:22 Reserved (RSVD25_22): Reserved
RO
0h TQ Poll Period (TQPOLLPER): This sets the frequency by which the D-Unit initiates
21:8 temperature sensor read from DRAM mode register to determine required refresh rate
RW (in 4x tREFI units).
Self Refresh Temperature Range Enable (DDR3 Only) (SRTEN): When set,
0h before every Self refresh entry, D-Unit writes a 1 to bit 7 of MR_SHADOW.MR_VALUE
4
RW when TQDATA for that rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3 for each enabled rank.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-Unit pushes the data
2
RW form the last temperature sensor read to a punit register.
0h Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic TQ Poll. If disabled,
0
RW D-Unit will not read the DRAM's temperature sensor value periodically.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
0h
15:11 Reserved (RSVD15_11): Reserved
RO
0h MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to TQDATA read from
10:8
RW MR4 the resulting value is used to control refresh rate and AC timing derating.
0h
7:3 Reserved (RSVD7_3): Reserved
RO
0h MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-Unit writes the merged
2 value of MR3_VALUE and MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this
RW/V bit once the value is written.
Initialization Complete (IC): Indicates that initialization of the D-Unit has been
completed. Memory accesses are permitted and maintenance operation begins. Until
0h this bit is set to a 1, the memory controller will not accept DRAM requests from the
31
RW/V Bunit/GSA/2LM (PMI ISMs will not leave idle). Note: Set this bit to 1 only when all
other D-Unit registers have been configured. Usually set at the last configuration step
by BIOS on cold/warm reset. D-Unit hardware sets this bit on SR exit.
0h DDRIO PHY Initialization Complete (DIOIC): Status indication that the DDRIO
30
RO/V PHY initialization is complete reflects the status spid_init_complete signal.
0h
29 Reserved (RSVD29): Reserved
RO
0h
27:8 Reserved (RSVD27_8): Reserved
RO
0h
7:4 Reserved (RSVD7_4): Reserved
RO
Enable PSMI Mode (PSMIEN): When enabled, D-Unit will synchronize clock crossing
signals.
0h
3 • 0: PSMI Mode is disabled.
RW
• 1: PSMI Mode is enabled.
Note: Change only allowed when D-Unit is idle.
0h
0 Reserved (RSVD0): Reserved
RO
0h
30 Reserved (RSVD30): Reserved
RO
Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
0h • 00: Clock gate disabled.
29:28
RW • 01: Clock Gate every 2 cycles.
• 10: Clock Gate every 3 cycles.
• 11: Clock Gate every 4 cycles.
0h
27:16 Reserved (RSVD27_16): Reserved
RO
0h Scrambling Key (KEY): Sets the key for the scrambler. The key should be a random
15:0
RW value that is set following each cold boot.
0h
31 Reserved (RSVD31): Reserved
RO
0h Error Injection Target Address (ADDRESS): Specifies the PMI address of the write
30:1 transaction to be injected with the error. Only applicable to Write transactions. Read/
RW under-fill read of the partial write operation is not affected.
0h
0 Reserved (RSVD0): Reserved
RO
0h
31:4 Reserved (RSVD31_4): Reserved
RO
Error Injection Type Higher 32B (SEL_HI): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
3 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Higher 32B (EN_HI): When set the error injection is
2 continuously armed for higher 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
1 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Lower 32B (EN_LO): When set, the error injection is
0 continuously armed for lower 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
0h
31 CLEAR: Setting this bit to one clears all fields in this register, including itself.
RW/V
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a correctable single-bit
0h error occurs on a memory read data transfer. When this bit is set, the address that
28 caused the error and the error syndrome are also logged and they are locked to further
RW/V single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is
set will override the address/error syndrome information.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of the error within a
26:25
RW/V chunk.
0h Error Chunk Number (ERR_CHUNK): Chunk number of the error. 0 - lower 32B
24 chunk has error if MERR/CERR is set 1 - higher 32B chunk has the error if MERR/CERR
RW/V is set
0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome for a QW (64 bit)
23:16
RW/V within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI Request Tag which
15:0
RW/V triggered the error log.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
D-Unit Fuse Status (FUSESTAT): D-Unit fuse bits are captured into this register and
are available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V • [5:5]: fus_dun_lpddr4_dis.
• [6:6]: fus_dun_wio2_dis.
• [7:7]: fus_dun_ddr3l_dis.
• [8:8]: fus_dun_ddr4_dis.
• [15:9]: reserved.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
RAW Conflict Read Priority for WMM Transition (RAW_WMM): If a conflict read
5h reaches this priority (or greater depending on access class occupancy), WMM will be
29:27 triggered to unblock the corresponding write. D-Unit will stay in WMM until
RW corresponding write is issued. Note: The value in this bit must not be higher than
lowest terminal priority level of each access class.
0h
26 Reserved (RSVD26): Reserved
RO
6h Read Isoch Trigger Priority (RIMPRIO): If any read in the RPQ is at this
25:23
RW programmable priority, RIM is triggered.
0h
22:18 Reserved (RSVD22_18): Reserved
RO
1Ah Write Isoch Threshold (WIMTHRS): When the number of entries in WPQ is greater
17:12 than or equal to this value (higher than WMM entry watermark, less than WPQ size), it
RW triggers write isoch mode (WIM).
14h Write Major Mode Exit Watermark (WMMEXIT): When the number of entries in
11:6
RW WPQ is less than this value, the D-Unit will switch back to read major mode.
18h Write Major Mode Entry Watermark (WMMENTRY): When the number of entries
5:0 in WPQ is greater than or equal to this value, the D-Unit will switch to write major
RW mode (WMM). Note: the value must not be set to 0.
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes B (MAXWRB): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set B).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes A (MAXWRA): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set A).
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes D (MAXWRD): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set D).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes C (MAXWRC): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set C).
0h
31:15 Reserved (RSVD31_15): Reserved
RO
1h Access Class 4 Initial Priority (AC4IP): Initial priority level of read requests
14:12
RW coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of read requests
11:9
RW coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of read requests
8:6
RW coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of read requests
5:3
RW coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of read requests
2:0
RW coming with access class 0.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Ah Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:11 Reserved (RSVD31_11): Reserved
RO
0h
31:25 Reserved (RSVD31_25): Reserved
RO
0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe write page hits block
24
RW safe write page misses same bank.
0h
23:20 Reserved (RSVD23_20): Reserved
RO
WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe priority 1 read miss
0h block write hit to same bank. Note: This rule does not block the bank that is being
19
RW blocked by WMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe priority 1 write hit
0h block write miss to same bank. Note: This rule does not block the bank that is being
18
RW blocked by WMM_PRIO_R1. Priority rules 1,3 and 4 should be enabled/disabled
together.
0h
17 WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS block rule.
RW
0h WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe top priority 1 write
16 miss block write hit same bank. Priority rules 1, 3 and 4 should be enabled/disabled
RW together.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
0h
RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe write page hits block
13
safe write page misses same bank.
RW
1h RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe read page miss block
12 all safe and unsafe write page hit to the same bank. Note: This field must not be set to
RW 0 (enabled) if RMM_REG_R4 is also 0.
1h RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe write page hit block
11 safe read page miss same bank. Note: This field must not be set to 0 (enabled) if
RW RMM_REG_R5 is also 0.
0h RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe read page hit block safe
10 read and write page miss same bank. Note: This rule does not block the bank that is
RW being blocked by RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe read page empty block
9
RW safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe read page hit block safe
8
RW write page hit same rank.
0h
7:4 Reserved (RSVD7_4): Reserved
RO
RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe critical read miss block
0h read and write hit to same bank. Note: This rule does not block the bank that is being
3
RW blocked by RMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe critical read hit block
0h read and write miss to same bank. Note: This rule does not block the bank that is being
2
RW blocked by RMM_PRIO_R1. Priority rules 1, 3 and 4 should be enabled/disabled
together.
0h
1 RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block rule.
RW
0h RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe top critical read miss
0 block read and write hit same bank. Note: Priority rules 1, 3 and 4 should be enabled/
RW disabled together.
0h
31:4 Reserved (RSVD31_4): Reserved
RO
SUSPENDP: A SUSPENDP message will put the DRAM into self-refresh mode. The D-
Unit will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in self refresh mode. Finally, a PM
3 message will be sent to the PHY. The bit is cleared by hardware after the PHY indicates
RW/V the transition requested in the PM message has been completed. D-Unit will perform an
MRW to MR17 with an opcode as defined by DPMC0.PASR before it places the DRAM
into Self-Refresh.
SUSPEND: A SUSPEND message will put the DRAM into self-refresh mode. The D-Unit
will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in Self Refresh mode. Finally, a PM
2
RW/V message will be sent to the PHY. The bit is cleared by hardware only after the PHY
indicates the transition requested in the PM message has been completed. Note: When
COLDWAKE is set prior of setting this bit the DRAM will not be placed in SR.
0h
1 Reserved (RSVD1): Reserved
RO
WAKE: Take PHY out of PM states and wakes the DRAM out of self refresh mode. The
0h bit is cleared by hardware only when the DRAM has exited out of self refresh mode and
0
RW/V is accessible. Note: When COLDWAKE is set prior of setting this bit the D-Unit will not
send SR exit command and will not set the DCO.IC bit.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts DQS oscillator, it must
0h wait this amount of time before being able to read the value in MR18 and MR19 (in 16x
13:4
RW DRAM clocks). Value in this register must be at least equal to DRAM's MR23 value. +
tOSCO.
0h
31 Reserved (RSVD31): Reserved
RO
0h
30:28 MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of MR4 data.
RW
0h
27 Reserved (RSVD27): Reserved
RO
0h
26:24 MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of MR4 data
RW
0h
23 Reserved (RSVD23): Reserved
RO
0h
22:20 MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of MR4 data.
RW
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of the MR4 data for
17:16
RW second device.
0h
15 Reserved (RSVD15): Reserved
RO
0h
14:12 MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW
0h
11 Reserved (RSVD11): Reserved
RO
0h
10:8 MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW
0h
7 Reserved (RSVD7): Reserved
RO
0h
6:4 MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW
0h
3:2 Reserved (RSVD3_2): Reserved
RO
0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of the MR4 data first
1:0
RW device.
0h
18:17 Reserved (RSVD18_17): Reserved
RO
Fine Bank Group Interleaving Enable (FBGINTEN): When enabled, D-unit will use
a lower order address bit in the bank hashing function (DDR4 Only).
0h
16 • 0: Bank Group Interleave disabled.
RW
• 1: Bank Group Interleave enabled.
Note: BAHEN must be set for this bit to take effect.
0h
13:9 Reserved (RSVD13_9): Reserved
RO
DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h
8:6 • 010: 8 Gb.
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.
DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
0h • 00: x8.
5:4
RW • 01: x16.
• 10: x32.
• 11: x64.
0h
3 Reserved (RSVD3): Reserved
RO
0h
1 Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to enable use of this rank.
RW
0h Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to enable use of this rank.
0
RW Note: Setting this bit to 0 is not a functional mode.
0h
31:23 Reserved (RSVD31_23): Reserved
RO
5h Write to Write DQ Delay Same Bank Group Same Rank (TWWSR_L): Specifies
22:18 the delay from a DRAM Write to another Write command within the same bank group of
RW the same rank (in DRAM clocks). DDR4 Equation: tWWSR_L = tCCD_L.
5h Read to Read DQ Delay Same Bank Group Same Rank (TRRSR_L): Specifies the
17:13 delay from a DRAM Read to another Read command within the same bank group of the
RW same rank (in DRAM clocks). DDR4 Equation: tRRSR_L = tCCD_L.
Write to Read DQ Delay Same Bank Group Same Rank (TWRSR_L): Specifies
15h the delay from a DRAM Read to Write command within the same bank group of the
12:6 same rank (in DRAM clocks).
RW
• DDR4 Equation: tWRSR_L = CWL + tDQSSmax + BL/2 + tWPST + tWTR_L.
Bh Activate RAS to CAS Command Delay [tRCD] (TRCD): Specifies the delay
11:6 between a DRAM Activate command and a DRAM Read or Write command to the same
RW bank (in DRAM clocks). Note: Derating adds 1.875ns to this timing.
Exit Power Down to Next Command Delay [tXP] (TXP): Specifies the delay from
6h the DRAM Power Down Exit (PDX) command to any valid command (in DRAM clocks).
31:27
RW Note: The value in this field must be programmed to tXPDLL when Slow Exit Mode
Power-down is enabled for DDR3L.
0h
26 Reserved (RSVD26): Reserved
RO
18h ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay between the DRAM ZQ
5:0 Calibration Latch command and any DRAM command (in DRAM clocks). LPDDR4 only.
RW Not used in DDR3L/DDR4/LPDDR3/WIO2.
118h All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies the delay between the
31:22
RW REFab command to the next valid command. (in DRAM clocks)
0h
21 Reserved (RSVD21): Reserved
RO
4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the minimum time from CKEL
20:17
RW to CKEH (in DRAM clocks).
0h
16 Reserved (RSVD16): Reserved
RO
C30h Refresh Interval Time [tREFI] (NREFI): Specifies the average time between
15:0 refresh commands. JEDEC Base Refresh Interval time (in DRAM clocks). Note: D-Unit
RW will ignore the 2 LSBs of this field.
Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay between
the DRAM Read and Precharge commands to the same bank (in DRAM clocks).
6h • LPDDR3 Equation: = BL/2 + tRTP - 4.
31:27
RW • LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• WIO2 Equation: NA.
• DDR3L/DDR4 Equation: = tRTP.
CAS to CAS Command Delay Adder (TCCD_INC): Specifies the number of clocks
0h to be added to turnaround times (for Stretch Mode). It increases delay between Read
26:20
RW to Read or Read to Write commands by the amount programmed in this field (in 4 x
DRAM clocks).
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
1h • 0h: Reserved.
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L/DDR4 only. tCMD must be set to 1N for LPDDR3/LPDDR4/WIO2.
Write Latency [WL/CWL] (TCWL): The delay between the internal write command
10:6 8h
and the availability of the first word of DRAM input data (in DRAM clocks).
RW
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW + 8 (BL32).
RW
• WIO2 Equation: NA.
Note: Masked Write operation in LPDDR4 is always BL16 and in WIO2 is always BL4.
D-Unit applies this timing for same rank as well as same bank.
30h Four Bank Activate Window [tFAW] (TFAW): A rolling timeframe in which a
31:24 maximum of four Activate commands can be issued to the same rank. This is to limit
RW the peak current draw from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 - (RL + tDQSCKmin -
8h
23:18 tRPRE).
RW
• LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 - tDQSCKmin.
• DDR3L/DDR4 Equation: tWRDR = CWL + tDQSSmax + BL/2 - (CL + tDQSCKmin -
tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
9h
17:12 • LPDDR3/LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL - tWPRE).
RW
• DDR3L/DDR4 Equation: tRWDR = CL + tDQSCKmax + BL/2 - (CWL - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.
Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Write data burst of a different
rank (in DRAM clocks).
5h
11:6 • LPDDR3/DDR3L/DDR4 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
RW tWPRE.
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
9h start of a Read data burst of one rank to the Start of a Read data burst of a different
5:0 rank (in DRAM clocks).
RW
• Equation: tRRDR = BL/2 + tDQSCKmax - tDQSCKmin + tRPRE.
Row Activation to Row Activation Delay [tRRD] (TRRD): Specifies the minimum
6h delay in DRAM clocks between two DRAM Activate commands to the same rank but
31:27
RW different banks (tRC is the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.
0h
26 Reserved (RSVD26): Reserved
RO
10h Write to Write DQ Delay Same Rank (TWWSR): Specifies the delay from a DRAM
22:18 Write to another Write command of the same rank (in DRAM clocks). Equation: tWWSR
RW = tCCD.
10h Read to Read DQ Delay Same Rank (TRRSR): Specifies the delay from a DRAM
17:13 Read to another Read command of the same rank (in DRAM clocks). Equation: tRRSR =
RW tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).
3h
12:6 • LPDDR3/LPDDR4/WIO2 Equation: tWRSR = WL + tDQSSmax + BL/2 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR.
• DDR4 Equation: tWRSR = CWL + tDQSSmax + BL/2 + tWTR_S.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle period that defines an
31:24
RW opportunity for refresh (in DRAM clocks).
0h
18:15 Reserved (RSVD18_15): Reserved
RW
Mode Register Read to Any Command Delay (TPSTMRRBLK): Specifies the quiet
time after issuing MRR command (in DRAM Clocks). This is the channel block time for
0h the MR19 command issued as part of LPDDR4 DQS Retraining flow. For all other MR
14:8 commands this is the rank block time. Note: D-Unit treats MRR as a read and always
RW applies relevant turnaround times, any value programmed in this CR must be greater
than those turnaround times for D-Unit to enforce any additional time from MRR to the
next read/write.
0h
7 Reserved (RSVD7): Reserved
RO
All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies the
delay between a DRAM Precharge All Bank command and a DRAM Activate command
3h (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4 in LP3 and
31:26 minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L, DDR4 and WIO2 8ch tRPpb = tRPab = tRP.
0h
8:7 Reserved (RSVD8_7): Reserved
RO
6h Row Activation Period [tRAS] (TRAS): Specifies the minimum delay between the
6:0 DRAM Activate and Precharge commands to the same bank (in DRAM clocks). Note:
RW Derating adds 1.875ns to this timing.
6h Minimum Low Power Mode Residency (LPMDRES): Specifies the minimum time
25:21
RW that PHY should remain in LPMode (in DRAM clocks).
Low Power Mode Exit to Clock Enable Delay (LPMDTOCKEDLY): Specifies the
Ah minimum time between the LP Mode exit to the CK stop/tristate deassertion and
20:15
RW powerdown exit (in DRAM clocks). Note: Must be equal to t_idle_latency published in
the DDRIO PHY and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY): Specifies the time
Ah between CK stop/tristate to the Low Power Mode entry. This timing parameter is used
14:8
RW to delay Low Power Mode entry (in DRAM clocks). Note: Must be at least equal to
t_idle_length parameter published in the DDRIO PHY and less than 0x7C.
18h Power Down Idle Timer (PWDDLY): This is a non-JEDEC timing parameter used to
7:0
RW delay powerdown entry (in DRAM clocks).
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Rank 1 Read ODT Control (R1RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 1. 0 - Read ODT is disabled for Rank 1 1 -
29
RW Assert ODT to for Rank 0 (non-targeted Rank) Note: This register should be set to 0 for
LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the behavior of ODT signals
0h when a Read command is issued to Rank 0. 0 - Read ODT is disabled for Rank 0 1 -
28
RW Assert ODT to for Rank 1 (non-targeted Rank) Note: This register is reserved for
LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 1. 00 - Write ODT is disabled 01 - Assert ODT
27:26
RW to Rank 0 (non-targeted Rank) 10 - Assert ODT to Rank 1 (targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
Rank 0 Write ODT Control (R0WRODTCTL): Specifies the behavior of ODT signals
0h when a Write command is issued to Rank 0. 00 - Write ODT is disabled 01 - Assert ODT
25:24
RW to Rank 0 (targeted Rank) 10 - Assert ODT to Rank 1 (non-targeted Rank) 11 - Assert
ODT to Rank 0 and Rank 1 Note: 10 and 11 are reserved values for LPDDR3
0h
23:18 Reserved (RSVD23_18): Reserved
RO
0h
13 Reserved (RSVD13): Reserved
RO
0h
4 Reserved (RSVD4): Reserved
RO
0h
31:29 Reserved (RSVD31_29): Reserved
RO
0h
23 Reserved (RSVD23): Reserved
RO
PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to deassert
before sending a PM message on SR entry.
0h
22 • 0: D-Unit will not wait for SPID_clk to deassert before sending the PM message to
RW PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.
Self-Refresh Entry Delay (SREDLY): Specifies the minimum time the D-Unit will
0h wait before it enters Dynamic Self-Refresh mode when idle (in 16x DRAM Clocks).
15:0
RW Note: The value in this field needs to be minimum of 4 in functional mode and
minimum of 50 in PSMI mode.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS): Setting this bit to 0 allows
majority of the repeaters between D-Unit and PHY to clock gate when there is no
activity in order to save power.
0h
29 • 0 - Enable Repeaters clock gating.
RW
• 1 - Disable Repeaters clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS): Setting this bit to 0
enables the clock gating of IOSF-SB End Points in D-Unit and CPGC when there is no
IOSF-SB activity in order to save power.
1h
28 • 0 - Enable IOSF-SB EP clock gating.
RW
• 1 - Disable IOSF-SB clock gating.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power. When
set to 1, D-Unit clockgating is disabled.
0h
27 • 0: Enable.
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.
0h Partial Array Self-Refresh Segment Mask (PASR): This is the Segment Mask used
23:16
RW for the MRW to enable PASR during SUSPENDP (Partial Array Self Refresh entry).
0h Page Close Timeout Period (PCLSTO): Specifies the time from the last access of a
15:8 DRAM page until that page is scheduled to close by sending a Precharge command to
RW DRAM (in 16 x DRAM clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
0h the DRAM page when idle.
7
RW • 0: Enable page close timer.
• 1: Disable page close timer (Used during DRAM init and DDRIO training).
0h
6 Reserved (RSVD6): Reserved
RO
Low Power Mode Opcode (LPMODEOP): D-Unit will send the value in this register
0h after it has entered Powerdown Mode and has stopped/tristated the clock. 00: Disable
2:1
RW LPMode. Note: LPMODE entry is not possible when global tristate flow is disabled
(DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0 for
normal operation.
0h • 0: The D-Unit dynamically controls the CKE pins to place the DRAM devices in
0
RW Power Down mode and bring them out of Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the DRAM devices from
entering Power Down mode when ranks are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior on
SR entry/exit.
0h
24:22 Reserved (RSVD24_22): Reserved
RO
Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:
0h
21 • 0: D-Unit sends all postponed REF commands to DRAM before it enters Self
RW
Refresh.
• 1: D-Unit enters SR without clearing the Refresh Debt (for Debug only).
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h
17:16 Reserved (RSVD17_16): Reserved
RO
0h Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit adds one extra
15
RW refresh debit (for a total of two) on Self-refresh exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Stop issuing refresh commands and accumulating refresh debits. (does not
stop tREFI counter).
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h
14:12 • 010: 0.5x refresh rate (i.e. 2x tREFI).
RW
• 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh counter per rank is
7h greater than this value, the D-Unit will send a REF command to the rank regardless of
11:8 pending requests. Note: REFWMPNC must be greater than or equal to REFWMHI and
RW greater than 2, Max Value must be less than 8 to not violate 9xtREFI JEDEC
requirement.
Refresh High Watermark (REFWMHI): When the Refresh counter per rank is
5h greater than this value, the D-Unit will send a REF command to the rank if there is no
7:4
RW critical priority requests in the pending queues. Note: Value must be greater or equal
to 1 and less than or equal to REFWMPNC.
0h
3:1 Reserved (RSVD3_1): Reserved
RO
0h • 0: D-Unit will send a REF command only if there is no pending request to that
0 rank.
RW
• 1: D-Unit will not send any opportunistic refreshes. Refresh commands are only
sent when the refresh counter is greater than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.
0h Early Write DQ Enable (EARLY_DQ_EN): Enables D-unit to send the write data to
31 the PHY one clock earlier than WL value (WL - 1). Note: Applicable to DDR3L and DDR4
RW only.
1Ch Write Pending Queue Count (WPQCOUNT): Used to limit the number of available
26:21 slots in Write Pending Queue/ Write Data Buffer. WPQCOUNT will only recognize
RW changes when PMI ISM is not active.
10h Read Pending Queue Count (RPQCOUNT): Used to limit the number of entries in
20:16 Read Pending Queue. RPQCOUNT will only recognize changes when PMI ISM is not
RW active.
0h
15 Reserved (RSVD15): Reserved
RO
Idle Bypass Mode Enable (BYPASSEN): When set new page hit/empty read
0h requests will bypass D-Unit pipeline stages to save latency 0 - Disable Idle Bypass 1 -
7
RW Enable Idle Bypass Note: Only applies to WIO2, this bit is reserved for other
technologies
0h Block When RDB Full (BLKRDBF): When set D-Unit stops scheduling new read
6
RW commands to DRAM when the read data buffer (RDB) is full.
0h
28:23 Reserved (RSVD28_23): Reserved
RO
0h
20:18 Reserved (RSVD20_18): Reserved
RO
0h
15:14 Reserved (RSVD15_14): Reserved
RO
1057h ZQ Calibration Interval (ZQINT): Specifies the time interval between two ZQCS
13:0 (LPDDR3/DDR3L/DDR4) or ZQ Start (LPDDR4) commands to a DRAM device. (in RTC
RW 32.8KHz clocks)
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h MR Value 2 (MR_VALUE2): MR3 Shadow Register (DDR4): BIOS writes the correct
29:16 value of MR3 register in DDR4 into this field at boot time. D-Unit modifies one bit and
RW rewrites the MR3 into DDR4 to enter and exit MPR mode.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
MR Value (MR_VALUE): MR3 Shadow Register (WIO2): BIOS sets the value of this
field at boot time based on the DRAM device configuration. D-Unit merges the value in
MR3_THERM_OFFSET with this field and writes the result into DRAM MR3 MR2 Shadow
0h Register (DDR3L): BIOS writes the correct value of MR2 register in DDR3L into this
13:0
RW field at boot time. D-Unit modifies one bit and rewrites the MR2 into DDR3L DRAM
before SR entry. MR4 Shadow Register (DDR4): BIOS writes the correct value of MR4
register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the
MR4 into DDR4 DRAM after temperature read out.
0h
30:12 Reserved (RSVD30_12): Reserved
RO
0h
11:0 VNN Timer Time (VNN_TIMER_TIME): The final timer value (in 16 x DRAM clocks).
RW
3h TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value will remain zero. This
31:29 field contains the data of the last temperature sensor read from Rank 1 DRAM Mode
RW/V Register. It is overwritten with each command.
3h TQ Data Rank 0 (TQDATAR0): This field contains the data of the last temperature
28:26
RW/V sensor read from Rank 0 DRAM Mode Register. It is overwritten with each command.
0h
25:22 Reserved (RSVD25_22): Reserved
RO
0h TQ Poll Period (TQPOLLPER): This sets the frequency by which the D-Unit initiates
21:8 temperature sensor read from DRAM mode register to determine required refresh rate
RW (in 4x tREFI units).
Self Refresh Temperature Range Enable (DDR3 Only) (SRTEN): When set,
0h before every Self refresh entry, D-Unit writes a 1 to bit 7 of MR_SHADOW.MR_VALUE
4
RW when TQDATA for that rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3 for each enabled rank.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-Unit pushes the data
2
RW form the last temperature sensor read to a punit register.
0h Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic TQ Poll. If disabled,
0
RW D-Unit will not read the DRAM's temperature sensor value periodically.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
0h
15:11 Reserved (RSVD15_11): Reserved
RO
0h MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to TQDATA read from
10:8
RW MR4 the resulting value is used to control refresh rate and AC timing derating.
0h
7:3 Reserved (RSVD7_3): Reserved
RO
0h MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-Unit writes the merged
2 value of MR3_VALUE and MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this
RW/V bit once the value is written.
Initialization Complete (IC): Indicates that initialization of the D-Unit has been
completed. Memory accesses are permitted and maintenance operation begins. Until
0h this bit is set to a 1, the memory controller will not accept DRAM requests from the
31
RW/V Bunit/GSA/2LM (PMI ISMs will not leave idle). Note: Set this bit to 1 only when all
other D-Unit registers have been configured. Usually set at the last configuration step
by BIOS on cold/warm reset. D-Unit hardware sets this bit on SR exit.
0h DDRIO PHY Initialization Complete (DIOIC): Status indication that the DDRIO
30
RO/V PHY initialization is complete reflects the status spid_init_complete signal.
0h
29 Reserved (RSVD29): Reserved
RO
0h
27:8 Reserved (RSVD27_8): Reserved
RO
0h
7:4 Reserved (RSVD7_4): Reserved
RO
Enable PSMI Mode (PSMIEN): When enabled, D-Unit will synchronize clock crossing
signals.
0h
3 • 0: PSMI Mode is disabled.
RW
• 1: PSMI Mode is enabled.
Note: Change only allowed when D-Unit is idle.
0h
0 Reserved (RSVD0): Reserved
RO
0h
30 Reserved (RSVD30): Reserved
RO
Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
0h • 00: Clock gate disabled.
29:28
RW • 01: Clock Gate every 2 cycles.
• 10: Clock Gate every 3 cycles.
• 11: Clock Gate every 4 cycles.
0h
27:16 Reserved (RSVD27_16): Reserved
RO
0h Scrambling Key (KEY): Sets the key for the scrambler. The key should be a random
15:0
RW value that is set following each cold boot.
0h
31 Reserved (RSVD31): Reserved
RO
0h Error Injection Target Address (ADDRESS): Specifies the PMI address of the write
30:1 transaction to be injected with the error. Only applicable to Write transactions. Read/
RW under-fill read of the partial write operation is not affected.
0h
0 Reserved (RSVD0): Reserved
RO
0h
31:4 Reserved (RSVD31_4): Reserved
RO
Error Injection Type Higher 32B (SEL_HI): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
3 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Higher 32B (EN_HI): When set the error injection is
2 continuously armed for higher 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable Error (UE) is armed
0h for write address matching to inject UE by using the same poisoning scheme, i.e.
1 inverting corresponding write ECC[6:0] on every QW of the 32B data. 1 - Correctable
RW Error (CE) is armed for write address matching to inject CE by inverting corresponding
write ECC[0] on every QW of the 32B data.
0h Error Injection Enable Lower 32B (EN_LO): When set, the error injection is
0 continuously armed for lower 32B of D_CR_ERR_INJ_ADDR write address matching
RW until it is cleared.
0h
31 CLEAR: Setting this bit to one clears all fields in this register, including itself.
RW/V
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a correctable single-bit
0h error occurs on a memory read data transfer. When this bit is set, the address that
28 caused the error and the error syndrome are also logged and they are locked to further
RW/V single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is
set will override the address/error syndrome information.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of the error within a
26:25
RW/V chunk.
0h Error Chunk Number (ERR_CHUNK): Chunk number of the error. 0 - lower 32B
24 chunk has error if MERR/CERR is set 1 - higher 32B chunk has the error if MERR/CERR
RW/V is set
0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome for a QW (64 bit)
23:16
RW/V within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI Request Tag which
15:0
RW/V triggered the error log.
0h
31:16 Reserved (RSVD31_16): Reserved
RO
D-Unit Fuse Status (FUSESTAT): D-Unit fuse bits are captured into this register and
are available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V • [5:5]: fus_dun_lpddr4_dis.
• [6:6]: fus_dun_wio2_dis.
• [7:7]: fus_dun_ddr3l_dis.
• [8:8]: fus_dun_ddr4_dis.
• [15:9]: reserved.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
RAW Conflict Read Priority for WMM Transition (RAW_WMM): If a conflict read
5h reaches this priority (or greater depending on access class occupancy), WMM will be
29:27 triggered to unblock the corresponding write. D-Unit will stay in WMM until
RW corresponding write is issued. Note: The value in this bit must not be higher than
lowest terminal priority level of each access class.
0h
26 Reserved (RSVD26): Reserved
RO
6h Read Isoch Trigger Priority (RIMPRIO): If any read in the RPQ is at this
25:23
RW programmable priority, RIM is triggered.
0h
22:18 Reserved (RSVD22_18): Reserved
RO
1Ah Write Isoch Threshold (WIMTHRS): When the number of entries in WPQ is greater
17:12 than or equal to this value (higher than WMM entry watermark, less than WPQ size), it
RW triggers write isoch mode (WIM).
14h Write Major Mode Exit Watermark (WMMEXIT): When the number of entries in
11:6
RW WPQ is less than this value, the D-Unit will switch back to read major mode.
18h Write Major Mode Entry Watermark (WMMENTRY): When the number of entries
5:0 in WPQ is greater than or equal to this value, the D-Unit will switch to write major
RW mode (WMM). Note: the value must not be set to 0.
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes B (MAXWRB): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set B).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes A (MAXWRA): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set A).
0h
31:26 Reserved (RSVD31_26): Reserved
RO
10h Max Writes D (MAXWRD): Maximum number of writes D-Unit can send in WMM
25:20
RW mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to be serviced before a
19:14
RW switch to WMM is allowed (set D).
0h
13:12 Reserved (RSVD13_12): Reserved
RO
10h Max Writes C (MAXWRC): Maximum number of writes D-Unit can send in WMM
11:6
RW mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to be serviced before a
5:0
RW switch to WMM is allowed (set C).
0h
31:15 Reserved (RSVD31_15): Reserved
RO
1h Access Class 4 Initial Priority (AC4IP): Initial priority level of read requests
14:12
RW coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of read requests
11:9
RW coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of read requests
8:6
RW coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of read requests
5:3
RW coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of read requests
2:0
RW coming with access class 0.
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
Ah Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of CASes that pass before a request in this
29:25
RW priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass before a request in this
24:20
RW priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass before a request in this
19:15
RW priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of Cases that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of Cases that pass before a request in this
24:20
RW priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of Cases that pass before a request in this
19:15
RW priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of Cases that pass before a request in this
14:10
RW priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of Cases that pass before a request in this
9:5
RW priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of Cases that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:30 Reserved (RSVD31_30): Reserved
RO
0h Priority 6 Residency (P6RES): Number of Cases that pass before a request in this
29:25
RW priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of Cases that pass before a request in this
24:20
RW priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of Cases that pass before a request in this
19:15
RW priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of Cases that pass before a request in this
14:10
RW priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of Cases that pass before a request in this
9:5
RW priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of Cases that pass before a request in this
4:0
RW priority promotes to the next priority level.
0h
31:11 Reserved (RSVD31_11): Reserved
RO
0h
31:25 Reserved (RSVD31_25): Reserved
RO
0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe write page hits block
24
RW safe write page misses same bank.
0h
23:20 Reserved (RSVD23_20): Reserved
RO
WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe priority 1 read miss
0h block write hit to same bank. Note: This rule does not block the bank that is being
19
RW blocked by WMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe priority 1 write hit
0h block write miss to same bank. Note: This rule does not block the bank that is being
18
RW blocked by WMM_PRIO_R1. Priority rules 1,3 and 4 should be enabled/disabled
together.
0h
17 WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS block rule.
RW
0h WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe top priority 1 write
16 miss block write hit same bank. Priority rules 1, 3 and 4 should be enabled/disabled
RW together.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe write page hits block
13
RW safe write page misses same bank.
RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe read page miss block
12 1h all safe and unsafe write page hit to the same bank. Note: This field must not be set to
RW 0 (enabled) if RMM_REG_R4 is also 0.
1h RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe write page hit block
11 safe read page miss same bank. Note: This field must not be set to 0 (enabled) if
RW RMM_REG_R5 is also 0.
0h RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe read page hit block safe
10 read and write page miss same bank. Note: This rule does not block the bank that is
RW being blocked by RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe read page empty block
9
RW safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe read page hit block safe
8
RW write page hit same rank.
0h
7:4 Reserved (RSVD7_4): Reserved
RO
RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe critical read miss block
0h read and write hit to same bank. Note: This rule does not block the bank that is being
3
RW blocked by RMM_PRIO_R3. Priority rules 1, 3 and 4 should be enabled/disabled
together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe critical read hit block
0h read and write miss to same bank. Note: This rule does not block the bank that is being
2
RW blocked by RMM_PRIO_R1. Priority rules 1, 3 and 4 should be enabled/disabled
together.
0h
1 RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block rule.
RW
0h RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe top critical read miss
0 block read and write hit same bank. Note: Priority rules 1, 3 and 4 should be enabled/
RW disabled together.
0h
31:4 Reserved (RSVD31_4): Reserved
RO
SUSPENDP: A SUSPENDP message will put the DRAM into self-refresh mode. The D-
Unit will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in self refresh mode. Finally, a PM
3 message will be sent to the PHY. The bit is cleared by hardware after the PHY indicates
RW/V the transition requested in the PM message has been completed. D-Unit will perform an
MRW to MR17 with an opcode as defined by DPMC0.PASR before it places the DRAM
into Self-Refresh.
SUSPEND: A SUSPEND message will put the DRAM into self-refresh mode. The D-Unit
will complete servicing outstanding memory requests and flush all queued Refresh
0h commands to DRAM before putting the DRAM in Self Refresh mode. Finally, a PM
2
RW/V message will be sent to the PHY. The bit is cleared by hardware only after the PHY
indicates the transition requested in the PM message has been completed. Note: When
COLDWAKE is set prior of setting this bit the DRAM will not be placed in SR.
0h
1 Reserved (RSVD1): Reserved
RO
WAKE: Take PHY out of PM states and wakes the DRAM out of self refresh mode. The
0h bit is cleared by hardware only when the DRAM has exited out of self refresh mode and
0
RW/V is accessible. Note: When COLDWAKE is set prior of setting this bit the D-Unit will not
send SR exit command and will not set the DCO.IC bit.
0h
15:14 Reserved (RSVD15_14): Reserved
RO
DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts DQS oscillator, it must
0h wait this amount of time before being able to read the value in MR18 and MR19 (in 16x
13:4
RW DRAM clocks). Value in this register must be at least equal to DRAM's MR23 value. +
tOSCO.
0h
31 Reserved (RSVD31): Reserved
RO
0h
30:28 MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of MR4 data.
RW
0h
27 Reserved (RSVD27): Reserved
RO
0h
26:24 MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of MR4 data
RW
0h
23 Reserved (RSVD23): Reserved
RO
0h
22:20 MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of MR4 data.
RW
0h
19:18 Reserved (RSVD19_18): Reserved
RO
0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of the MR4 data for
17:16
RW second device.
0h
15 Reserved (RSVD15): Reserved
RO
0h
14:12 MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW
0h
11 Reserved (RSVD11): Reserved
RO
0h
10:8 MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW
0h
7 Reserved (RSVD7): Reserved
RO
0h
6:4 MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW
0h
3:2 Reserved (RSVD3_2): Reserved
RO
0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of the MR4 data first
1:0
RW device.
C006121020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RO to read the registers contained in the policy group.
C006121020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RO to write the registers contained in the policy group.
4000100020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to update the CP, RAC, and WAC registers of the policy group.
80000C0063 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 010217h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to read the registers contained in the policy group.
3.211 C_CR_BIOSWR_WAC
(C_CR_BIOSWR_WAC_0_0_0_MCHBAR) — Offset 6028h
Write access control policy register for the BIOS Write Policy Group.
400010C021 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to write the registers contained in the policy group.
4000100020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to update the CP, RAC, and WAC registers of the policy group.
FFFFFFFFFFF Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 FFFFFh with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RO to read the registers contained in the policy group.
4000100020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to write the registers contained in the policy group.
C006121020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to update the CP, RAC, and WAC registers of the policy group.
80000C0063 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 210217h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to read the registers contained in the policy group.
C00612C021 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to write the registers contained in the policy group.
4000120020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to update the CP, RAC, and WAC registers of the policy group.
FFFFFFFFFFF Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 FFFFFh with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RO to read the registers contained in the policy group.
4000120020 Security Attribute of Initiator Permission Enable (SAI): Each bit is associated
63:0 2h with the SAI of an agent. When set to 1'b1, the associated agent is granted permission
RW to write the registers contained in the policy group.
0h
31:30 Reserved (RSVD): Reserved
RO
1h
29:24 VC0B Completion Grant Count (VC0B_C): VC0B completion grant count to T-Unit.
RW
0h
23:22 Reserved (RSVD): Reserved
RO
1h VC0B Posted Grant Count (VC0B_P): VC0B posted transaction grant count to T-
21:16
RW Unit. This is only for MSIs.
0h
15:14 Reserved (RSVD): Reserved
RO
1h
13:8 VC0A Completion Grant Count (VC0A_C): VC0A completion grant count to T-Unit.
RW
0h
7:6 Reserved (RSVD): Reserved
RO
1h
5:0 VC0A Posted Grant Count (VC0A_P): VC0A posted to T-Unit MSIs.
RW
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 RO Reserved (RSVD): Reserved
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD): Reserved
RO
0h
23:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
0h
7:6 Reserved (RSVD): Reserved
RO
0h
31:22 Reserved (RSVD): Reserved
RO
1h
21:16 C: All Completions.
RW
0h
15:14 Reserved (RSVD): Reserved
RO
1h
13:8 Non-posted (NP): All non-posted.
RW
0h
7:6 Reserved (RSVD): Reserved
RO
1h
5:0 P: All posted.
RW
0h
31:22 Reserved (RSVD): Reserved
RO
0h
15:14 Reserved (RSVD): Reserved
RO
1h
13:8 NP: All Non Posteds
RW
0h
7:6 Reserved (RSVD): Reserved
RO
1h
5:0 P: All Posteds
RW
FFh
31:24 Channel ID 3 (CHID3): Gazelle queue limit for Upstream NP on channel ID 3.
RW
FFh
23:16 Channel ID 2 (CHID2): Gazelle queue limit for Upstream NP on channel ID 2.
RW
FFh
15:8 Channel ID 1 (CHID1): Gazelle queue limit for Upstream NP on channel ID 1.
RW
FFh
7:0 Channel ID 0 (CHID0): Gazelle queue limit for Upstream NP on channel ID 0.
RW
FFh
31:24 Channel ID 7 (CHID7): Gazelle queue limit for Upstream NP on channel ID 7.
RW
FFh
23:16 Channel ID 6 (CHID6): Gazelle queue limit for Upstream NP on channel ID 6.
RW
FFh
15:8 Channel ID 5 (CHID5): Gazelle queue limit for Upstream NP on channel ID 5.
RW
FFh
7:0 Channel ID 4 (CHID4): Gazelle queue limit for Upstream NP on channel ID 4.
RW
0h
31:22 Reserved (RSVD): Reserved
RO
1h
21:16 Class Count (CLASS_CNT): IOMMU arbiter class grant count.
RW
0h
15:14 Reserved (RSVD): Reserved
RO
1h
13:8 Device Non-posted (DEV_NP): IOMMU arbiter device grant count for NP.
RW
0h
7:6 Reserved (RSVD): Reserved
RO
1h
5:0 Device Posted (DEV_P): IOMMU arbiter device grant count for p.
RW
0h
31:22 Reserved (RSVD): Reserved
RO
1h
21:16 Class Count (CLASS_CNT): IOMMU arbiter class grant count.
RW
0h
15:14 Reserved (RSVD): Reserved
RO
1h
13:8 Device Non-posted (DEV_NP): IOMMU arbiter device grant count for NP.
RW
0h
7:6 Reserved (RSVD): Reserved
RO
1h
5:0 Device Posted (DEV_P): IOMMU arbiter device grant count for p.
RW
0h
31:22 Reserved (RSVD): Reserved
RO
1h
21:16 Class Count (CLASS_CNT): IOMMU arbiter class grant count.
RW
0h
15:14 Reserved (RSVD): Reserved
RO
1h
13:8 Device Non-posted (DEV_NP): IOMMU arbiter device grant count for NP.
RW
0h
7:6 Reserved (RSVD): Reserved
RO
1h
5:0 Device Posted (DEV_P): IOMMU arbiter device grant count for p.
RW
4h
31:24 Channel ID 3 (CHID3): Gazelle queue limit for Upstream NP on channel ID 3.
RW
4h
23:16 Channel ID 2 (CHID2): Gazelle queue limit for Upstream NP on channel ID 2.
RW
1h
15:8 Channel ID 1 (CHID1): Gazelle queue limit for Upstream NP on Channel ID 1.
RW
1h
7:0 Channel ID 0 (CHID0): Gazelle queue limit for Upstream NP on Channel ID 0.
RW
1h
31:24 Channel ID 7 (CHID7): Gazelle queue limit for Upstream NP on channel ID 7.
RW
1h
23:16 Channel ID 6 (CHID6): Gazellequeue limit for Upstream NP on channel ID 6.
RW
1h
15:8 Channel ID 5 (CHID5): Gazelle queue limit for Upstream NP on channel ID 5.
RW
1h
7:0 Channel ID 4 (CHID4): Gazelle queue limit for Upstream NP on channel ID 4.
RW
0h
31:0 SPARE RW Bits (SPARE_RW): Spare RW 32 bits in BIOSWR policy group.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
4h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
4h
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
Ch
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
4h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
4h
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
4h
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
0h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
7Fh
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
0h
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
0h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
7Fh
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
7Fh
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
0h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
4h
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
0h
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
0h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
4h
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
4h
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
0h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
4h
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
4h
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h
31:23 Reserved (RSVD): Reserved
RO
0h
22:16 Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for Chid.
RW
0h
15 Reserved (RSVD): Reserved
RO
4h
14:8 Non-Posted Max (NP_MAX): Max non-posted credits sent to PSF0 for Chid.
RW
0h
7 Reserved (RSVD): Reserved
RO
Ch
6:0 Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW
0h IMR enable (IMR_EN): IMR Enable: Enables access checking for the MOT region.
31 Note: this does not enable MOT itself merely enables access control checks for
RW transactions that attempt to access the MOT buffer.
0h Trace Enable (TR_EN): Asset Classification (AC)[0]: Trace Enable: Enables snooping
30 of transactions to the IMR region by tracing agents such as MOT. Reserved and set to 0
RO for the MOT region, since otherwise this would enable recursive
0h
29 Reserved (RSVD): Reserved
RO
MOT_OUT_BASE: Specifies bits 38:24 of the start address of the MOT memory
0h region. Region size must be a strict poweroftwo at least 16MB and naturally aligned to
28:14 the size. These bits are compared with the result of the MOT_OUT_MASK[28:14]
RW applied to bits 38:24 of the incoming address to determine if an access falls within the
MOT region.
0h
13:0 Reserved (RSVD): Reserved
RO
0h
29 Reserved (RSVD): Reserved
RO
0h MOT OUT Mask (MOT_OUT_MASK): Specifies the size of the MOT region. If
28:14 Request Address [38:24] ANDed with MOT_OUT_MASK[28:14] matches the
RW MOT_OUT_BASE[28:14] then the request falls within the MOT_OUT region
0h
13:0 Reserved (RSVD): Reserved
RO
C006101020 BIOS Control Policy (BIOSWR_CP): Bit vector used to determine which agents are
2h allowed access to the A-Unit BIOSWR Registers based on the value from the agents 6
63:0
bit SAI field. This register is selfreferential the access policy provided applies to access
RW to the control register itself.
80000C0063 BIOS Read Access Control (BIOSWR_RAC): Bit vector used to determine which
63:0 010217h agents are allowed Rd access to the A-Unit BIOSWR Register based on the value from
RW the agents 6 bit SAI field.
C006100021 BIOS Write Access Control (BIOSWR_WAC): Bit vector used to determine which
63:0 2h agents are allowed Wr access to the A-Unit BIOSWR registers based on the value from
RW the agents 6 bit SAI field.
0h
31:24 Reserved (RSVD): Reserved
RO
0h
15:8 Reserved (RSVD): Reserved
RO
0h
31:24 Reserved (RSVD): Reserved
RO
0h
15:8 Reserved (RSVD): Reserved
RO
0h
31:4 Reserved (RSVD): Reserved
RO
0h
31 reserved (UNDEFINED31): reserved for future use
RO
0h
30 reserved (UNDEFINED30): reserved for future use
RO
0h
29 reserved (UNDEFINED29): reserved for future use
RO
0h
28 reserved (UNDEFINED28): reserved for future use
RO
0h
27 reserved (UNDEFINED27): reserved for future use
RO
0h
26 reserved (UNDEFINED26): reserved for future use
RO
0h
25 reserved (UNDEFINED25): reserved for future use
RO
0h
24 reserved (UNDEFINED24): reserved for future use
RO
0h
23 reserved (UNDEFINED23): reserved for future use
RO
0h
22 reserved (UNDEFINED22): reserved for future use
RO
0h
21 reserved (UNDEFINED21): reserved for future use
RO
0h
19 reserved (UNDEFINED19): reserved for future use
RO
0h
18 reserved (UNDEFINED18): reserved for future use
RO
0h
17 reserved (UNDEFINED17): reserved for future use
RO
0h
16 reserved (UNDEFINED16): reserved for future use
RO
0h
15 reserved (UNDEFINED15): reserved for future use
RO
0h
14 reserved (UNDEFINED14): reserved for future use
RO
0h
13 reserved (UNDEFINED13): reserved for future use
RO
0h
12 reserved (UNDEFINED12): reserved for future use
RO
0h
11 reserved (UNDEFINED11): reserved for future use
RO
0h
10 msi rsvd set (MSI_RSVD_SET): An MSI was received with reserved bits set
RW/1C
0h
6 reserved (UNDEFINED5): reserved for future use
RO
1h
31 reserved (UNDEFINED31): reserved for future use
RO
1h
30 reserved (UNDEFINED30): reserved for future use
RO
1h
29 reserved (UNDEFINED29): reserved for future use
RO
1h
28 reserved (UNDEFINED28): reserved for future use
RO
1h
27 reserved (UNDEFINED27): reserved for future use
RO
1h
26 reserved (UNDEFINED26): reserved for future use
RO
1h
25 reserved (UNDEFINED25): reserved for future use
RO
1h
24 reserved (UNDEFINED24): reserved for future use
RO
1h
23 reserved (UNDEFINED23): reserved for future use
RO
1h
22 reserved (UNDEFINED22): reserved for future use
RO
1h
21 reserved (UNDEFINED21): reserved for future use
RO
1h
20 reserved (UNDEFINED20): reserved for future use
RO
1h
19 reserved (UNDEFINED19): reserved for future use
RO
1h
18 reserved (UNDEFINED18): reserved for future use
RO
1h
17 reserved (UNDEFINED17): reserved for future use
RO
1h
16 reserved (UNDEFINED16): reserved for future use
RO
1h
15 reserved (UNDEFINED15): reserved for future use
RO
1h
13 reserved (UNDEFINED13): reserved for future use
RO
1h
12 reserved (UNDEFINED12): reserved for future use
RO
1h
11 reserved (UNDEFINED11): reserved for future use
RO
1h
10 msi rsvd set (MSI_RSVD_SET): An MSI was received with reserved bits set
RW
1h
6 reserved (UNDEFINED5): reserved for future use
RO
3C00000000
MEM 64 bit [B:0, D:0, F:0] MCHBAR + 65C0h
h
LOCK: Intended usage is for BIOS to set the LOCK when it updates the CR. A-Unit
0h implements only storage for this bit. No hardware exists to implement hardware
63
RW locking. NOTE: B-Unit copy of this bit is used by ucode to protect WRMSR to the B-
Unit's CR. Ucode has no access to the A-Unit's copy of the CR.
0h
62:52 Reserved (RSVD): Reserved
RO
Channel Hash Mask (CH_HASH_MASK): When both PMI channels in a slice are
enabled, this field specifies the Channel Hash Mask to be applied on Addr[19:6]
postremap DRAM address of the request to compute which PMI channel a request must
0h be routed to. Relevant only when HVM mode is disabled and only for requests that do
51:38
RW not fall under the MOT region. B-Unit will override the programmed value to include the
Channel Selector bit See SLICEHASH.INTERLEAVE_MODE field. Note that HVM mode
and MOT regions have special hash requirements and hence they do not use the
CH_HASH_MASK.
0h
33 Reserved (RSVD): Reserved
RO
0h
30:20 Reserved (RSVD): Reserved
RO
Slice Hash Mask (SLICE_HASH_MASK): When both slices are enabled this field
specifies the Slice Hash Mask to be applied on Addr[19:6] physical address of the
request to compute which slice a request must be routed to. Relevant only when HVM
0h mode is disabled and only for physical addresses that do not fall under the Asymmetric
19:6
RW Memory Region and the MOT region. B-Unit will override the programmed value to
include the Slice Selector bit See INTERLEAVE_MODE field. Note that HVM mode
nonaddress IDI requests asymmetric memory region and MOT regions have special
hash requirements and hence they do not use the SLICE_HASH_MASK.
0h
5 Reserved (RSVD): Reserved
RO
0h
63:48 Reserved (RSVD): Reserved
RO
0h
31:16 Reserved (RSVD): Reserved
RO
0h MIRROR_BASE: Mirror Base: specifies b38:b23 of HPA indicating the start of mirror
15:0
RW packet buffer region
0h
18:15 Reserved (RSVD): Reserved
RO
0h
3:0 Reserved (RSVD): Reserved
RO
0h
18:15 Reserved (RSVD): Reserved
RO
0h
3:0 Reserved (RSVD): Reserved
RO
0h
30:28 Reserved (RSVD): Reserved
RO
0h
16:15 Reserved (RSVD): Reserved
RO
0h
3:2 Reserved (RSVD): Reserved
RO
0h
31:4 Reserved (RESERVED_0): Reserved
RO
ABSEGINDRAM: When this bit is set, reads and writes targeting A or Bsegments are
1h routed to DRAM. Asegment corresponds to the memory range 0xA_0000 to 0xA_FFFF.
2
RW Bsegment corresponds to the memory ranges 0xB_0000 to 0xB_7FFF and 0xB_8000 to
0xB_FFFF.
1h Read FSeg from DRAM (READ_FSEG_FROM_DRAM): When this bit is set, reads
1 targeting Fsegment are routed to DRAM. Fsegment corresponds to the memory range
RW 0xF_0000 to 0xF_FFFF.
1h Read ESeg from DRAM (READ_ESEG_FROM_DRAM): When this bit is set, reads
0 targeting Esegment are routed to DRAM. Esegment corresponds to the memory range
RW 0xE_0000 to 0xE_FFFF.
1h Security SAI Read Access Policy (SEC_SAI_POL_9): Bit vector used to determine
9 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_8): Bit vector used to determine
8 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_7): Bit vector used to determine
7 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_6): Bit vector used to determine
6 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_5): Bit vector used to determine
5 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_4): Bit vector used to determine
4 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_3): Bit vector used to determine
3 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_2): Bit vector used to determine
2 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
1h Security SAI Read Access Policy (SEC_SAI_POL_1): Bit vector used to determine
1 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h Security SAI Read Access Policy (SEC_SAI_POL_0): Bit vector used to determine
0 which agents are allowed read access to the B-Unit Security Group Configuration
RO registers based on each agent's 6bit encoded SAI value.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR0 Base (IMR0_BASE): Specifies bits 38:10 of the start address of IMR0
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR0MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR0
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR0 Mask (IMR0_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR0BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR0 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR1 Base (IMR1_BASE): Specifies bits 38:10 of the start address of IMR1
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR1MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR1
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR1 Mask (IMR1_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR1BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR1 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR2 Base (IMR2_BASE): Specifies bits 38:10 of the start address of IMR2
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR2MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR2
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR2 Mask (IMR2_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR2BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR2 region.
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR3RAC and IMR3WAC
registers.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR3 Base (IMR3_BASE): Specifies bits 38:10 of the start address of IMR3
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR3MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR3
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR3 Mask (IMR3_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR3BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR3 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
Asset Classification AC[0]: Trace Enable (TR_EN): Enables snooping of
30 RW
transactions to the IMR region by tracing agents.
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR4 Base (IMR4_BASE): Specifies bits 38:10 of the start address of IMR4
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR4MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR4
defined region.
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR4RAC and IMR4WAC
registers.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR4 Mask (IMR4_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR4BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR4 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR5 Base (IMR5_BASE): Specifies bits 38:10 of the start address of IMR5
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR5MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR5
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR5 Mask (IMR5_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR5BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR5 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR6 Base (IMR6_BASE): Specifies bits 38:10 of the start address of IMR6
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR6MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR6
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR6 Mask (IMR6_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR6BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR6 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR7 Base (IMR7_BASE): Specifies bits 38:10 of the start address of IMR7
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR7MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR7
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR7 Mask (IMR7_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR7BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR7 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR8 Base (IMR8_BASE): Specifies bits 38:10 of the start address of IMR8
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR8MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR8
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR8 Mask (IMR8_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR8BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR8 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR9 Base (IMR9_BASE): Specifies bits 38:10 of the start address of IMR9
0h region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally aligned
28:0 to the size. These bits are compared with the result of the IMR9MASK[28:0] applied to
RW bits 38:10 of the incoming address, to determine if an access falls within the IMR9
defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR9 Mask (IMR9_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR9BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR9 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR10 Base (IMR10_BASE): Specifies bits 38:10 of the start address of
0h IMR10 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR10MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR10 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR10 Mask (IMR10_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR10BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR10 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR11 Base (IMR11_BASE): Specifies bits 38:10 of the start address of
0h IMR11 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR11MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR11 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR11 Mask (IMR11_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR11BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR11 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR12 Base (IMR12_BASE): Specifies bits 38:10 of the start address of
0h IMR12 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR12MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR12 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR12 Mask (IMR12_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR12BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR12 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR13 Base (IMR13_BASE): Specifies bits 38:10 of the start address of
0h IMR13 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR13MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR13 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR13 Mask (IMR13_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR13BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR13 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR14 Base (IMR14_BASE): Specifies bits 38:10 of the start address of
0h IMR14 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR14MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR14 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR14 Mask (IMR14_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR14BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR14 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR15 Base (IMR15_BASE): Specifies bits 38:10 of the start address of
0h IMR15 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR15MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR15 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR15 Mask (IMR15_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR15BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR15 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
Base 0 IMR16 Base (IMR16_BASE): Specifies bits 38:10 of the start address of
0h IMR16 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR16MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR16 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR16 Mask (IMR16_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR16BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR16 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR17 Base (IMR17_BASE): Specifies bits 38:10 of the start address of
0h IMR17 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR17MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR17 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR17 Mask (IMR17_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR17BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR17 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR18 Base (IMR18_BASE): Specifies bits 38:10 of the start address of
0h IMR18 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR18MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR18 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR18 Mask (IMR18_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR18BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR18 region.
0h
31 IMR Enable (IMR_EN): Enables access checking for the IMR region.
RW
0h
29 Reserved (RESERVED_1): Reserved
RO
Base 0 IMR19 Base (IMR19_BASE): Specifies bits 38:10 of the start address of
0h IMR19 region. IMR region size must be a strict poweroftwo, at least 1KB, and naturally
28:0 aligned to the size. These bits are compared with the result of the IMR19MASK[28:0]
RW applied to bits 38:10 of the incoming address, to determine if an access falls within the
IMR19 defined region.
0h
29 Reserved (RESERVED_0): Reserved
RO
0h Mask 0 IMR19 Mask (IMR19_MASK): These bits are ANDed with bits 38:10 of the
28:0 incoming address to determine if the combined result matches the IMR19BASE[28:0]
RW value. A match indicates that the incoming address falls within the IMR19 region.
0h IMR Enable (IMR_EN): Enables access checking for the MOT region. Note: this does
31 not enable MOT itself, but merely enables access control checks for transactions that
RW attempt to access the MOT buffer.
0h
29 Reserved (RESERVED_1): Reserved
RO
MOT_OUT Base (MOT_OUT_BASE): Specifies bits 38:24 of the start address of the
0h MOT memory region. Region size must be a strict power of two, at least 16MB, and
28:14 naturally aligned to the size. These bits are compared with the result of the
RW MOT_OUT_MASK[28:14] applied to bits 38:24 of the incoming address to determine if
an access falls within the MOT region.
0h
13:0 Reserved (RESERVED_0): Reserved
RO
0h
29 Reserved (RESERVED_1): Reserved
RO
0h MOT Out Mask (MOT_OUT_MASK): Specifies the size of the MOT region. If Request
28:14 Address [38:24] ANDed with MOT_OUT_MASK[28:14] matches the
RW MOT_OUT_BASE[28:14] then the request falls within the MOT_OUT region.
0h
13:0 Reserved (RESERVED_0): Reserved
RO
FFFFFFFFFFF BM Read Access Policy (BM_READ_POL): Bit vector used to determine which
63:0 FFFFFh agents are allowed read access to all IMRxBASE and IMRxMASK registers, based on
RO each agent's 6bit encoded SAI value.
0h TPM Control Policy (CTRL_POL_63): Bit vector used to determine which agents are
63 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_62): Bit vector used to determine which agents are
62 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_61): Bit vector used to determine which agents are
61 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_60): Bit vector used to determine which agents are
60 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_59): Bit vector used to determine which agents are
59 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_58): Bit vector used to determine which agents are
58 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_57): Bit vector used to determine which agents are
57 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_56): Bit vector used to determine which agents are
56 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_55): Bit vector used to determine which agents are
55 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_54): Bit vector used to determine which agents are
54 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_53): Bit vector used to determine which agents are
53 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_52): Bit vector used to determine which agents are
52 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_51): Bit vector used to determine which agents are
51 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_50): Bit vector used to determine which agents are
50 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_49): Bit vector used to determine which agents are
49 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_48): Bit vector used to determine which agents are
48 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_47): Bit vector used to determine which agents are
47 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_46): Bit vector used to determine which agents are
46 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_45): Bit vector used to determine which agents are
45 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_44): Bit vector used to determine which agents are
44 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_43): Bit vector used to determine which agents are
43 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_42): Bit vector used to determine which agents are
42 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_41): Bit vector used to determine which agents are
41 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_40): Bit vector used to determine which agents are
40 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_39): Bit vector used to determine which agents are
39 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_38): Bit vector used to determine which agents are
38 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_37): Bit vector used to determine which agents are
37 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_36): Bit vector used to determine which agents are
36 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_35): Bit vector used to determine which agents are
35 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_34): Bit vector used to determine which agents are
34 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_33): Bit vector used to determine which agents are
33 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_32): Bit vector used to determine which agents are
32 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_31): Bit vector used to determine which agents are
31 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_30): Bit vector used to determine which agents are
30 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_29): Bit vector used to determine which agents are
29 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_28): Bit vector used to determine which agents are
28 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_27): Bit vector used to determine which agents are
27 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_26): Bit vector used to determine which agents are
26 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_25): Bit vector used to determine which agents are
25 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_24): Bit vector used to determine which agents are
24 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_23): Bit vector used to determine which agents are
23 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_22): Bit vector used to determine which agents are
22 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_21): Bit vector used to determine which agents are
21 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_20): Bit vector used to determine which agents are
20 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_19): Bit vector used to determine which agents are
19 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_18): Bit vector used to determine which agents are
18 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_17): Bit vector used to determine which agents are
17 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_16): Bit vector used to determine which agents are
16 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_15): Bit vector used to determine which agents are
15 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_14): Bit vector used to determine which agents are
14 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_13): Bit vector used to determine which agents are
13 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_12): Bit vector used to determine which agents are
12 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_11): Bit vector used to determine which agents are
11 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_10): Bit vector used to determine which agents are
10 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_9): Bit vector used to determine which agents are
9 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_8): Bit vector used to determine which agents are
8 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_7): Bit vector used to determine which agents are
7 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_6): Bit vector used to determine which agents are
6 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_5): Bit vector used to determine which agents are
5 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_4): Bit vector used to determine which agents are
4 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_3): Bit vector used to determine which agents are
3 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_2): Bit vector used to determine which agents are
2 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
1h TPM Control Policy (CTRL_POL_1): Bit vector used to determine which agents are
1 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
0h TPM Control Policy (CTRL_POL_0): Bit vector used to determine which agents are
0 allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI
RW value.
C006101020 TPM Access Policy (AC_POL): Bit vector used to determine which agents are
63:0 2h allowed read/write access to TPM_SELECTOR, based on each agent's 6-bit encoded SAI
RW value.
0h
31:5 Reserved (RESERVED_0): Reserved
RO
RS0 Asset Classification Bit for Graphics and Data Stolen Memory (RS0_EN):
PII transactions from RS0 that hit the Graphics and Data Stolen Memory range will be
1h allowed access only when both of the following conditions are met: a) Request SAI is in
4
RW the legal permitted list as specified in the RAC/WAC policy registers and b)
GSM_RS0_EN bit is set to 1. PII RS0 transactions targeting DRAM that do not hit any
enabled IMR or special protected regions will always be allowed access.
1h Range Check Enable (RANGE_CHECK_EN): Enables SAI checking for the memory
0
RW range from BGSM to TOLUD-1
0h
31:5 Reserved (RESERVED_0): Reserved
RO
0h RS0 Asset Classification Bit for SMM Region (RS0_EN): No PII transaction is
4 allowed access to SMM region. As such RS0 asset classification bit does not apply and
RO hence provisioned as a readonly bit and set to 0.
1h Range Check Enable (RANGE_CHECK_EN): Enables SAI checking for the SMM
0
RW memory range: TSEGMB to BGSM.
0h
31:5 Reserved (RESERVED_1): Reserved
RO
RS0 Asset Classification Bit for the High and Low VTd PMRs (RS0_EN): PII
transactions from RS0 that hit VTd PMR high and low memory ranges will be allowed
access only when both of the following conditions are met: a) Request SAI is in the
4 1h
legal permitted list as specified in the RAC/WAC policy registers and b)
RW VTDPMR_RS0_EN bit is set to 1. PII RS0 transactions targeting DRAM that do not hit
any enabled IMR or special protected regions will always be allowed access.
0h
0 Reserved (RESERVED_0): Reserved
RO
0h
27 Reserved (RESERVED_0): Reserved
RO
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
5:2 Reserved (RESERVED_1): Reserved
RO
0h MOT Buffer Wrap (MOT_BUFFER_WRAP): Indication that the MOT slice 0 buffer
0 has wrapped since the last clear of this write cleared by power good or explicit SW
RW/V write.
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
5:2 Reserved (RESERVED_1): Reserved
RO
0h MOT Buffer Wrap (MOT_BUFFER_WRAP): Indication that the MOT slice 1 buffer
0 has wrapped since the last clear of this write cleared by power good or explicit SW
RW/V write.
0h
31:27 Reserved (RESERVED_0): Reserved
RO
0h
25:0 Record ID (RECORD_ID): The current MOT unique record ID number.
RW/V
0h
31:27 Reserved (RESERVED_0): Reserved
RO
0h
25:0 Record ID (RECORD_ID): The current MOT unique record ID number.
RW/V
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
7FFFFFFFE0
MEM 64 bit [B:0, D:0, F:0] MCHBAR + 6BA8h
h
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
7FFFFFFFE0
MEM 64 bit [B:0, D:0, F:0] MCHBAR + 6BB8h
h
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
0h
63:35 Reserved (RESERVED_0): Reserved
RO
GT Match (GT_MATCH):
0h
18 • 1: Match
RW
• 0: Ignore
0h
63:35 Reserved (RESERVED_0): Reserved
RO
GT Match (GT_MATCH):
0h
18 • 1: Match
RW
• 0: Ignore
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
7FFFFFFFE0
MEM 64 bit [B:0, D:0, F:0] MCHBAR + 6BD8h
h
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
7FFFFFFFE0
MEM 64 bit [B:0, D:0, F:0] MCHBAR + 6BE8h
h
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
4:0 Reserved (RESERVED_1): Reserved
RO
0h
63:35 Reserved (RESERVED_0): Reserved
RO
GT Match (GT_MATCH):
0h
18 • 1: Match
RW
• 0: Ignore
0h
63:35 Reserved (RESERVED_0): Reserved
RO
GT Match (GT_MATCH):
0h
18 • 1: Match
RW
• 0: Ignore
0h
31:2 Reserved (RESERVED_0): Reserved
RO
3.424 B_CR_BIOSWR_WAC
(B_CR_BIOSWR_WAC_0_0_0_MCHBAR) — Offset 6C18h
This register configures the Write Access Policy for the BIOSWR security policy group.
The requesting agent's 6bit encoded SAI value is used as an index into this register's
bits to determine write access.
0h
31:4 Reserved (RESERVED_0): Reserved
RO
0h
3:0 OVERRIDE: Bit 0: When set overrides CSE SRAM destination. Bits 3:1 reserved.
RW
0h
31:2 Reserved (RESERVED_0): Reserved
RO
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_9):
9 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_8):
8 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_7):
7 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_6):
6 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
0h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_5):
5 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_4):
4 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
0h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_3):
3 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_2):
2 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_1):
1 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
1h B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy (IA_SAI_POL_0):
0 Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/
RO Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value.
0h
63:40 Reserved (RESERVED_0): Reserved
RO
0h
11:2 Reserved (RESERVED_1): Reserved
RO
0h LOCK: Locks the contents of the register including itself. Unused by the B-Unit, and
1 does not implement the intended lock functionality. B-Unit includes this bit to support
RW shadow copies of the register that rely on this lock bit.
0h
63:39 Reserved (RESERVED_0): Reserved
RO
0h
11:2 Reserved (RESERVED_1): Reserved
RO
0h LOCK: Locks the contents of the register, including itself. Unused by the B-Unit, and
1 does not implement the intended lock functionality. B-Unit includes this bit to support
RW shadow copies of the register that rely on this lock bit.
0h
11:10 Reserved (RESERVED_0): Reserved
RO
0h DWord Select (DWORD_SELECT): Selects the dword within the 512bit data field
7:4
RW that is compared for data mask/matches for Lites Group 0.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this field enables data
3
RW matching on Lites Group 0.
Enable Group (ENABLE_GROUP): Enables all match filters for Lites Group 0. The
following are the observation points that contain match filters: Badmit logic within each
0h slice after a transaction is successfully admitted into the B-Unit, U2C request launch,
0 PMI datain for each PMI channel for read data, PMI dataout for each PMI channel for
RW writes, data write from requesters to BRAM in each slice, and read data return on the
live bypass and nonlive bypass paths in each slice. To report a match at an observation
point, all match criteria for that point must be satisfied.
Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points, Badmit in both slices and the U2C request interface, use this same opcode
match register. Each bit, when set, enables a match on the corresponding opcode, and,
when clear, will suppress a match on the corresponding opcode. To match on any
opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_PicletReplay
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_PicletReplay
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_PicletReplay
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_PicletReplay
• Bit 19: C2U_Req_ItoM
0h
31:0 • Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
RW
• Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI_noPicletReplay
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI_noPicletReplay
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite_noPicletReplay
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW_noPicletReplay
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI_noPicletReplay
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI_noPicletReplay
0h GT Match (GT_MATCH): This field is used to match IDI transactions from GT for
31 Lites Group0. When set, enables a match for a transaction originating from GT. When
RW clear, suppresses a match for a transaction from GT.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
0h
38:3 Address Match (ADDRESS_MATCH): Address value to match for Lites.
RW
0h
2:0 Reserved (RESERVED_0): Reserved
RO
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR) — Offset
6CA8h
This register, together with the LITES0_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 0 address match on a transaction.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
Address Mask (ADDRESS_MASK): Address mask value used for comparing request
0h address during filter operation for Lites. If the mask bit in this register is 0, then the
38:3 corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the
RW corresponding bit in the ADDR_MATCH register must match the corresponding request
address bit for a match.
0h
2:0 Reserved (RESERVED_0): Reserved
RO
0h
31:0 Data Match (DATA_MATCH): Data value to match for Lites.
RW
Data Mask (DATA_MASK): Data mask value used for comparing data during filter
0h operations for Lites. If the mask bit in this register is 0, then the corresponding bit in
31:0 the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in
RW the DATA_MATCH register must match the corresponding bit of the request data for a
match.
0h
11:10 Reserved (RESERVED_0): Reserved
RO
0h DWord Select (DWORD_SELECT): Selects the dword within the 512bit data field
7:4
RW that is compared for data mask/matches for Lites Group 1.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this field enables data
3
RW matching on Lites Group 1.
Enable Group (ENABLE_GROUP): Enables all match filters for Lites Group 1. The
following are the observation points that contain match filters: Badmit logic within each
0h slice after a transaction is successfully admitted into the B-Unit, U2C request launch,
0 PMI datain for each PMI channel for read data, PMI dataout for each PMI channel for
RW writes, data write from requesters to BRAM in each slice, and read data return on the
live bypass and nonlive bypass paths in each slice. To report a match at an observation
point, all match criteria for that point must be satisfied.
Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points -- Badmit in both slices, and the U2C request interface -- use this same opcode
match register. Each bit, when set, enables a match on the corresponding opcode, and
when clear will suppress a match on the corresponding opcode. To match on any
opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_PicletReplay
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_PicletReplay
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_PicletReplay
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_PicletReplay
• Bit 19: C2U_Req_ItoM
0h
31:0 • Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
RW
• Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI_noPicletReplay
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI_noPicletReplay
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite_noPicletReplay
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW_noPicletReplay
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI_noPicletReplay
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI_noPicletReplay
0h GT Match (GT_MATCH): This field is used to match IDI transactions from GT for
31 Lites Group1. When set, enables a match for a transaction originating from GT. When
RW clear, suppresses a match for a transaction from GT.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
0h
38:3 Address Match (ADDRESS_MATCH): Address value to match for Lites
RW
0h
2:0 Reserved (RESERVED_0): Reserved
RO
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR) — Offset
6CD8h
This register, together with the LITES1_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 1 address match on a transaction.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
Address Mask (ADDRESS_MASK): Address mask value used for comparing request
0h address during filter operation for Lites. If the mask bit in this register is 0, then the
38:3 corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the
RW corresponding bit in the ADDR_MATCH register must match the corresponding request
address bit for a match.
0h
2:0 Reserved (RESERVED_0): Reserved
RO
0h
31:0 Data Match (DATA_MATCH): Data value to match for Lites.
RW
Data Mask (DATA_MASK): Data mask value used for comparing data during filter
0h operations for Lites. If the mask bit in this register is 0, then the corresponding bit in
31:0 the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in
RW the DATA_MATCH register must match the corresponding bit of the request data for a
match.
0h
11:10 Reserved (RESERVED_0): Reserved
RO
0h Dword Select (DWORD_SELECT): Selects the dword within the 512bit data field
7:4
RW that is compared for data mask/matches for Lites Group 2.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this field enables data
3
RW matching on Lites Group 2.
Enable Group (ENABLE_GROUP): Enables all match filters for Lites Group 2. The
following are the observation points that contain match filters: Badmit logic within each
0h slice after a transaction is successfully admitted into the B-Unit, U2C request launch
0 PMI datain for each PMI channel read data, PMI dataout for each PMI channel write
RW data, agent data write to BRAM in each slice, read data return on the live bypass and
nonlive bypass paths in each slice. To report a match at an observation point all match
criteria for that point must be satisfied.
Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points -- Badmit in both slices, and the U2C request interface -- use this same opcode
match register. Each bit, when set, enables a match on the corresponding opcode and
when clear will suppress a match on the corresponding opcode. To match on any
opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_PicletReplay
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_PicletReplay
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_PicletReplay
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_PicletReplay
• Bit 19: C2U_Req_ItoM
0h
31:0 • Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
RW
• Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI_noPicletReplay
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI_noPicletReplay
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite_noPicletReplay
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW_noPicletReplay
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI_noPicletReplay
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI_noPicletReplay
0h GT Match (GT_MATCH): This field is used to match IDI ransactions from GT for Lites
31 Group2. When set, enables a match for a transaction originating from GT. When clear,
RW suppresses a match for a transaction from GT.
VC Match (VC_MATCH): This field is used to match VC Channel ID, for PII
transactions for Lites Group2. Each bit, when set, enables a match for a transaction
originating from that VC. When clear, suppresses a match for a transaction from that
VC.
• Bit 30: VC14
• Bit 29: VC13
• Bit 28: VC12
• Bit 27: VC11
• Bit 26: VC10
0h • Bit 25: VC9
30:16
RW • Bit 24: VC8
• Bit 23: VC7
• Bit 22: VC6
• Bit 21: VC5
• Bit 20: VC4
• Bit 19: VC3
• Bit 18: VC2
• Bit 17: VC1
• Bit 16: VC0
0h
63:39 Reserved (RESERVED_1): Reserved
RO
0h
38:3 Address Match (ADDRESS_MATCH): Address value to match for Lites.
RW
0h
2:0 Reserved (RESERVED_0): Reserved
RO
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR) — Offset
6D08h
This register, together with the LITES2_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 2 address match on a transaction.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
Address Mask (ADDRESS_MASK): Address mask value used for comparing request
0h address during filter operation for Lites. If the mask bit in this register is 0, then the
38:3 corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the
RW corresponding bit in the ADDR_MATCH register must match the corresponding request
address bit for a match.
0h
2:0 Reserved (RESERVED_0): Reserved
RO
0h
31:0 Data Match (DATA_MATCH): Data value to match for Lites
RW
Data Mask (DATA_MASK): Data mask value used for comparing data during filter
0h operations for Lites. If the mask bit in this register is 0, then the corresponding bit in
31:0 the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in
RW the DATA_MATCH register must match the corresponding bit of the request data for a
match.
0h
11:10 Reserved (RESERVED_0): Reserved
RO
0h Dword Select (DWORD_SELECT): Selects the dword within the 512bit data field
7:4
RW that is compared for data mask/matches for Lites Group 3.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this field enables data
3
RW matching on Lites Group 3.
Enable Group (ENABLE_GROUP): Enables all match filters for Lites Group 3. The
following are the observation points that contain match filters Badmit logic within each
0h slice after a transaction is successfully admitted into the B-Unit U2C request launch
0 PMI datain for each PMI channel read data PMI dataout for each PMI channel write data
RW agent data write to BRAM in each slice read data return on the live bypass and nonlive
bypass paths in each slice. To report a match at an observation point all match criteria
for that point must be satisfied.
Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points -- Badmit in both slices, and the U2C request interface -- use this same opcode
match register. Each bit, when set, enables a match on the corresponding opcode, and
when clear will suppress a match on the corresponding opcode. To match on any
opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_PicletReplay
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_PicletReplay
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_PicletReplay
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_PicletReplay
• Bit 19: C2U_Req_ItoM
0h
31:0 • Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
RW
• Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI_noPicletReplay
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI_noPicletReplay
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite_noPicletReplay
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW_noPicletReplay
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI_noPicletReplay
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI_noPicletReplay
0h GT Match (GT_MATCH): This field is used to match IDI ransactions from GT for Lites
31 Group3. When set, enables a match for a transaction originating from GT. When clear,
RW suppresses a match for a transaction from GT.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
0h
38:3 Address Match (ADDRESS_MATCH): Address value to match for Lites.
RW
0h
2:0 Reserved (RESERVED_0): Reserved
RO
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR) — Offset
6D38h
This register, together with the LITES3_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 3 address match on a transaction.
0h
63:39 Reserved (RESERVED_1): Reserved
RO
Address Mask (ADDRESS_MASK): Address mask value used for comparing request
0h address during filter operation for Lites. If the mask bit in this register is 0, then the
38:3 corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the
RW corresponding bit in the ADDR_MATCH register must match the corresponding request
address bit for a match.
0h
2:0 Reserved (RESERVED_0): Reserved
RO
0h
31:0 DATA_MATCH: Data value to match for Lites
RW
Data Mask (DATA_MASK): Data mask value used for comparing data during filter
0h operations for Lites. If the mask bit in this register is 0, then the corresponding bit in
31:0 the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in
RW the DATA_MATCH register must match the corresponding bit of the request data for a
match.
0h Emon VC Mask (EMON_VC_MASK): B-Unit and T-Unit expose only the Emons
23:13
RW corresponding to the VC(s) specified in this field (it is a mask).
0h Emon IDI Mask (EMON_IDI_MASK): B-Unit and T-Unit expose only the Emons
12:5 corresponding to the IDI agent(s) specified in this field (it is a mask). IDI agent refers
RW to GLM modules and GT not Sunits.
0h Lites IDI Select (LITES_IDI_SELECT): B-Unit and T-Unit expose only the views
4:2 corresponding to the IDI agent specified in this field. IDI agents only refer to GT and
RW GLM modules, not Sunits. Used only on the C2U response views.
Lites PMI Select (LITES_PMI_SELECT): When set to 0, B-Unit exposes only PMI
0h channel 0 views in either slice. No Lites observability of any transaction routed to PMI
0
RW channel 1 in either slice. When set to 1, B-Unit exposes only PMI Channel 1 views in
either slice.
0h
31:30 Reserved (RESERVED_0): Reserved
RO
4h
29:24 Agent 3 Weight (AGENT3_WEIGHT): Arbiter weight for Agent 3.
RW
0h
23:22 Reserved (RESERVED_1): Reserved
RO
4h
21:16 Agent 2 Weight (AGENT2_WEIGHT): Arbiter weight for Agent 2.
RW
0h
15:14 Reserved (RESERVED_2): Reserved
RO
4h
13:8 Agent 1 Weight (AGENT1_WEIGHT): Arbiter weight for Agent 1.
RW
0h
7:6 Reserved (RESERVED_3): Reserved
RO
4h
5:0 Agent 0 Weight (AGENT0_WEIGHT): Arbiter weight for Agent 0.
RW
0h
31:30 Reserved (RESERVED_0): Reserved
RO
4h
29:24 Agent 7 Weight (AGENT7_WEIGHT): Arbiter weight for Agent 7.
RW
0h
23:22 Reserved (RESERVED_1): Reserved
RO
4h
21:16 Agent 6 Weight (AGENT6_WEIGHT): Arbiter weight for Agent 6.
RW
0h
15:14 Reserved (RESERVED_2): Reserved
RO
4h
13:8 Agent 5 Weight (AGENT5_WEIGHT): Arbiter weight for Agent 5.
RW
0h
7:6 Reserved (RESERVED_3): Reserved
RO
4h
5:0 Agent 4 Weight (AGENT4_WEIGHT): Arbiter weight for Agent 4.
RW
0h
31:30 Reserved (RESERVED_0): Reserved
RO
4h
29:24 Agent 3 Weight (AGENT3_WEIGHT): Arbiter weight for Agent 3.
RW
0h
23:22 Reserved (RESERVED_1): Reserved
RO
4h
21:16 Agent 2 Weight (AGENT2_WEIGHT): Arbiter weight for Agent 2.
RW
0h
15:14 Reserved (RESERVED_2): Reserved
RO
4h
13:8 Agent 1 Weight (AGENT1_WEIGHT): Arbiter weight for Agent 1.
RW
0h
7:6 Reserved (RESERVED_3): Reserved
RO
4h
5:0 Agent 0 Weight (AGENT0_WEIGHT): Arbiter weight for Agent 0.
RW
0h
31:30 Reserved (RESERVED_0): Reserved
RO
4h
29:24 Agent 7 Weight (AGENT7_WEIGHT): Arbiter weight for Agent 7.
RW
0h
23:22 Reserved (RESERVED_1): Reserved
RO
4h
21:16 Agent 6 Weight (AGENT6_WEIGHT): Arbiter weight for Agent 6.
RW
0h
15:14 Reserved (RESERVED_2): Reserved
RO
4h
13:8 Agent 5 Weight (AGENT5_WEIGHT): Arbiter weight for Agent 5.
RW
0h
7:6 Reserved (RESERVED_3): Reserved
RO
4h
5:0 Agent 4 Weight (AGENT4_WEIGHT): Arbiter weight for Agent 4.
RW
0h
31:30 Reserved (RESERVED_0): Reserved
RO
4h
29:24 Agent 11 Weight (AGENT11_WEIGHT): Arbiter weight for Agent 11.
RW
0h
23:22 Reserved (RESERVED_1): Reserved
RO
4h
21:16 Agent 10 Weight (AGENT10_WEIGHT): Arbiter weight for Agent 10.
RW
0h
15:14 Reserved (RESERVED_2): Reserved
RO
4h
13:8 Agent 9 Weight (AGENT9_WEIGHT): Arbiter weight for Agent 9.
RW
0h
7:6 Reserved (RESERVED_3): Reserved
RO
4h
5:0 Agent 8 Weight (AGENT8_WEIGHT): Arbiter weight for Agent 8.
RW
0h
31:30 Reserved (RESERVED_0): Reserved
RO
4h
29:24 Agent 15 Weight (AGENT15_WEIGHT): Arbiter weight for Agent 15.
RW
0h
23:22 Reserved (RESERVED_1): Reserved
RO
4h
21:16 Agent 14 Weight (AGENT14_WEIGHT): Arbiter weight for Agent 14.
RW
0h
15:14 Reserved (RESERVED_2): Reserved
RO
4h
13:8 Agent 13 Weight (AGENT13_WEIGHT): Arbiter weight for Agent 13.
RW
0h
7:6 Reserved (RESERVED_3): Reserved
RO
4h
5:0 Agent 12 Weight (AGENT12_WEIGHT): Arbiter weight for Agent 12.
RW
FFh Flush Threshold (FLUSH_THRESHOLD): All write commands are blocked at Badmit
31:24
RW if the number of write commands in the Flush Pool exceeeds this value.
0h
23:17 Reserved (RESERVED_0): Reserved
RO
0h Dirty Low Water Mark (DIRTY_LWM): Low water mark for dirty entries retained by
15:8 the B-Unit. B-Unit will immediately attempt to flush any dirty entry, hence setting the
RW low water mark to 0.
0h Dirty High Water Mark (DIRTY_HWM): High water mark for dirty entries retained
7:0 by the B-Unit. B-Unit will immediately attempt to flush any dirty entry, hence setting
RW the low water mark to 0.
0h
30:14 Reserved (RESERVED_1): Reserved
RO
0h
7:0 Reserved (RESERVED_0): Reserved
RO
0h
30:14 Reserved (RESERVED_1): Reserved
RO
0h
7:6 Reserved (RESERVED_0): Reserved
RO
0h Enable DRAM Read for Partial Write (ENABLE_DRAM_READ): The B-Unit has
30 byte enable capability, so it doesn't require a DRAM read when there is a partial write.
RW This bit forces it to perform the read anyway.
0h
29:26 Reserved (RESERVED_2): Reserved
RO
DRAM_ECC_ENABLE: If DRAM ECC is enabled, the data error bits from the Dunit is
0h used for indicating the derror for the corresponding transactions to the agents and
25
RW forcing the poison bit when BUNIT PARITY is unsupported and Read for partial writes
are enabled
0h Casual Timer (CASUAL_TIMER): The number of clock cycles that the B-Unit waits
15:8 before starting a casual dirty flush. Casual Flush feature will not be enabled by PND2
RW architecture. Instead, a dirty write will be made eliGBle for scheduling immediately.
0h
7:6 Reserved (RESERVED_1): Reserved
RO
1h Enable 64B Write (ENABLE_64B_WRITE): When set, B-unit will send 64B PMI
5 Write requests for transactions requiring write access to DRAM. Must always be set to
RW one, otherwise functional errors may occur.
1h Enable 64B Read (ENABLE_64B_READ): When set, B-unit will send 64B PMI read
4 requests for transactions requiring read access to DRAM. Must always be set to one,
RW otherwise functional errors may occur.
0h Dirty Stall (DIRTY_STALL): This mode causes reads or writes from any requester
0 interface to dirty valid B-Unit buffer entries to stall on the appropriate requester
RW interface until the entry has been flushed from the B-Unit.
0h
31:21 Reserved (RESERVED_0): Reserved
RO
0h
31:17 Reserved (RSVD): Reserved
RO
IDI Agent Real-Time Traffic Mask Bits (RT_IDI_AGENT): IDI Agent Real-Time
0h Traffic Mask Bits. Controls which IDI Agent supports Real-Time Traffic/Transactions.
16 Only one IDI Agent needs to be selected for real-time traffic. Currently we don't
RW support multiple IDI agents to be enabled for real-time traffic at the same time. This
field will be active only when Bit 0:RT_ENABLE is set to '1'
0h
15:1 Reserved (RSVD): Reserved
RO
0h
0 Real-Time Enable (RT_ENABLE): Global enable bit for Real-Time Support
RW
0h
31:9 Reserved (RSVD): Reserved
RO
0h
18:15 Reserved (RSVD): Reserved
RO
0h
3:0 Reserved (RSVD): Reserved
RO
0h
18:15 Reserved (RSVD): Reserved
RO
0h
3:0 Reserved (RSVD): Reserved
RO
0h
31:1 Reserved (RESERVED_0): Reserved
RO
Machine Check Signal Mode (MC_SIGNAL_MODE): When set to 1, B-Unit will not
allow any transaction with uncorrectable error or subsequent memory transaction to
0h propagate through to Requester. This will essentially hang CPU and CPU will end up
0 with IERR shutdown. Issue: When set to zero B-Unit will allow transaction with an
RW uncorrectable error to propagate and signal MC event to CPU if enabled in
IA32_MC5_CTL. If enabled MC event will be taken by CPU cores at the end of
instruction boundary after it detected by ROB
0h
31:0 Reserved (RESERVED_0): Reserved
RO
0h
30:28 Reserved (RSVD): Reserved
RO
0h
16:15 Reserved (RSVD): Reserved
RO
0h
1:0 Reserved (RSVD): Reserved
RO
0h
31:1 Reserved (RESERVED_0): Reserved
RO
0h
31:0 DATA: This field contains the low 32 bits of data associated with specific commands.
RW/V
0h
31:0 DATA: This field contains the low 32 bits of data associated with specific commands.
RW/V
Run/Busy (RUN_BUSY): The run/busy control is used for managing the semaphore
on the mailbox interface. Typical usage involves the following flow:
• Software waits for the interface run/busy bit to clear.
• Software writes the mailbox data registers as appropriate for this command.
• Software writes a command encoding and sets the run/busy bit in the interface
register.
0h • Software waits for the interface run/busy bit to clear to indicate the command has
31 been handled.
RW/1S/V
• Software queries the completion code in the command field of the interface
register to ensure it passed (0b indicates pass)
Bit encoding for the run/busy:
• 0 = The thermal mailbox is idle or the last request has been completed. Software
may initiate new requests.
• 1 = The thermal mailbox is busy. The thermal device is still handling a request.
Writes to thermal mailbox are not allowed at this time.
0h
30:29 Reserved (RSVD): Reserved
RO
COMMAND: For incoming requests (where run/busy=1), this field represents the
0h command opcode. For responses (where run/busy=0), this field represents the
7:0 response completion code. A completion code of 0b indicates passing, all other
RW/V completion codes indicate failure. For detailed definition of services provided by this
mailbox, see the full mailbox specification.
0h LOCK: Used to lock P_CR_INTR_LAT_0_0_1_PCI.INTPIN. BIOS should set this lock bit
31
RW/L before passing control to the OS
0h
30:8 RESERVED: Reserved
RO
0h IRQ: IRQ vector number for the thermal / power device. This field controls the event
7:0 vector issues to the IOAPIC. It must be configured by BIOS for INTA support.
RW Recommended setting for Broxton is 24 (18h)
0h
31 Reserved (RSVD): Reserved
RO
0h
7:3 Reserved (RSVD): Reserved
RO
0h
31:24 Reserved (RSVD): Reserved
RO
0h
15:6 Reserved (RSVD): Reserved
RO
0h
31:6 RESERVED_0: Reserved
RO
0h
31:6 RESERVED_0: Reserved
RO
0h
31 CATERR: Asserted by HW on IERR or MCERR assertion.
RW/V
0h
30 IERR: Asserted by HW on IERR assertion.
RW/V
0h
29 MCERR: Asserted by HW on MCERR assertion.
RW/V
0h
28:8 Reserved (RSVD): Reserved
RO
0h
7:0 RESERVED: Reserved
RW
0h
31:26 RESERVED_1: Reserved
RO
0h
15:10 RESERVED_0: Reserved
RO
0h
7 Reserved (NM_THERM_THRT_ENABLE): Reserved
RW/V
0h
6:4 Reserved (NM_THERM_THRT_THRESHOLD): Reserved
RW/V
0h
31 Reserved (RSVD): Reserved
RO
0h
23:16 Reserved (RSVD): Reserved
RO
0h
15 Reserved (NEAR_MEM_MR4_THRESHOLD2_INT_ENABLE): Reserved
RW
0h
14:12 Reserved (NEAR_MEM_MR4_THRESHOLD2): Reserved
RW
0h
11 Reserved (NEAR_MEM_MR4_THRESHOLD1_INT_ENABLE): Reserved
RW
0h
10:8 Reserved (NEAR_MEM_MR4_THRESHOLD1): Reserved
RW
0h
31:22 Reserved (RSVD): Reserved
RO
0h
21:19 Reserved (NEAR_MEM_MR4): Reserved
RO/V
0h
15:8 Reserved (RSVD): Reserved
RO
0h
7 Reserved (NEAR_MEM_MR4_THRESHOLD2_LOG): Reserved
RW/0C/V
0h
6 Reserved (NEAR_MEM_MR4_THRESHOLD2_STATUS): Reserved
RO/V
0h
5 Reserved (NEAR_MEM_MR4_THRESHOLD1_LOG): Reserved
RW/0C/V
0h
4 Reserved (NEAR_MEM_MR4_THRESHOLD1_STATUS): Reserved
RO/V
0h JOULES: Total Joules of energy consumed by all DIMMs. Units are proportional to
31:0
RO/V Joules and are defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT.
Performance Throttle Duration (COUNTS): Time that any core in the IA domain is
0h performance throttled below OS request and below the base frequency (P1) because of
31:0
RW power limits (PL1 or PL2). Counts in time units defined by
PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT
0h
31:5 RESERVED_0: Reserved
RO
0h IA Core Priority Level (PRIPTP): Performance priority Level for the IA Core
4:0
RW (primary) power plane. A higher number implies a higher priority.
0h
31:5 RESERVED_0: Reserved
RO
10h Graphics Priority Level (SECPTP): Performance priority Level for the Graphics
4:0
RW (secondary) power plane. A higher number implies a higher priority.
3.503 PACKAGE_POWER_SKU_UNIT
(P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR) —
Offset 7068h
Defines units for calculating SKU power, current, energy, resistance and timing
parameters.
RESISTANCE_UNIT: Used to define the units of resistance for control registers that
3h describe parameters in ohms such as VR_CURRENT_CONFIG. The actual unit value is
31:28
RW calculated by 1mohm / 2^RESISTANCE_UNIT. The default value of 3 corresponds to
0.125mohm.
0h
23:20 RESERVED_2: Reserved
RSV
Ah TIME_UNIT: Used for to define the time units in registers such as PL1, PL2, PL3 and
19:16 PL4. The actual unit value is calculated by 1s / 2^TIME_UNIT. The default value of 10
RW corresponds to 0.977ms.
0h
15:13 RESERVED_1: Reserved
RSV
0h
7:4 RESERVED_0: Reserved
RSV
8h PWR_UNIT: Used to define the units of power control registers such as PL1, PL2, PL3
3:0 and PL4. The actual unit value is calculated by 1 W / 2^PWR_UNIT. The default value of
RW 8 corresponds to 3.9mW per bit.
SOC Energy Counter (DATA): Contains accumulated energy consumed by the entire
0h CPU. This counter will wrap around and keep counting when the counter overflows.
31:0
RO/V Units are proportional to Joules exact precsion is defined by
PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT
3.505 GT_PERF_STATUS
(P_CR_GT_PERF_STATUS_0_0_0_MCHBAR) — Offset
7070h
Contains the voltage and ratio status for GT. This register is mapped to
GT_PERF_STATUS_0_0_0_MCHBAR.
0h
31:26 Reserved (RSVD): Reserved
RO
0h
7:0 RP_STATE_VOLTAGE: RP-State Voltage GT Target Voltage in U1.7 Volts
RO/V
0h
31 Reserved (RSVD): Reserved
RO
0h
7:0 Reserved (RSVD): Reserved
RO
0h
31:16 RESERVED0: Reserved
RW
Stage7 Pcode Reset Complete (PCODE_INIT_DONE7): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
15
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
Stage6 Pcode Reset Complete (PCODE_INIT_DONE6): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
14
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
Stage5 Pcode Reset Complete (PCODE_INIT_DONE5): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
13
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
Stage4 Pcode Reset Complete (PCODE_INIT_DONE4): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
12
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
Stage3 Pcode Reset Complete (PCODE_INIT_DONE3): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
11
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
Stage2 Pcode Reset Complete (PCODE_INIT_DONE2): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
10
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
Stage1 Pcode Reset Complete (PCODE_INIT_DONE1): Pcode sets this bit when
0h it has completed this stage, BIOS must wait for this bit to be set before proceeding to
9
RO/V the next stage. Stage validity is product-specific and this stage may not be applicable
to this product.
0h
7 Stage7 BIOS Reset Complete (RST_CPL7): reset complete
RW
Stage6 BIOS Reset Complete (RST_CPL6): BIOS sets this bit when it has
0h completed this stage, Pcode must wait for this bit to be set before proceeding to the
6
RW next stage. Stage validity is product-specific and this stage may not be applicable to
this product.
Stage5 BIOS Reset Complete (RST_CPL5): BIOS sets this bit when it has
0h completed this stage, Pcode must wait for this bit to be set before proceeding to the
5
RW next stage. Stage validity is product-specific and this stage may not be applicable to
this product.
Stage4 BIOS Reset Complete (RST_CPL4): BIOS sets this bit when it has
0h completed this stage, Pcode must wait for this bit to be set before proceeding to the
4
RW next stage. Stage validity is product-specific and this stage may not be applicable to
this product.
Stage3 BIOS Reset Complete (RST_CPL3): BIOS sets this bit when it has
0h completed this stage, Pcode must wait for this bit to be set before proceeding to the
3
RW next stage. Stage validity is product-specific and this stage may not be applicable to
this product.
Stage2 BIOS Reset Complete (RST_CPL2): BIOS sets this bit when it has
0h completed this stage, Pcode must wait for this bit to be set before proceeding to the
2
RW next stage. Stage validity is product-specific and this stage may not be applicable to
this product.
Stage1 BIOS Reset Complete (RST_CPL1): BIOS sets this bit when it has
0h completed this stage, Pcode must wait for this bit to be set before proceeding to the
1
RW next stage. Stage validity is product-specific and this stage may not be applicable to
this product.
Stage0 BIOS Reset Complete (RST_CPL): Set by BIOS to indicate that all power
management configurations as part of reset are complete. This must include Punit
0h patch load done as well as all relevant Punit power management register and mailbox
0 configurations done. Once this bit is set, Punit will allow normal power management to
RW start. Before setting this bit, P-states and C-states support is disabled. BIOS should
wait before receiving the Pcode Stage0 reset complete before proceeding with any
further steps.
3.508 BIOS_MAILBOX_DATA
(P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR) — Offset
7080h
Data register for the BIOStoPCODE mailbox. This mailbox is implemented as a means
for accessing statistics and implementing BIOS-Pcode handshakes. This register is used
in conjunction with BIOS_MAILBOX_INTERFACE. THIS REGISTER IS DUPLICATED IN
THE PCU IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
0h
31:0 DATA: This field contains the data associated with specific commands.
RW/V
3.509 BIOS_MAILBOX_INTERFACE
(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR) —
Offset 7084h
Control and Status register for the BIOStoPCODE mailbox. This mailbox is implemented
as a means for accessing statistics and implementing BIOS-Pcode handshakes. This
register is used in conjunction with BIOS_MAILBOX_DATA. THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
RUN_BUSY: SW may write to the two mailbox registers only when RUN_BUSY is
0h clear(0). Setting RUN_BUSY to 1 will pend a Fast Path event to Pcode. After setting this
31
RW/1S/V bit SW will poll this bit until it is cleared. PCODE will clear RUN_BUSY after updating the
mailbox registers with the result and error code.
0h
30:29 Reserved (RSVD): Reserved
RO
0h COMMAND: This field contains the SW request command or the PCODE response
7:0
RW/V code depending on the setting of RUN_BUSY.
3.510 CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBA
R) — Offset 7088h
PUNIT_MMIO: Core Frequency Capabilities This register describes the frequency
capabilities of the IA cores. Units are 100MHz multiplied by the ratio. Minimum and
maximum ratio fields are initialized by pCode at reset. Last resolved ratio is updated
upon changes to the processing system frequency. The efficient ratio is determined by
firmware and may be updated dynamically depending on firmware support.
0h LAST_RESOLVED_FREQ: Last resolved ratio for the IA cores. Units are 100MHz
31:24 multiplied by the ratio. This value is updated dynamically whenever the IA core
RO/V frequency changes.
3.511 GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_M
CHBAR) — Offset 708Ch
PUNIT_MMIO: Graphics Engine Frequency Capabilities This register describes the
frequency capabilities of the integrated graphics engine. Units are 16.67MHz multiplied
by the ratio. Minimum and maximum ratio fields are initialized by pCode at reset. Last
resolved ratio is updated upon changes to the integrated graphics engine frequency.
The efficient ratio is determined by firmware and may be updated dynamically
depending on firmware support.
3.512 SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0
_0_MCHBAR) — Offset 7090h
PUNIT_MMIO: System Agent Frequency Capabilities This register describes the
frequency capabilities of the System Agent. Units are 16.666MHz multiplied by the
ratio. Last resolved ratio is updated upon changes to the System Agent frequency.
0h
31:24 LAST_RESOLVED_RATIO: Last resolved System Agent ratio, in units of 16.666MHz.
RO/V
0h
23:16 MAX_RATIO: max ratio
RO/V
0h
15:8 RESERVED_1: Reserved
RO/V
0h
7:0 MIN_RATIO: min ratio
RO/V
0h
23:16 RESERVED_2: Reserved
RO/V
0h
15:8 RESERVED_1: Reserved
RO/V
0h
7:0 RESERVED_0: Reserved
RO/V
0h
47 RESERVED_2: Reserved
RO
0h
31 RESERVED_1: Reserved
RO
0h
15 RESERVED_0: Reserved
RO
0h PKG_TDP: The TDP package power setting allowed for the SKU. The TDP setting is
14:0 typical not guaranteed. The default value for this field is determined by fuses. The units
RW for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].
limits. A lock mechanism allow the software agent to enforce power limit settings. Once
the lock bit is set, the power limit settings are static and un-modifiable until next
RESET.
0h Package RAPL Lock (PKG_PWR_LIM_LOCK): When set all settings in this register
63 are locked and are treated as Read Only. This lock control is persistent until the next
RW/L reset. This bit will typically set by BIOS during boot time or resume from Sx.
0h
62:56 RESERVED_1: Reserved
RSV
Power Limit 2 (PL2) Clamp (PKG_CLMP_LIM_2): Clamp mode control for PL2.
• 0 = PL2 power control is prevented from forcing P-states below the base frequency
/ P1 for any domain in the SOC.
0h • 1 = PL2 power control will take all actions necessary to meet the power target,
48
RW/L even if that involves running at clock frequencies below the base frequency / P1
level.
In order to ensure proper SOC cooling, it is generally recommended that the clamp
mode is always enabled.
Power Limit 2 (PL2) (PKG_PWR_LIM_2): Sets the average power usage limit of
the package domain corresponding to the PL2 time window. The power units of this
0h field are specified by the PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT. This power
46:32
RW/L limit must be configured by software before it will engage. The PL2 limit is most
commonly associated with long time windows (1s and longer), although there are no
explicit constraints on what software configures.
0h
31:24 RESERVED_0: Reserved
RSV
Power Limit 1 (PL1) Clamp (PKG_CLMP_LIM_1): Clamp mode control for PL1.
• 0 = PL1 power control is prevented from forcing P-states below the base frequency
/ P1 for any domain in the SOC.
0h • 1 = PL1 power control will take all actions necessary to meet the power target,
16
RW/L even if that involves running at clock frequencies below the base frequency / P1
level.
In order to ensure proper SOC cooling, it is generally recommended that the clamp
mode is always enabled.
Power Limit 1 (PL1) (PKG_PWR_LIM_1): Sets the average power usage limit of
the package domain corresponding to the PL1 time window. The power units of this
0h field are specified by the PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT. This power
14:0
RW/L limit must be configured by software before it will engage. The PL1 limit is most
commonly associated with long time windows (1s and longer), although there are no
explicit constraints on what software configures.
3.516 IA_PERF_LIMIT_REASONS
(P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR) —
Offset 70B0h
Interface to allow software to determine what is causing resolved frequency to be
clamped below the requested frequency. Status bits are updated by Punit firmware
every millisecond and log bits are set upon observing the corresponding status bit
being set. Software may clear log bits to track performance limit reasons inbetween
reads of this register.
QOS_LOG: Sticky log bit corresponding to the associated status bit in the lower 16
31 0h
bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
RW/0C/V
0h EDP_LOG: Sticky log bit corresponding to the associated status bit in the lower 16
28
RW/0C/V bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h DEV3_LOG: Sticky log bit corresponding to the associated status bit in the lower 16
24
RW/0C/V bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h DEV2_LOG: Sticky log bit corresponding to the associated status bit in the lower 16
23
RW/0C/V bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h PL2_LOG: Sticky log bit corresponding to the associated status bit in the lower 16
19
RW/0C/V bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h PL1_LOG: Sticky log bit corresponding to the associated status bit in the lower 16
18
RW/0C/V bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h THERMAL_LOG: Sticky log bit corresponding to the associated status bit in the lower
17
RW/0C/V 16 bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h PROCHOT_LOG: Sticky log bit corresponding to the associated status bit in the lower
16
RW/0C/V 16 bits. Set by hardware when the status bit asserts. Cleared by software write of zero.
0h
15 QOS_STATUS: Frequency is limited below the quality of service level.
RO/V
0h
10 VR_THERMALERT_STATUS: Frequency is limited due to a VR thermal excursion.
RO/V
0h
8 DEV3_STATUS: Frequency is limited due to camera (device3) driver override.
RO/V
0h
7 DEV2_STATUS: Frequency is limited due to graphics (device2) driver override.
RO/V
0h
3 PL2_STATUS: Frequency is limited due to a package-level RAPL PL2 excursion.
RO/V
0h
2 PL1_STATUS: Frequency is limited due to a package-level RAPL PL1 excursion.
RO/V
0h
1 THERMAL_STATUS: Frequency is limited due to thermal excursion.
RO/V
0h C0 Residency (DATA): This counter measures time that any core is active in the C0
31:0
RO/V state. This counter counts at the crystal clock frequency divided by 16.
0h C0 Residency (DATA): This counter measures time that graphics is active in the C0
31:0
RO/V state. This counter counts at the crystal clock frequency divided by 16.
0h C0 Residency (DATA): This counter measures time that I-unit processing system is
31:0
RO/V active in the C0 state. This counter counts at the crystal clock frequency divided by 16.
3.520 TELEM_IA_FREQ_ACCUMULATOR
(P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR
) — Offset 70CCh
Frequency accumulation data counted at ART >> 4
0h
31:0 DATA: Residency data
RO/V
0h Clock Ratio Multiplier Accumulator (DATA): This counter integrates the current
31:0
RO/V clock ratio of the domain at the same rate as the corresponding C0 residency counter
0h Clock Ratio Multiplier Accumulator (DATA): This counter integrates the current
31:0
RO/V clock ratio of the domain at the same rate as the corresponding C0 residency counter
DATA: This counter measures the total time spent with memory active, as measured
0h by any rank being in the active or active idle state. The inverse of this counter indicates
63:0
RO/V the total time spent with all memory in the self-refresh state. This counter counts at
the crystal clock frequency divided by 16.
0h
31:9 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (NUM_NM_CH): Reserved
RW
0h
29:24 Reserved (WIO_FREQ): Reserved
RW
• P-unit firmware executes the initial configuration of PHY settings, and when
complete it clears Run/Busy bit
• BIOS executes DDR PHY static configuration flow and initializes PHY PLL, and
ensures that both steps are complete
• BIOS sets MC_BIOS_REQ.PHY_CONFIG_COMPLETE and MC_BIOS_REQ.RUN_BUSY
to start the next phase
• P-unit firmware initiates the power-up sequence for D-units and Wide I/O collateral
logic.
• P-unit firmware sets MC_BIOS_REQ.DUNIT_RESET_COMPLETE and clears the Run/
Busy when it is done.
• BIOS observes Run/Busy deassertion and continues with MRC flow to initilize, train,
configure memory subsystem settings.
• BIOS sets MC_BIOS_REQ.CPGC_MODE_COMPLETE and MC_BIOS_REQ.RUN_BUSY
to start the next phase
• P-unit firmware configures D-unit, PHY to support normal operation of memory
subsystem, and when completed, clears the Run/Busy bit
• BIOS waits for MC_BIOS_REQ.RUN_BUSY to clear, and then complete remaining
configuration of Dunit and MLMC.
• BIOS executes memory configuration validation and lock sequence with the CSE.
• BIOS sets MC_BIOS_REQ.MEM_INIT_DONE and MC_BIOS_REQ.RUN_BUSY to
indicate to Punit that all memory configuration is complete and memory
configuration is locked.
Run/Busy (RUN_BUSY): This bit indicates that the BIOS request is pending for P-
unit firmware processing. BIOS sets this bit together with command details defined in
the lower bits of this register. Firmware may only clear this bit after the BIOS request
0h has been observed and completed.
31
RW • 0 = The MC BIOS reset mailbox is idle or the last request has been completed.
Software may initiate new requests.
• 1 = The MC BIOS reset mailbox is busy. It is still handling a request. Writes to the
mailbox are not allowed at this time.
0h
30:27 RESERVED_2: Reserved
RW
0h
23:20 RESERVED_1: Reserved
RW
0h Memory Init Done (MEM_INIT_DONE): BIOS programs this bit after memory
19
RW subsystem is fully configured, including security locking configuration completed
0h
11 RESERVED_2 (WIO_ONLY): Reserved
RW
0h
10 RESERVED_0: Reserved
RW
0h
9 RESERVED_3 (REQ_TYPE_SPECIAL): Reserved
RW
Request Type (REQ_TYPE): This field is used to configure reset hints to the P-unit
firmware. Encodings include:
0h
8:6 • 1xxb = Memory is in self-refresh, manual self-refresh exit is required
RW
• 0xxb = Memory is not in self-refresh or DRAM contents do not need to be
preserved.
3.528 P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR
— Offset 7118h
Describes the maximum frequency capabilities of DDR supported and DDR
configuration on this particular SOC. If the maximum supported frequency reports a
zero, it indicates that the respective DRAM technology is not supported on this product.
0h
31:25 RESERVED_2: Reserved
RW
3.529 PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
(P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR) — Offset
7160h
GT RC0 residency counter. Holds the accumulated number of CS clks that GT has been
in RC0.
0h
31:0 DATA: Accumulated cycles GT has been in RC0.
RO/V
0h
31:4 Reserved (RSVD): Reserved
RO
0h
3 CORE3_EXISTS: Indication of core physical presence
RW
0h
2 CORE2_EXISTS: Indication of core physical presence
RW
0h
1 CORE1_EXISTS: Indication of core physical presence
RW
0h
0 CORE0_EXISTS: Indication of core physical presence
RW
• Cold boot
• BIOS reads CORE_EXISTS_VECTOR to establish which modules and cores are
present
• BIOS writes 1b to the corresponding core that it wishes to disable.
• BIOS may disable entire modules by writing 1b to a pair of cores.
• The results of the configuration are maintained in the sustain power well.
• BIOS initiates a cold reset flow at the platform. In a cold reset, the sustain power
well maintains power most other rails are power cycled.
• On cold reset exit, Punit firmware inspects the core configuration and launches only
the cores requested by BIOS. To software, it will appear as if these cores do not
exist.
0h
31:4 Reserved (RSVD): Reserved
RO
0h
3 CORE3_DISABLE_MASK: core3 disable mask
RW
0h
2 CORE2_DISABLE_MASK: core2 disable mask
RW
0h
1 CORE1_DISABLE_MASK: core1 disable mask
RW
0h
0 CORE0_DISABLE_MASK: core0 disable mask
RW
• PL3 is designed to clamp peak sustained power to levels supported by the battery
or input power supply and as such manage lifetime degradation of that power
delivery element. With PL3, peak power excursions above the limit are allowed so
long as they do not exceed the configured duty cycle constraint in this register.
• PL4 is designed to clamp peak instantaneous power to levels below the max
supported by the battery or input power supply. These clamps are implemented a
priori and the SOC is guaranteed to constrain itself below the PL4 limit always.
0h LOCK: Write a 1b to lock this register until next reset. Once locked, no further updates
63
RW/L may be written to any bits in the register.
0h
62:48 Reserved (RSVD): Reserved
RO
0h PL4 Max Power (PMAX): Power Limit 'PL4' or Pmax power limit in the units as
46:32 described PACAKGE_POWER_SKU_UNIT MSR. The SOC guarantees it will never exceed
RW/L this power limit even for very short time windows.
0h
31 Reserved (RSVD): Reserved
RO
PL3 Duty Cycle (DUTY_CYCLE): Power limit excursion duty cycle control for PL3,
describing what percentage of time it is allowed for the SOC to exceed the
0h programmed PL3 power limit. 0% implies excursions are not supported ever and 100%
30:24
RW/L implies excursions are always allowed (effectively disabling the feature). Units are in
percentage(%). E.g., to allow for 20% excursion time and 80% PL3 power limit clamp
time, program a value of 14h. Values greater than 100 (64h) are clipped to 100%.
PL3 Time Window (TIME_WINDOW): Duration over which duty cycle control will
be maintained. The bits of this field describe parameters for a mathematical equation
for time window configuration. This time window is strictly adhered to, if the window
described is 40ms, then silicon guarantees no excursions to the programmed duty
0h cycle within a rolling 40ms window. This field is split into two sub-fields:
23:17
RW/L • x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)
0h
16 Reserved (RSVD): Reserved
RO
PL3 Power Limit (POWER_LIMIT): Power Limit 3 (PL3) or PAppMax power level.
0h Any SOC power measurement observed above this level is considered as an excursion
14:0
RW/L against the PL3 power limit and duty cycle / time window budget. Units of this power
limit are defined by PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT.
0h
31:6 RESERVED_0: Reserved
RO
0h
31:6 RESERVED_0: Reserved
RO
0h
31:22 Reserved 2 (RESERVED_2): Reserved
RO
INTPRIUP Gap DIS (INTPRIUP_GAP_DIS): When the T-unit receives the data for
intpriupdate IDI transaction, if the data specifies legacy clustered mode, then the T-
0h Unit will assume there is a gap in the logical apic id field, such that: cluster_id[3:0] ==
21 logical_id[19:16] and agent_id[3:0] == logical_id[3:0]. These two fields are stored
RW without a gap in the T-Unit CRs. If this CR bit is a one, then T-Unit will not assume a
gap in the incoming data, and will just use the lower 8 bits of logical_id for the legacy
cluster case.
0h
15:9 Reserved 1 (RESERVED_1): Reserved
RO
0h
5:4 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:24 Reserved 1 (RESERVED_1): Reserved
RO
0h
7:2 Reserved 0 (RESERVED_0): Reserved
RO
0h
1:0 PII2 Read Data Completion Weight (PII2_READ_DATA_COMP_WEIGHT):
RW
• 0: Overrides clock gating and forces the clock gating domain to behave like a
freerunning clock.
• 1: Enables Clock Gating.
The reset value for this register is controlled by an SA strap. SOCs can tie this strap to
a constant, a fuse or an output from another unit. NOTE: This has to be revisited for
the new PND2 T-Unit structure clock gating control.
0h
31 Reserved 8 (RESERVED_8): Reserved
RO
0h
30 Reserved 7 (RESERVED_7): Reserved
RO
0h
29 Reserved 6 (RESERVED_6): Reserved
RO
0h
28 Reserved 5 (RESERVED_5): Reserved
RO
0h
27 Reserved 4 (RESERVED_4): Reserved
RO
0h
26 Reserved 3 (RESERVED_3): Reserved
RO
0h
25 IDI_U2C_CRDT_CNT_CLK_GATE_EN: IDI U2C Credit Counters Clock Gate Enable
RW
0h
24 BT_FREE_CLK_GATE_EN: BT Free Clock Gate Enable
RW
0h
23 Monitor Logic Clock Gate Enable (MON_LOG_CLK_GATE_EN):
RW
0h
22 A2T Queue Clock Gate Enable (A2T_Q_CLK_GATE_EN):
RW
0h T2A Queue Clock Gate Enable (T2A_Q_CLK_GATE_EN): T2A queue clock gate
21
RW enable. NOTE: Need both request and writepull.
0h
20 A2TAPIC Clock Gate Enable (A2TAPIC_CLK_GATE_EN):
RW
0h
19 B2X Data Selector Clock Gate Enable (B2X_DATSEL_CLK_GATE_EN):
RW
0h
18 X2B Data Selector Clock Gate Enable (X2B_DATSEL_CLK_GATE_EN):
RW
0h
17 U2C Response Selector Clock Gate Enable (U2C_RESP_SEL_CLK_GATE_EN):
RW
0h
16 T2A Request Selector Clock Gate Enable (T2A_REQ_SEL_CLK_GATE_EN):
RW
0h
15 C2APIC FIFO Clock Gate Enable (C2APIC_FIFO_CLK_GATE_EN):
RW
0h
12 Upstream Ordering Block Clock Gate Enable (UOB_CLK_GATE_EN):
RW
0h
2 Tracker Scoreboard Clock Gate Enable (TRKR_SB_CLK_GATE_EN):
RW
0h
0 IOSF SB Message Clock Gate Enable (IOSF_SB_MSG_CLK_GATE_EN):
RW
0h
31:26 Reserved (RSVD): Reserved
RO
0h Snoop Ready Vector (SNP_RDY_VEC): Allows Debug to dynamically read this state
25:24
RO/V in the T-Unit.
0h
23:18 Reserved (RSVD): Reserved
RO
IWB_FORWARDING_EN: When an IWB comes into to B-unit, let it write the BRAM,
0h even if the btag entry is locked waiting on the memory read return. Also, once written
14 into the BRAM, let the tub2xdata logic consider the ooaq entry as ready to receive
RO data. These two allowances will forward the IWB data to the requester, without waiting
on the memory read return.
0h
13:12 Spare 2 (SPARE2): Spare bits for hardware.
RW
0h SPARE: Readable and Writable Spare bits. SPARE[0] has been consumed. It is used
11:8 by PCODE to bypass IDI_SHUTDOWN detection and will force IDI CSM FSM indicator to
RW 1 for pgcb/idle detection.
0h
7 Reserved (RSVD): Reserved
RO
DPTE Count (DPTE_CNT): This field controls the number of cycles between sending
Dynamic Prefetch Throttle Update Events to each IDI Attach Point. The 4-bit value in
this field is N and the Count is 2 to the Nth power.
• 0: T-Unit can send a DPTE every cycle.
0h
4:1 • 1: T-Unit can send a DPTE every 2 cycles.
RW
• 2: T-Unit can send a DPTE every 4 cycles.
• 3: T-Unit can send a DPTE every 8 cycles.
• 4: T-Unit can send a DPTE every 16 cycles.
• 15: T-Unit can send a DPTE every 32768 cycles.
0h
31 Reserved 1 (RESERVED_1): Reserved
RO
0h
23:22 Reserved 0 (RESERVED_0): Reserved
RO
0h TG Half Tunnel (TG_HALF_TUNNEL): Enable IDI Half Tunneling. By Default IDI Half
13 Tunneling is not required for proper functionality. This should only be enabled in an
RO Intel Debug setting on Dual Core SoCs.
0h • 0: DRAM Read Completions to IOSF VC0 are stalled in the BRAM until all prior
10 downstream Posted Requests from IDI are pushed into the Aunit. This ensures
RW proper PCI Producer/Consumer Ordering Rules.
• 1: Disables the Posted Push Logic.
Note this mode violates the Producer/Consumer Ordering rules.
Broadcast APIC (BCAST_APIC): Broadcast APIC Mode. When 1 T-Unit will wake up
all IDI attach points and broadcast APIC messages to all attach points not just the IDI
attach points that needs to receive the APIC message. Note: The T-Unit does not
0h change the APIC ID to the broadcast APIC ID. What is meant by Broadcast is the
8 Interrupt message is sent to all IDI Attach Points. For directed interrupts the directed
RW interrupt is sent to all Attach Points with the unmodified APIC ID. For redirected
interrupts the T-Unit performs the standard redirection algorithm fixed roundrobin or
PAIR selects 1 APIC ID to send the message but then sends the message to all IDI
Attach Points.
0h SNPINV: SnpInv only when 1 T-Unit will only send SnpInv. This disables all other
7
RW Snoop types e.g. SnpCode SnpData.
0h
31:8 Reserved 2 (RESERVED_2): Reserved
RO
0h
7 Reserved 1 (RESERVED_1): Reserved
RO
Select IDI Attach Point (SEL_IDI_ATTACH): Selects IDI Attach Point. i.e. Module
to capture/replay.
0h • 00b: IDI Attach Point 0
6:5
RW • 01b: IDI Attach Point 1
• 10b: Reserved
• 11b: Reserved
0h
2 Reserved (RESERVED_0): Reserved
RO
0h
1 PSMI Replay Mode (PSMI_REPLAY_MODE):
RW
38h PII_IDLE_THRESHOLD: Number of 1x cycles that BT-unit PII idle conditions should
31:24 exist before the ISM requests idle. The restart time of PII BGFs is on the order of 150
RW to 210 ns. To avoid this penalty, idle should not be entered too quickly.
0h
23:15 Spare (SPARE1): Spare register bits for read/write.
RW
0h
4:0 Spare (SPARE0): Spare register bits for read/write.
RW
0h
31:16 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:16 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:18 Reserved 0 (RESERVED_0): Reserved
RO
0h
31:16 Reserved 0 (RESERVED_0): Reserved
RO
C006101020
2h Access Control Policy (ACCESS_CTRL_POL): The Access Control Policy for this
63:0
register and the T-Unit Read/write Policy Registers.
RW
80000C0063
63:0 0D0217h Read Policy (READ_POL): The Read Policy for the T-Unit Registers.
RW
C00610C021
63:0 2h Write Policy (WRITE_POL): The Write Policy for the T-Unit Registers.
RW
4000100020
2h ACCESS_CTRL_POL: The Access Control Policy for this register and the Tunit ucode
63:0
Read/write Policy Registers.
RW
FFFFFFFFFFF
63:0 FFFFFh READ_POL: The Read Policy for the Tunit ucode Registers.
RO
4080100860
63:0 2h WRITE_POL: The Write Policy for the Tunit ucode Registers.
RW
3.560 PMTA_WEIGHTED_ARB_CONFIG
(PMTA_WEIGHTED_ARB_CONFIG)—Offset 4C04h
PMTA_WEIGHTED_ARB_CONFIG
Access Method
Default: 12204011h
31:30
0h RSVD (RSVD): Reserved
RO
CFG_INITIAL_LINK_PREFERENCE_COMPQM
0h (CFG_INITIAL_LINK_PREFERENCE_COMPQM): Initial link
29
RW preference for MEE completion queue. Preference is used to break
ties between contending requests with same urgency value.
CFG_INITIAL_LINK_PREFERENCE_COMPQB
1h (CFG_INITIAL_LINK_PREFERENCE_COMPQB): Initial link
28
RW preference for non-MEE completion queue. Preference is used to
break ties between contending requests with same urgency value.
CFG_INITIAL_LINK_WEIGHT_COMPQM
(CFG_INITIAL_LINK_WEIGHT_COMPQM): Initial link weight
2h
27:24 for MEE completion queue. Once the queue wins arbitration, it will
RW
stay as the winner for as many cycles as the weight assigned,
provided there are responses available in the queue.
CFG_INITIAL_LINK_WEIGHT_COMPQB
(CFG_INITIAL_LINK_WEIGHT_COMPQB): Initial link weight
2h
23:20 for non-MEE completion queue. Once the queue wins arbitration, it
RW
will stay as the winner for as many cycles as the weight assigned,
provided there are responses available in the queue.
0h
19:16 Reserved.
RO
CFG_INITIAL_LINK_PREFERENCE_REQQM
1h (CFG_INITIAL_LINK_PREFERENCE_REQQM): Initial link
15:14
RW preference for MEE request queue. Preference is used to break
ties between contending requests with same urgency value.
CFG_INITIAL_LINK_PREFERENCE_REQQB
0h (CFG_INITIAL_LINK_PREFERENCE_REQQB): Initial link
13:12
RW preference for non-MEE request queue. Preference is used to
break ties between contending requests with same urgency value.
0h
11:8 Reserved.
RO
CFG_INITIAL_LINK_WEIGHT_REQQM
(CFG_INITIAL_LINK_WEIGHT_REQQM): Initial link weight for
1h
7:4 MEE request queue. Once the queue wins arbitration, it will stay
RW
as the winner for as many cycles as the weight assigned, provided
there are requests available in the queue.
CFG_INITIAL_LINK_WEIGHT_REQQB
(CFG_INITIAL_LINK_WEIGHT_REQQB): Initial link weight for
1h
3:0 non-MEE request queue. Once the queue wins arbitration, it will
RW
stay as the winner for as many cycles as the weight assigned,
provided there are requests available in the queue.
Access Method
Default: 808000408000h
Access Method
Default: 40001484442h
63:48
0h RSVD (RSVD): Reserved
RO
Access Method
Default: 3C00000000h
63
0h LOCK (LOCK): When set all writes to this register will be dropped
RW/L
62:52
0h RESERVED_3 (RESERVED_3): Reserved
RO
SYM_SLICE1_CHANNEL_ENABLED
(SYM_SLICE1_CHANNEL_ENABLED): Specifies which channels
in Slice1 are enabled for hosting the symmetric region of the
DRAM address space. If SLICE_1_DISABLED is set to disable
mapping of DRAM address space to Slice 1, this field has no effect
and symmetric region is considered to be not mapped to Slice1. If
CH_1_DISABLED is set, Channel 1 in Slice 1 is not enabled for
symmetric DRAM address space regardless of the setting of this
register. DRAM address space is divided into a symmetric regions,
asymmetric regions that are partially interleaved across a subset
of channels (2-way) or asymmetric regions that are non-
3h interleaved and mapped only to a single channel. This field
37:36
RW/L specifies which channels in Slice 1 are enabled for interleaving the
symmetric region. SLICE0_CHANNEL_ENABLED defines which
channels in Slice 0 are enabled for interleaving the symmetric
region. The mapping of partial (2-way) interleaved and non-
interleaved regions are specified in other registers. For symmetric
region, only selected configurations are supported. Across both
slices, only a total of 1 channel, 2 channels or 4 channels must be
enabled for interleaving the symmetric region. The total of 1, 2 or
4 channels can be made up of any combination of channel enables
across both slices. B-unit does not support a 3-way interleaving of
the symmetric region across 3 enabled channels in the two slices
combined.
SYM_SLICE0_CHANNEL_ENABLED
(SYM_SLICE0_CHANNEL_ENABLED): Specifies which channels
in Slice0 are enabled for hosting the symmetric region of the
DRAM address space. If SLICE_0_MEM_DISABLED is set to disable
mapping of DRAM address space to Slice 0, this field has no effect
and symmetric region is considered to be not mapped to Slice0. If
CH_1_DISABLED is set, Channel 1 in Slice 0 is not enabled for
symmetric DRAM address space regardless of the setting of this
register. DRAM address space is divided into a symmetric regions,
asymmetric regions that are partially interleaved across a subset
of channels (2-way) or asymmetric regions that are non-
3h interleaved and mapped only to a single channel. This field
35:34
RW/L specifies which channels in Slice 0 are enabled for interleaving the
symmetric region. SLICE1_CHANNEL_ENABLED defines which
channels in Slice 1 are enabled for interleaving the symmetric
region. The mapping of partial (2-way) interleaved and non-
interleaved regions are specified in other registers. For symmetric
region, only selected configurations are supported. Across both
slices, only a total of 1 channel, 2 channels or 4 channels must be
enabled for interleaving the symmetric region. The total of 1, 2 or
4 channels can be made up of any combination of channel enables
across both slices. B-unit does not support a 3-way interleaving of
the symmetric region across 3 enabled channels in the two slices
combined.
33
0h RESERVED_2 (RESERVED_2): Resesved
RO
30:20
0h RESERVED_1 (RESERVED_1): Reserved
RO
5
0h POISON (POISON): Indication that Poison is enabled when set
RW/L
SLICE_0_MEM_DISABLED (SLICE_0_MEM_DISABLED):
0h
4 Slice 0 is disabled for memory accesses; no memory address
RW/L
mapped to Slice 0 and all memory requests sent to Slice 1.
§§
0h
15:11 Reserved (RESERVED_0): Reserved
RO
INTx Disable (INTDIS): This bit disables the device from asserting INTx.
0h • 0: Enable the assertion of this devices INTx signal.
10
RW/V • 1: Disable the assertion of this devices INTx signal. DO_INTx messages will not be
sent to DMI.
0h
9 FB2B: Not Implemented. Hardwired to 0.
RO
0h
8 SEN: Not Implemented. Hardwired to 0.
RO
0h
7 WCC: Not Implemented. Hardwired to 0.
RO
0h PER: Not Implemented. Hardwired to 0. Since the IGD belongs to the category of
6 devices that does not corrupt programs or data in system memory or hard drives the
RO IGD ignores any parity error that it detects and continues with normal operation.
0h
5 VPS: This bit is hardwired to 0 to disable snooping.
RO
0h MWIE: Hardwired to 0. The IGD does not support memory write and invalidate
4
RO commands.
0h
3 SCE: This bit is hardwired to 0. The IGD ignores Special cycles.
RO
BME:
0h • 0: Disable IGD bus mastering.
2
RW/V • 1: Enable the IGD to function as a PCI compliant master.
.
MAE: This bit controls the IGD's response to memory space accesses.
0h • 0: Disable.
1
RW/V • 1: Enable.
Device 2 Function Level Reset must reset this bit.
IOAE: This bit controls the IGD's response to I/O space accesses.
0h • 0: Disable.
0
RW/V • 1: Enable.
Device 2 Function Level Reset must reset this bit.
0h
23:4 Address Mask (ADM): Hardwired to 0s to indicate at least 16MB address range.
RO
0h
3 Prefetch Memory Enable (PREFMEM): Hardwired to 0 to prevent prefetching.
RO
0h
0 Memory or IO Space (MIOS): Hardwired to 0 to indicate memory space.
RO
0h
31:7 Reserved (RESERVED_0): Reserved
RO
0h Memory Base Address (MBA): These bits are set by the OS, and correspond to
6:0 address signals [38:24]. 16MB combined for MMIO and Global GTT table aperture. 2MB
RW/V are for MMIO, 6MB are reserved and 8 MB are for GTT.
0h Memory Base Address or Address Map 4096 (ADMSK4096): This Bit is either
31 part of the Memory Base Address R/W, or part of the Address Mask RO, depending on
RW/V the value of MSAC[4:0].
0h Memory Base Address or Address Map 2048 (ADMSK2048): This Bit is either
30 part of the Memory Base Address R/W, or part of the Address Mask RO, depending on
RW/V the value of MSAC[4:0].
0h Memory Base Address or Address Map 1024 (ADMSK1024): This Bit is either
29 part of the Memory Base Address R/W, or part of the Address Mask RO, depending on
RW/V the value of MSAC[4:0].
0h Memory Base Address or Address Map 512 (ADMSK512): This Bit is either part
28 of the Memory Base Address R/W, or part of the Address Mask RO, depending on the
RW/V value of MSAC[4:0].
0h Memory Base Address or Address Map 256 (ADMSK256): This Bit is either part
27 of the Memory Base Address R/W, or part of the Address Mask RO, depending on the
RW/V value of MSAC[4:0].
0h
26:4 Address Mask (ADM): Hardwired to 0s to indicate at least 128MB address range.
RO
0h
3 Prefetch Memory Enable (PREFMEM): Hardwired to 0 to prevent prefetching.
RO
0h
0 Memory or IO Space (MIOS): Hardwired to 0 to indicate memory space.
RO
0h
31:7 Reserved (RESERVED_0): Reserved
RO
0h Memory Base Address (MBA): These bits are set by the OS, and correspond to
6:0
RW/V address signals [38:32].
0h
31:16 Reserved (RESERVED_1): Reserved
RO
0h
5:3 Reserved (RESERVED_0): Reserved
RO
1h
0 Memory or IO Space (MIOS): Hardwired to 1 to indicate IO space.
RO
0h
7:1 Reserved (RESERVED_0): Reserved
RO
IOBAR Disable (IOBARDIS): System BIOS can choose to disable and hide the
IOBAR for systems that do not require legacy IOBAR access to Gfx MMIO registers.
0h • 0: IOBAR is enabled and exposed at offset 0x20 in Device 2 Configuration space.
0
RW/V Default
• 1: IOBAR is disabled and not visible in PCI Configuration Space. Behaves as if
hardwired to zeros.
0h
7:5 Reserved (RESERVED_0): Reserved
RO
0h
4 Aperture Size 4 (APSZ4): Refer to description for APSZ0 [0:0].
RW/V
0h
3 Aperture Size 3 (APSZ3): Refer to description for APSZ0 [0:0].
RW/V
0h
2 Aperture Size 2 (APSZ2): Refer to description for APSZ0 [0:0].
RW/V
0h
1 Aperture Size 1 (APSZ1): Refer to description for APSZ0 [0:0].
RW/V
Aperture Size 0 (APSZ0): This field is used in conjunction with other APSZ fields to
determine the size of Aperture GMADR. It affects certain bits of the GMADR register.
The description below is for all APSZ fields [4:0]:
• 00000b: 128MB GMADR.B[26:4] is hardwired to 0.
• 00001b: 256MB GMADR.B[27]=0, RO.
• 00010b: illegal hardware will treat this as 00011.
1h
0 • 00011b: 512MB GMADR.B[28:27]=0, RO.
RW/V
• 00100b-00110b: illegal hardware will treat this as 00111.
• 00111b: 1024MB GMADR.B[29:27]=0,RO.
• 01000b-01110b: illegal hardware will treat this as 01111.
• 01111b: 2048MB GMADR.B[30:27]=0,RO.
• 10000b-11110b: illegal hardware will treat this as 11111.
• 11111b: 4096MB GMADR.B[31:27]=0,RO
0h Power Management Event Status (PMESTS): This bit is 0 to indicate that the
15 Internal Graphics Device does not support Power Management Event generation from
RO D3 (cold).
0h Data Scale (DSCALE): The Internal Graphics Device does not support data register.
14:13
RO This bit always returns 00 when read write operations have no effect.
0h Data Select (DSEL): The IGD does not support data register. This bit always returns
12:9
RO 0h when read write operations have no effect.
0h Power Management Event Enable (PMEEN): This bit is 0 to indicate that PME
8
RO assertion from D3 (cold) is disabled.
0h
7:2 Reserved (RESERVED_1): Reserved
RO
Power State (PWRSTAT): This field indicates the current power state of the IGD,
and can be used to set the IGD into a new power state. If software attempts to write
an unsupported state to this field, the write operation must complete normally on the
bus, but the data is discarded and no state change occurs. On a transition from D3 to
0h D0, the graphics controller is optionally reset to initial values.
1:0
RW/V • 00: D0 Default
• 01: D1 Not Supported
• 10: D2 Not Supported
• 11: D3
§§
8086h
15:0 Vendor ID (VENDOR_ID): Hardwired to Intel's Vendor ID value.
RO
5.2 PCI_STATUS_COMMAND_0_0_1_PCI
(B_CR_PCI_STATUS_COMMAND_0_0_1_PCI) — Offset 4h
PCI Status is used to record status information for PCI bus related events, including the
occurrence of a PCI compliant Master Abort (MA) and PCI compliant Target Abort (TA).
PCISTS also indicates the DEVSEL# timing that has been set by the thermal device.
0h Detected Parity Error (DPE): The Thermal device does not implement this bit and it
31
RO is hardwired to a 0.
0h Signaled System Error (SSE): This bit is hardwired to zero. The Thermal device
30
RO never asserts SERR#, and therefore it has no need to implement this bit.
0h Received Master Abort (RURS): The Thermal device does not implement this bit
29
RO and it is hardwired to a 0.
0h Received Target Abort (RCAS): The Thermal device does not implement this bit
28
RO and it is hardwired to a 0.
0h Signaled Target Abort (STAS): his bit is hardwired to 0. The Thermal device will not
27 generate a Target Abort DMI completion packet or Special Cycle, and therefore it has
RO no need to implement this bit.
0h DEVSEL Timing (DEVT): These bits are hardwired to 0. Device 4 does not physically
26:25
RO connect to PCI_A.
0h Master Data Parity Error (DPD): This bit is hardwired to 0. PERR signaling and
24 messaging are not implemented by the Thermal Device, and therefore it has no need
RO to implement this bit.
0h
22 Reserved (RSVD): Reserved
RO
0h 66MHz Capable (PCI66M): The Thermal device does not implement this bit and it is
21
RO hardwired to a 0.
1h Capabilities List (CLIST): This bit is set to 1 to indicate that the register at 34h
20 provides an offset into the function. PCI Configuration Space containing a pointer to
RO the location of the first item in the list.
Interrupt Status (IS): Reflects the state of the INTA# signal at the input of the
0h enable/disable circuit. This bit is set by HW to 1 when the INTA# is asserted and reset
19
RO/V by HW to 0 after the interrupt is cleared (independent of the state of the Interrupt
Disable bit in the 0.0.1.PCICMD register).
0h
18:11 Reserved (RSVD): Reserved
RO
0h INTx# Disable (INTDIS): This bit, when set, disables the device from asserting
10
RW INTx#, where 'x' is configured in the INTPIN register.
0h Fast Back to Back Enable (FB2B_ENABLE): The Thermal device does not
9
RO implement this bit and it is hardwired to a 0.
0h SERR# Enable (SERRE): The Thermal device does not implement this bit and it is
8
RO hardwired to a 0.
0h
7 ADSTEP: The Thermal device does not implement this bit and it is hardwired to a 0.
RO
Parity Error Enable (PERRE): This bit is hardwired to 0. The Thermal device belongs
0h to the category of devices that does not corrupt programs or data in system memory or
6
RO hard drives. It therefore ignores any parity error that it detects and continues with
normal operation.
0h VGA Snoop (VGASNOOP): The Thermal device does not implement this bit and it is
5
RO hardwired to a 0.
0h Memory Write and Invalidate Enable (MWIE): This bit is hardwired to 0. The
4 Thermal device will never issue memory write and invalidate commands, and therefore
RO has no need to implement this bit.
0h Special Cycle Enable (SCE): The Thermal device does not implement this bit and it
3
RO is hardwired to a 0.
0h Bus Master Enable (BME): The Thermal device is enabled to function as a PCI-
2
RW compliant bus master when this bit is set. If it is not set, bus mastering is disabled.
0h Memory Access Enable (MAE): The Thermal device will allow access to thermal
1 registers when this bit is set. If it is not set, access to memory mapped thermal
RW registers is disabled.
0h I/O Access Enable (IOAE): The Thermal device does not implement this bit and it is
0
RO hardwired to a 0.
11h Base Class Code (BASE_CLASS_CODE): This is an 8-bit value that indicates the
31:24 base class code for the Thermal Controller. This code has the value 11h, indicating a
RO device that is used for data acquisition and signal processing.
80h Sub-class Code (SUB_CLASS_CODE): The code is 80h which indicates 'Other Data
23:16
RO Acquisition and Signal Processing Controllers.'
0h Programming Interface (PI): This is an 8-bit value that indicates the programming
15:8 interface of this device. This value does not specify a particular register set layout and
RO provides no practical use for this device.
0h
7:0 Revision ID (REVISION_ID): Revision ID.
RO/V
0h BIST Support (BS): This bit is hardwired to zero. The Thermal device does not
31
RO support BIST.
0h
30:24 Reserved (RSVD): Reserved
RO
0h Header Type (HDR): This field always returns 0 to indicate that the Thermal device
23:16
RO is a single function device with standard header layout.
0h Master Latency Timer (MLT): This field is hardwired to 0. The Thermal device does
15:8
RO not support perform bursts.
0h Cache Line Size (CLS): This field is hardwired to 0. The Thermal Device as a PCI
7:0 compliant master does not use the Memory Write and Invalidate command and, in
RO general, does not perform operations based on cache line size.
TMMBA: This field corresponds to bits 31 to 15 of the base address TMBAR address
0h space. BIOS will program this register resulting in a base address for a 32KB block of
31:15 contiguous memory address space. This register ensures that a naturally aligned 32KB
RW space is allocated within total addressable memory space. The DPTF driver uses this
base address to program all Thermal and Throttling control register set.'
0h
14:4 Address Map (ADM): Hardwired to 11'h000 to indicate at least 32KB address range.
RO
0h
3 Prefetch Memory (PM): Hardwired to 1'b0 to prevent prefetching.
RO
2h
2:1 Memory Type (MT): Hardwired to 2'b10 to indicate 64-bit address.
RO
0h
0 Memory or IO Space (MIOS): Hardwired to 0 to indicate memory space.
RO
0h
31:7 Reserved RW (RSVDRW): Reserved
RW
TMMBA: This field corresponds to bits 38 to 32 of the base address TMBAR address
0h space. BIOS will program this register resulting in a base address for a 32KB block of
6:0 contiguous memory address space. This register ensures that a naturally aligned 32KB
RW space is allocated within total addressable memory space. The DPTF driver uses this
base address to program all Thermal and Throttling control register set.
0h
31:8 Reserved (RSVD): Reserved
RO
D0h Base Address of First Capability Register (BASE_ADDR): This pointer is an 8-bit
7:0 address to an offset within this device's Configuration Space that holds the first
RO Capability Register (CAPID0_CAPCTRL).
0h Maximum Latency Value (MLV): These bits are hardwired to zero. The Thermal
31:24
RO device has no specific requirements for how often it needs to access the PCI bus.
0h Minimum Grant Value (MGV): These bits are hardwired to zero. The Thermal device
23:16
RO does not burst as a PCI compliant master.
Interrupt Pin (INTPIN): As a single function device, the Thermal device specifies
1h INTA as its interrupt pin. 01h = INTA by default. BIOS may need to reconfigure this in
15:8 order allow software to disambiguate multiple functions within MCHBAR.
RW/L Recommended setting is 02h = INTB. This field is locked from future writes when the
THERMAL_DEVICE_IRQ.LOCK
0h
31:6 RESERVED_1: Reserved
RO
0h
3 Reserved (RSVD): Reserved
RO
0h
2 RESERVED_0: Reserved
RO
0h
31:1 Reserved (RSVD): Reserved
RO
0h CTED: If set, indicates a thermal event was detected and SCI has optionally been
0 generated. If this bit is already set, then an interrupt message will not be sent on a
RW/1C/V new event. ACPI software will write this bit to 1b to clear the event.
0h
31:17 Reserved (RSVD): Reserved
RO
0h
15:0 Reserved (RSVD): Reserved
RO
0h PME Support (PMES): This field indicates the power states in which the thermal
31:27 device may assert PME#. It is hardwired to 0 to indicate that the Thermal device does
RO not support nor assert the PME# signal.
0h
26 RO D2: Hardwired to 0 to indicate that the D2 power management state is not supported.
0h
25 D1: Hardwired to 0 to indicate that the D1 power management state is not supported.
RO
0h
24:22 Reserved (RSVD): Reserved
RO
0h
20 APS: The Thermal device does not implement this bit and it is hardwired to a 0.
RO
0h PME# Capbility (PMEC): Hardwired to 0 to indicate the thermal device does not
19
RO support PME# generation.
3h VER: This device complies with revision 1.2 of the PCI Power Management Interface
18:16
RO Specification.
E0h Next Capability Pointer (NCP): This contains a pointer to next item in capabilities
15:8
RO list. The next capability is E0h which is device 0 / func 0 capability mirror.
1h
7:0 Capability ID (CID): 01h indicates that this is a power management capability
RO
0h DATA: The data register, data scale and data select registers are not supported.
31:24
RO Hardwired to zero.
0h
23:16 Reserved (RSVD): Reserved
RO
0h PME# Status (PMES): This bit is set when the function would normally assert the
15 PME# signal independent of the state of the PME_En bit. This bit is hardwired to 0b to
RO indicate that PME# assertion from D3 (cold) is not supported.
0h Data Scale (DS): The data register, data scale and data select registers are not
14:13
RO supported
0h
Data Select (DSEL): The data register, data scale and data select registers are not
12:9
supported
RO
0h PME# Enable (PMEEN): This bit is hardwired to 0b to indicate that PME# assertion
8
RO from D3 (cold) is disabled.
0h
7:4 Reserved (RSVD): Reserved
RO
0h
2 Reserved (RSVD): Reserved
RO
Power State (PS): This field indicates the current power state of the thermal device
and can be used to set the thermal device into a new power state. If software attempts
to write an unsupported state to this field, the write operation must complete normally
on the bus, but the data is discarded and no state change occurs.
0h
1:0 • 00b = D0 Default
RW/V
• 01b = D1 Not Supported
• 10b = D2 Not Supported
• 11b = D3
0h
31:1 Reserved (RSVD): Reserved
RO
0h Interrupt Status (INTSTAT): If set, indicates a thermal event was detected. If this
0 bit is already set, then an interrupt message will not be sent upon detection of a new
RW/1C/V event.
0h
31:28 Reserved (RSVD): Reserved
RO
1h Capability ID Version (CAPID_VER): This field has the value 0001b to identify the
27:24
RO first revision of the CAPID register definition.
Ch Capability ID0 Structure Length (CAPIDLEN): This field has the value 0Ch to
23:16 indicate the structure length 12 bytes. This is the total size of this CAPCTRL and the
RO CAPID0_A and CAPID0_B registers in the following bytes.
0h Next Capability Register Pointer (NCP): This field is hardwired to 00h, indicating
15:8
RO the end of the capabilities linked list.
9h Capability ID (CAP_ID): This field has the value 1001b to identify the CAP_ID
7:0
RO assigned by the PCI SIG for vendor dependent capability pointers.
0h
31:24 SPARE31_24: Reserved for future capabilities.
RW/V
0h
22 FUSE_SPARE22: Fuse backed spare.
RW/V
0h
21 FUSE_SPARE21: Fuse backed spare.
RW/V
0h
20 FUSE_SPARE20: Fuse backed spare.
RW/V
0h
19 FUSE_SPARE19: Fuse backed spare.
RW/V
0h
18 FUSE_SPARE18: Fuse backed spare.
RW/V
0h
17 FUSE_SPARE17: Fuse backed spare.
RW/V
0h
16 FUSE_SPARE16: Fuse backed spare.
RW/V
0h
14 FUSE_SPARE14: Fuse backed spare.
RW/V
0h
13 FUSE_SPARE13: Fuse backed spare.
RW/V
0h
12 FUSE_SPARE12: Fuse backed spare.
RW/V
DIDOE: Controls if there is an override of Dev2 (GFX) device ID. Hardwired to 1'b0.
0h
10 • 0 = Disable ability to override DID - For production
RO
• 1 = Enable ability to override DID - For debug and samples only
CDID: Controls the value of Dev2 (GFX) device ID. Hardwired to 2'b00. Identifier
assigned to the core/primary PCI device.The corresponding two bit capability ID
programming is:
0h
9:8 • 00b = Desktop
RO
• 01b = Mobile
• 10b = Server
• 11b = Marketing Spare
0h
7:0 SPARE7_0: Reserved for future capabilities
RW
0h
30 FUSE_SPARE30: Fuse backed spare.
RW/V
0h
29 FUSE_SPARE29: Fuse backed spares, potentially to be used for PKGTYP encoding.
RW/V
0h
28 FUSE_SPARE28: Fuse backed spares potentially to be used for PKGTYP encoding.
RW/V
0h
27 FUSE_SPARE27: Fuse backed spares potentially to be used for PKGTYP encoding.
RW/V
0h
26 FUSE_SPARE26: Fuse backed spares potentially to be used for PKGTYP encoding.
RW/V
0h
25 FUSE_SPARE25: Fuse backed spares potentially to be used for PKGTYP encoding.
RW/V
0h
23:0 Spare (SPARE23_0): Reserved for future capabilities.
RW
Access Method
Default: 0h
EPM (EPM): This field controls DMA accesses to the protected lowmemory and
protected highmemory regions.
• 0: Protected memory regions are disabled.
• 1: Protected memory regions are enabled. Access control is implemented. IA
accesses are always allowed access. NonIA accesses are allowed if request SAI
0h matches the SAI of the Default VTd Engine. Requests blocked due to protected
31
RW/V memory region violation are not recorded or reported as remapping faults.
Hardware reports the status of the protected memory enable/disable operation
through the PRS field in this register. Hardware implementations supporting DMA
draining must drain any inflight translated DMA requests queued within the
RootComplex before indicating the protected memory region as enabled through
the PRS field.
30:1
0h Reserved (RESERVED_0): Reserved.
RO
PRS Unused (PRS): Unused by the B-Unit. This field indicates the status of protected
0h memory regions:
0
RO • 0: Protected memory regions are disabled.
• 1: Protected memory regions are enabled.
significant bit position with 0 in the value read back from the register. Bits N:0 of this
register are decoded by hardware as all 0s. Software must setup the protected low
memory region below 4GB. Section 10.4.18 of the Intel Virtualization Technology for
Directed I/O: Spec describes the Protected Low-Memory Limit register and hardware
decoding of these registers. Software must not modify this register when protected
memory regions are enabled (PRS field Set in PMEN_REG).
Access Method
Default: 0h
19:0
0h Reserved (RESERVED_0): Reserved.
RO
Access Method
Default: 0h
19:0
0h Reserved (RESERVED_0): Reserved.
RO
Access Method
Default: 0h
63:39
0h Reserved (RESERVED_1): Reserved.
RO
19:0
0h Reserved (RESERVED_0): Reserved.
RO
follows: Programming the protected low-memory base and limit registers with the
same value in bits HAW:(N+1) specifies a protected low-memory region of size
2^(N+1) bytes. Programming the protected high-memory limit register with a value
less than the protected high-memory base register disables the protected high-memory
region. Software must not modify this register when protected memory regions are
enabled (PRS field Set in PMEN_REG).
Access Method
Default: 0h
63:39
0h Reserved (RESERVED_1): Reserved.
RO
19:0
0h Reserved (RESERVED_0): Reserved.
RO
§§
6.1 ID — Offset 0h
Device ID assigned to GNA and Vendor ID
0h Device Identification Number (DID): Indicates the device ID assigned to the GNA
31:16 [6:0] set by straps [15:7] This field is set to the module via IOSF SB message received
RO/V during device reset.
0h
15:0 Vendor Identification Number (VID): Intels identification
RO
0h
15 Reserved (RSVD): Reserved
RO
0h
12:11 Reserved (RSVD_1): Reserved
RO
0h Interrupt Disable (INTDIS): Interrupt Disable: Controls the ability of the function
10
RW to generate INTx interrupts. 0: INTx allowed 1: INTx disabled
0h
9:6 Reserved (RSVD_2): Reserved
RO
0h
5 Max Aligned Payload Size (MXAPAYLDSZ): Max Aligned Payload Size - Reserved
RO
0h Max Aligned Read Request Size (MXARDREQSZ): Max Aligned Read Request Size
4
RO - Reserved
0h
3 Special Cycle Enable (SCEN): Special Cycle Enable - Reserved
RO
0h Bus Master Enable (BME): Bus Master Enable: 0: Disable (default) 1: Enabled.
2
RW Device may generate bus master transactions depending on its mode of operation.
0h Memory Space Enable (MSE): Memory Space Enable Controls the GMM devices
1 response to memory space accesses 0: Disabled (default) 1: Enabled. Device will
RW respond to memory space accesses.
0h
0 IO Space Enable (IOSE): IO Space Enable. Not implemented.
RO
Detected Parity Error (DPE): This bit is Set by a Function whenever it receives a
Poisoned TLP, regardless of the state the Parity Error Response bit in the Command
0h register. On a Function with a Type 1 Configuration header, the bit is Set when the
15
RO Poisoned TLP is received by its Primary Side. Note : some implementations use this
error type as non-fatal error indication This bit is typically RWC. Change to RO as this
bit is not in use
Signaled System Error (SSE): This bit is Set when a Function sends an ERR_FATAL
0h or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1.
14
RO Note: some implementations use this error for fatal. When received all operations are
aborted. This bit is typically RWC. Change to RO as this bit is not in use
Received Master Abort (RMA): This bit is Set when a Requester receives a
0h Completion with Unsupported Request Completion Status. On a Function with a Type 1
13
RW/1C/V Configuration header, the bit is Set when the Unsupported Request is received by its
Primary Side.
0h Received Target Abort (RTA): This bit is set when a transaction abort is received to
12
RW/1C/V a GMM initiated transaction
0h Signaled Target Abort (STA): This bit is Set when a Function completes a Posted or
11 Non-Posted Request as a Completer Abort error. This applies to a Function with a Type
RW/1C/V 1 Configuration header when the Completer Abort was generated by its Primary Side.
0h
10:8 Reserved (RSVD): Reserved
RO
0h
7 Fast Back-to-Back (FB2B): Fast Back-to_Back (ignored by SW)
RO
0h
6:5 Reserved (RSVD_1): Reserved
RO
0h Capability List (CLIST): Capability List 0 : no capability list 1 : the GMM contains a
4
RO linked list of capabilities which is accessed via the CAPPTR register at offset 34h
Interrupt Status (INTSTS): Interrupt Status Reflects the state of the interrupt in
0h the device. Only when the Interrupt Disable bit in the command register is a 0 and this
3 Interrupt Status bit is a 1, will this device send a virtual INTA. Setting the Interrupt
RO/V Disable bit to a 1 has no effect on the state of this bit. This bit is controlled by HW. 0 :
No interrupt pending 1 : Interrupt pending
0h
2:0 Reserved (RSVD_2): Reserved
RO
0h
31:24 Base Class Code (BCC): Base Class (Generic system Peripherals)
RO
0h
23:16 Sub Class Code (SCC): Sub Class
RO
0h
15:8 Peripheral Interface (PROGINTERFACE): Interface (other system peripheral)
RO
0h Revision ID (RID): Indicates stepping of this device. This register is set by side-
7:0 band. All RID registers are sourced from a fuse/settings incremented for each
RO/V stepping.
0h Cache Line Size (CLS): Implemented by PCI Express devices as a read-write field for
7:0 legacy compatibility purposes but has no impact on any PCI Express device
RW functionality
0h Multi Function Device (MFD): Hardwired to 0 indicating this device is not a multi-
7
RO function device.
0h Header Type (HT): The value 00h, indicates a basic (i.e., single function)
6:0
RO configuration space format.
0h BIST Capable (BISTCAP): BIST Capable. Hardwired to 0 since this device does not
7
RO implement BIST.
0h Start BIST (BISTST): Start BIST. Hardwired to 0 since this device does not
6
RO implement BIST
0h
5:4 Reserved (RSVD): Reserved
RO
0h BIST Completion Code (BISTCC): Hardwired to 0 since this device does not
3:0
RO implement BIST.
0h Memory Base Address Low (BAL): Memory Base Address Low Base address of this
31:12
RW device's memory mapped IO space. A page of 4KB of address is used
0h
3 PREF: Hardwired to 0 indicating that this range is not prefetchable
RO
0h Memory Type (MEMTY): Memory Type: 00: 32 bit base address 01: reserved 10:
2:1
RO 64-bit base address 11: reserved
0h Space Type (SPTY): Space Type: Memory/IO Space Hardwired to 0 indicating that
0
RO this is a Memory BAR
0h Memory Base Address High (Reserved) (BAR): These bits must be loaded with
31:7
RW zeros
0h Memory Base Address High (BAH): Memory Base Address High - bits Includes the
6:0
RW high bits of the base address used by 64-bit OS. Must hold zero for 32-bit OS
0h
31:8 Reserved (RSVD): Reserved
RO
0h Capability Pointer (CAPP): Indicates that the MSI capability pointer offset is offset
7:0
RO 90h
0h
7:3 Reserved (RSVD): Reserved
RO
0h Legacy Interrupt (LEGINT): When Legacy interrupts are used, function use legacy
2:0
RO interrupt INTA.
0h
15:8 Min Latency (MINLAT): Reserved: Min Latency
RO
0h
7:0 Min Grant (MINGNT): Reserved: Min Grant
RO
0h
31:17 RSVD (RSVD1): Reserved
RO
0h
14 FLR_NP_Disable (FLRNPDIS): 0: FLR operates normally.
RW
0h
12:10 RSVDCTL: Reserved
RW
PGCB Clock Trunk Clock Gating Enable (PGCBCGEN): This bit, when set, allows
0h the PGCB interface clock for GMM from SoC (pgcb_clk) to be gated when conditions are
9
RW met by de-asserting GMMs clock request (pgcb_clkreq). When clear, GMM will always
assert its clock request.
0h Sideband Clock Gating Enable (SBDCGEN): This bit, when set, enables the
8 sideband interface clock used for GMM bus interface operations (gated_side_clk) to be
RW gated when conditions are met. When clear, clock gating is disabled.
Sideband Clock Trunk Clock Gating Enable (SBTCGEN): This bit, when set, allows
0h the sideband interface clock for GMM from SoC (iosfsf_clk) to be gated when conditions
7
RW are met by deasserting GMMs clock request (iosfst_side_clkreq). When clear, GMM will
always assert its clock request.
0h Sideband Clock Partition Clock Gating Enable (SBPCGEN): This bit, when set,
6 enables the IOSF sideband interface clock for GMM (side_clk) to be gated when
RW conditions are met. When clear, clock gating is disabled
0h GMM Core Clock Gating Enable (GM_BB_GMMC_DCGEN): This bit, when set,
5 enables the primary interface clock used for GMM core operations (ggm_core_clk) to
RW be gated when conditions are met. When clear, clock gating is disabled.
DMA engine Clock Gating Enable (GM_BB_DMA_DCGEN): This bit, when set,
0h enables the primary interface clock used for GMM DMA and MMU operations
4
RW (ggm_bb_clk_ra) to be gated when conditions are met. When clear, clock gating is
disabled.
Register Access Clock Gating Enable (GM_BB_RA_DCGEN): This bit, when set,
0h enables the primary interface clock used for GMM register access operations
3
RW (ggm_bb_clk_ra) to be gated when conditions are met. When clear, clock gating is
disabled.
Host interface Clock Gating Enable (GM_BB_HOST_DCGEN): This bit, when set,
0h enables the primary interface clock used for GMM bus interface operations
2
RW (ggm_bb_clk_host) to be gated when conditions are met. When clear, clock gating is
disabled
0h Partition Clock Gating Enable (PCGEN): This bit, when set, enables the primary
1 interface clock for GMM (gm_bb_clk) to be gated when conditions are met. When clear,
RW clock gating is disabled.
Trunk Clock Gating Enable (TCGEN): This bit, when set, allows the primary
0h interface clock for GMM from SoC (iosfpf_clk) to be gated when conditions are met by
0
RW deasserting GMMs clock request (iosfpt_prim_clkreq). When clear, GMM will always
assert its clock request.
0h Capability ID (CAPID): Capability ID Value of 05h identifies this linked list item
7:0
RO (capability structure) as being for MSI registers.
0h
15:9 Reserved (RSVD): Reserved
RO
MSI Enable (MSIEN): MSI Enable Controls the ability of GMM to generate MSI
0h Messages. A device driver is prohibited from writing this bit to mask a functions service
0
RW request. 0: MSI will not be generated 1: MSI will be generated. INTA will not be
generated and INTA status is not set.
0h
1:0 Reserved (RSVD): Reserved
RO
0h
31:16 Reserved (RSVD): Reserved
RO
Message Data (MDAT): Message Data Base message data pattern assigned by
0h system software and used to handle an MSI from the device. When the device must
15:0 generate an interrupt request, it writes a 32-bit value to the memory address specified
RW in the MA register. The upper 16 bits are always set to 0. The lower 16 bits are supplied
by this register.
0h Pointer to Next Capability (NXTPTR): This contains a pointer to the next item in
15:8
RO the capabilities list which is the Power Management Capability
0h Capability ID (CAPID): Value of 09h identifies this linked list item (capability
7:0
RO structure) is a vendor specific capability.
0h
11:8 Vendor Specific Capability Revision (VSREV): Reserved for VSID of Fh
RO
0h Vendor Specific Capability Length (VSLEN): This field indicates the number of
7:0
RO bytes in this capability including the CapID and Cap registers.
0h SW LTR Update MMIO Offset Location (SWLTRLOC): The value in this field is
31:4
RO ignored as GMM does not support SW LTR
0h Base Address Register Number (BARNUM): The value in this field is ignored as
3:1
RO GMM does not support SW LTR
0h
0 VALID: Indicates the use of SW LTR by the function.GMM does not use SW LTR
RO
0h
3:1 Base Address Register Number (BARNUM): The DevIdle is located in BAR0
RO
0h
0 VALID: GMM has a DevIdle register
RO
0h
15:13 Reserved (RSVD): Reserved
RO
0h Power On Latency Scale (POLS): Latency Scale multiplier: 010: 1us 011: 32us All
12:10 other settings are reserved. This field is a RO as there is no need for BIOS programing
RO of it.
0h
15:6 Reserved (RSVD): Reserved
RO
0h
4 Reserved (RSVD_1): Reserved
RO
0h Sleep Enable (SE): if clear, then IP will never asset Sleep to the retention flops. If
3 set, then IP may assert Sleep during PGing. Note that some platforms may default this
RO bit to 0, others to 1.
0h D3-Hot Enable (D3HE): If set, then IP will PG when idle and the PMCSR[1:0]
2
RW register in the IP =11.
0h I3 Enable (I3E): If set, then IP will PG when idle and the D0i3 register (D0i3C[2] =
1 1) is set. NOTE: If bits [2:1] = 11, then the IP would PG whenever either PMCSR = 11
RW or the D0i3C.i3 bit is set.
0h PMC Request Enable (PMCRE): If set, then IP will PG when idle and the PMC
0
RW requests power gating by asserting the pmc_*_sw_pg_req_b signal.
0h Next Pointer (NXTPTR): Next Pointer This contains a pointer to next item in
15:8
RO capabilities list. This is the final capability in the list and must be set to 00h.
0h Capability Identifier (CAPID): Capability Identifier Identifies this linked list item as
7:0 being for PCI Power Management registers. This is compliant with the PCI Power
RO Management Interface Specification.
0h
15:11 RO PME Support (PMES): PME Support This device does not support PMEB signal
0h
10 D2 Support (D2S): D2 This device does not support D2
RO
0h
9 D1 Support (D1S): D1 This device does not support D1
RO
0h
8:6 Auxiliary Current (AUXC): Auxiliary Current Reserved. Not applicable for GNA
RO
0h Device Specific Initialization (DSI): Device specific Initialization Indicates that this
5 device requires device specific initialization before generic class device driver is to use
RO it
0h
4 Auxiliary Power (AUXP): Aux Power This device does not use Aux power
RO
0h PME Clock (PMEC): PME Clock indicate this device does NOT support PMEB
3
RO generation
0h VER: Version Hardwired to 010b to indicate there are 4 bytes of power management
2:0 registers implemented and that this device complies with revision 1.1 of the PCI Power
RO Management Interface Specification.
0h PME Generation from D3 (cold) (PMEGD3): PME Generation from D3 (cold) Not
15
RO supported
0h
14:13 Data Scale (DATSC): Data Scale No support for Power Management Data register
RO
0h
12:9 Data Select (DATSEL): Data Select No support for Power Management Data register
RO
0h
8 PME Enable (PMEE): PME Enable PMEB is not supported
RO
0h
7:2 Reserved (RSVD): Reserved
RO
Power State (PS): Indicates the current power state of this device and can be used
to set the device into a new power state. If software attempts to write an unsupported
state to this field, write operation must complete normally on the bus, but the data is
discarded and no state change occurs. 00: D0 01: D1 (Not supported in this device.)
0h 10: D2 (Not supported in this device.) 11: D3 Write of reserved values is ignored and
1:0
RW state will not change. Support of D3cold does not require any special action. While in
the D3hot state, this device can only act as the target of PCI configuration transactions
(for power management control). This device also cannot generate interrupts or
respond to MMR cycles in the D3 state. The device must return to the D0 state in order
to be fully-functional.
0h Next Pointer (NXTPTR): Next Pointer This contains a pointer to next item in
15:8
RO capabilities list. This is the final capability in the list and must be set to 00h.
0h
15:10 Reserved (RSVD): Reserved
RO
0h
9 FLR Capability (FLRCAP): Indicates support for Function Level Reset (FLR).
RO
0h
8 TXP Capability (TXPCAP): Indicates that TP bit is supported
RO
0h Capability Length (CAPLEN): Capability Length This bit indicates the number of
7:0 bytes this vendor specified capability requires. it has a value of 06h for the FLR
RO capability
0h
7:1 Reserved (RSVD): Reserved
RO
0h Initiate FLR (INITFLR): Writing 1 to this field starts the Functional Level Reset.This
0 will act similar to the Abort + will bring all non-CFG registers to their reset value. The
WO FLR is completed when the FLR status bit is cleared
0h
7:1 Reserved (RSVD): Reserved
RO
Access Method
Default: 0h
31:24
0h Reserved (RSVD): Reserved Always returns zero when read
RO
23:18
0h Reserved (RSVDSTS): Reserved for future use
RW/1C/V
15:9
0h Reserved (RSVD_1): Reserved
RO
Access Method
Default: 0h
31:24
0h Reserved (RSVD): Reserved Always returns zero when read
RO
23:19
0h Reserved (RSVDCTL): Reserved for future use
RW
11
0h Reserved (RSVD_1): Reserved Always returns zero when read
RO
7
0h Reserved (RSVD_2): Reserved
RO
Access Method
Default: Fh
31:9
0h Reserved (RSVD): Reserved
RO
7:4
0h Reserved (RSVD_1): Reserved
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
31:11
0h Reserved (RSVD): Reserved
RO
0h Index (IND): Index that select the proper internal status for the
10:0
RW GMM module. Signal list is defined in Table 1-3
Access Method
Default: 0h
Low Status Bits (GNAPISVL): Low Status bits Low Status bits.
0h
31:0 Meaning of field depends on status register selected in the Index
RO/V
field.
Access Method
Default: 0h
High Status bits (GNAPISVH): High Status bits High Status bits
0h
31:0 applicable for some data elements. Meaning of field depends on
RO/V
status register selected in the Index field.
Access Method
Default: 0h
Access Method
Default: 0h
31
0h Reserved1 (RSVD1): Reserved
RW
30:19
0h Reserved (RSVD): Reserved
RO
Access Method
Default: 8h
31:8
0h Reserved (RSVD1): Reserved
RO
7:4
0h Reserved (RSVD): Reserved
RO
Access Method
Default: FFFFFFFFh
Access Method
Default: 18h
31:8
0h Reserved (RSVD): Reserved
RO
18h GNA Input buffer size (GNAIBUFFS): GNA Input Buffer Size.
7:0
RO The size of the input buffer in KB.
Access Method
Default: FFF0FFFFh
Access Method
Default: FFF0FFFFh
Access Method
Default: FFF0FFFFh
Access Method
Default: FFF0FFFFh
Access Method
Default: 0h
31:8
0h Reserved (RSVD): Reserved
RO
7:0
0h GNA SAIV Setup (GNASAIV): Outgoing SAI of GNA
RO
§§
7 SMBus Registers
This chapter documents the registers in Bus: 0, Device 31, Function 1.
0h
15:0 Vendor ID (VID): Value indicates Intel as the vendor
RO
0h
15:0 Device ID (DID): Indicates the device number assigned by the SIG.
RO/V
0h
15:11 Reserved (RSVD): Reserved
RO
0h Interrupt Disable (INTD): 1 = Disables SMBus to assert its PIRQB# signal. Defaults
10
RW to 0.
0h
9 Fast Back to Back Enable (FBE): Reserved as 0. Read Only.
RO
0h
8 SERR# Enable (SERRE): 1 = Enables SERR# generation
RW
0h
7 Wait Cycle Control (WCC): Reserved as 0. Read Only.
RO
0h Parity Error Response (PER): 1 = Sets Detected Parity Error bit when parity error is
6
RW detected
0h
5 VGA Palette Snoop (VGAPS): Reserved as 0. Read Only.
RO
0h
4 Postable Memory Write Enable (PMWE): Reserved as 0. Read Only.
RO
0h
3 Special Cycle Enable (SCE): Reserved as 0. Read Only.
RO
0h
2 Bus Master Enable (BME): Reserved as 0. Read Only.
RO
0h
1 Memory Space Enable (MSE): 1= Enables memory mapped config space.
RW
0h I/O Space Enable (IOSE): 1= enables access to the SM Bus I/O space registers as
0
RW defined by the Base Address Register.
0h Detected Parity Error (DPE): Set when the bridge detects a parity error on the
15
RW/1C internal backbone. This bit gets set even if CMD.PERE is not set.
0h Signaled System Error (SSE): Set when the SMBus signals a system error to the
14
RW/1C internal SERR# logic.
0h
13 Received Master Abort (RMA): Reserved as 0.
RO
0h
12 Received Target Abort (RTA): Reserved as '0'.
RO
0h
11 Signaled Target-Abort Status (STA): Reserved as 0.
RW/1C
DEVSEL# Timing Status (DEVT): This 2-bit field defines the timing for DEVSEL#
0h assertion. These read only bits indicate the SoC's DEVSEL# timing when performing a
10:9
RO positive decode. Note: SoC generates DEVSEL# with medium time. Note: It is not clear
if a PCI master can write to SMBus controller.
0h
8 Data Parity Error Detected (DPED): Reserved as 0.
RO
0h
7 Fast Back-to-Back Capable (FBC): Reserved as '1'.
RO
0h
6 User Definable Features (UDF): Reserved as 0.
RO
0h
5 66 MHz Capable (C_66M): Reserved as 0.
RO
0h
2:0 Reserved (RSVD): Reserved
RO
0h Revision ID (RID): The value reported in this register depends on theglobal revision
7:0
RO ID for the PCH.
0h
7:0 Programming Interface (PI): No programming interface defined.
RO
0h Sub Class Code (SCC): A value of 05h indicates that this device is a SM Bus serial
7:0
RO controller.
0h
7:0 Base Class Code (BCC): A value of 0Ch indicates that this device is a serial controller
RO
0h
31:8 BA: Provides the 32 byte system memory base address for the SoC SMB logic.
RW
0h
7:4 HARDWIRED_0: Hardwired to 0.
RO
0h
3 PREF: Hardwired to 0. Indicated that SMBMBAR is not pre- fetchable
RO
0h Address Range (ADDRNG): Indicates that this SMBMBAR can be located anywhere
2:1
RO in 64 bit address space
0h
0 Memory Space Indicator (MSI): Indicates that the SMB logic is memory mapped.
RO
0h
31:0 BA: Bits 63-32 of SMbus Memory Base Address
RW
0h
31:16 Reserved (RSVD): Reserved
RO
0h
15:5 BA: Provides the 32 byte t system I/O base address for the SMB logic.
RW
0h
4:1 Reserved (RSVD_1): Reserved
RO
0h IO Space Indicator (IOSI): This read-only bit always is 1, indicating that the SMB
0
RO logic is I/O mapped.
SVID: BIOS sets the value in this register to identify the Subsystem Vendor ID. The
0h SMBus SVID register, in combination with the SMBus Subsystem ID register, enables
15:0 the operating system to distinguish each subsystem from the others. Note: The
RW/O software can write to this register only once per core well reset. Writes should be done
as a single 16-bit cycle.
SID: BIOS can write to this register to identify the Subsystem ID. The SID register, in
0h combination with the SVID, enable the operating system to distinguish each subsystem
15:0
RW/O from other(s). Note: The software can write to this register only once per core well
reset. Writes should be done as a single 16-bit cycle.
0h Interrupt Line (INTLN): This data is not used by the hardware. It is to communicate
7:0
RW to software the interrupt line that the interrupt pin is connected to PIRQB#.
0h Interrupt Pin (INTPN): This defines the interrupt pin to be used by the SMBus
7:0 controller. Bits : Pins 0h : No Interrupt 1h : INTA# 2h : INTB# 3h : INTC# 4h : INTD#
RW/O 5h-Fh : Reserved.
0h
7:5 Reserved (RSVD): Reserved
RO
SPD Write Disable (SPDWD): This bit is must be set to '1' to disable writes to SPD
which are on Host SMB address ranges A0h - AEh. The SMBus range is unwriteable
until next platform reset. HW Default is '0.' Note: This bit is RW O and will be reset on
0h PLTRST# reset. This should be set by BIOS memory reference code to '1'. SW can only
4
RW/1L program this bit when both HCTL(6) = 0 (START) and HSTS(0) = 0 (HBSY), else it may
result in an undefined behavior. [Noted in HSTS.HBSY that states "No SMB registers
should be accessed while HSTS.HBSY bit is set, the same will apply to SPD write
disable. 3 RW 0 SSRESET : Soft SMBUS Reset: When this bit is 1,
0h SSRESET: Soft SMBUS Reset: When this bit is 1, the SMbus state machine and logic
3
RW in PCH is reset. The HW will reset this bit to 0 when reset operation is completed.
0h I2C_EN (I2CEN): When this bit is 1, the SoC is enabled to communicate with I2C
2 devices. This will change the formatting of some commands. When this bit is 0,
RW behavior is for SMBus.
0h SMB_SMI_EN (SSEN): When this bit is set, any source of an SMB interrupt will
1
RW instead be routed to generate an SMI#.
HST_EN (HSTEN): When set, the SMB Host Controller interface is enabled to execute
0h commands. The HST_INT_EN bit needs to be enabled in order for the SMB Host
0
RW Controller to interrupt or SMI#. Additionally, the SMB Host Controller will not respond
to any new requests until all interrupt requests have been cleared.
7.17 B-Unit Copy of the TCO Base Address Register for Legacy
SMBUS (B_CR_TCOBASE_SMBUS) — Offset 50h
0h
31:16 Reserved (RSVD): Reserved
RO
0h TCO Base Address (TCOBA): Provides the 32 bytes of I/O space for TCO logic,
15:5
RW/V mappable anywhere in the 64k I/O space on 32-byte boundaries.
0h
4:0 Reserved (RSVD): Reserved
RO
7.18 B-Unit Copy of the TCO Control Register for Legacy SMBUS
(B_CR_TCOCTL_SMBUS) — Offset 54h
0h
31:9 Reserved (RSVD): Reserved
RO
0h TCO Base Enable (TCO_BASE_EN): When set, decode of the I/O range pointed to
8
RW/V by the TCO base register is enabled.
0h
7:0 Reserved (RSVD): Reserved
RO
0h
31:28 Reserved (RSVD): Reserved
RO
0h
27:24 Dot Portion of Process ID (DPID): Indicates the dot process as x.8
RO/V
0h Stepping ID (SID): This field is incremented for each stepping of the part. Note that
23:16 this field can be used by software to differentiate steppings when the Revision ID may
RO/V not change.
0h
15:8 Manufacturer (MAFA): 0Fh = Intel
RO/V
0h
7:0 Process/Dot (PD): Indicates that the process base is 1271.
RO/V
Access Method
Default: 0h
Failed (FAIL): When set, this indicates that the source of the
0h
4 interrupt or SMI# was a failed bus transaction. This is set in
RW/1C
response to the KILL bit being set to terminate the host transaction.
0h Bus Error (BERR): When set, this indicates the source of the
3
RW/1C interrupt or SMI# was a transaction collision.
Device Error (DERR): When set, this indicates that the source of
0h the interrupt or SMI# was due one of the following: Illegal
2
RW/1C Command Field Unclaimed Cycle (host initiated) Host Device Time-
out Error. CRC Error
Interrupt (INTR): When set, this indicates that the source of the
0h
1 interrupt or SMI# was the successful completion of its last
RW/1C
command.
Host Busy (HBSY): A 1 indicates that the SoC is running a
command from the host interface. No SMB registers should be
accessed while this bit is set. Exception: The BLOCK DATA
0h
0 REGISTER can be accessed when this bit is set ONLY when the
RW/1C
SMB_CMD bits (in Host control register) are programmed for Block
command or I2C Read command. This is necessary in order to
check the DONE_STS bit.
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
0
0h RW (RW): Direction of the host transfer. 1 = read, 0 = write
RW
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 44h
0h Reserved (RSVD)
7
RO
Access Method
Default: 0h
Access Method
Default: 0h
0h Reserved (RSVD)
7:5
RO
Access Method
Default: 0h
0h Reserved (RSVD)
7:2
RO
Enable 32-byte Buffer (E32B): When set, the Host Block Data
0h register is a pointer into a 32-byte buffer, as opposed to a single
1
RW register. This enables the block commands to transfer or receive up
to 32-bytes before the SoC generates an interrupt.
Automatically Append CRC (AAC): When set, the SoC will
0h automatically append the CRC. This bit must not be changed during
0
RW SM Bus transactions, or undetermined behavior will result. It should
be programmed only once during the lifetime of the function.
Access Method
Default: 4h
0h Reserved (RSVD)
7:3
RO
Access Method
Default: 4h
0h Reserved (RSVD)
7:3
RO
Access Method
Default: 0h
0h Reserved (RSVD)
7:1
RO
Access Method
Default: 0h
0h Reserved (RSVD)
7:3
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 4h
0h Reserved (RSVD)
15:10
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
0h Reserved (RSVD)
15:14
RO
Access Method
Default: 0h
0h Reserved (RSVD)
15:5
RO
Access Method
Default: 0h
0h Reserved (RSVD)
15:13
RO
Access Method
Default: 8h
0h Reserved (RSVD)
15:6
RO
Access Method
Default: 0h
Access Method
Default: 0h
Default: 0h
0h Reserved (RSVD)
7:0
RO
Access Method
Default: 3h
0h Reserved (RSVD)
7:2
RO
Default: 0h
0h Reserved (RSVD)
7:0
RO
Access Method
Default: 4h
0h Reserved (RSVD)
15:10
RO
TCOTMR (TCOTMR): Value that is loaded into the timer each time
the TCO_RLD register is written. Values of 0000h or 0001h will be
4h ignored and should not be attempted. The timer is clocked at
9:0
RW approximately 0.6 seconds, and thus allows timeouts ranging from
1.2 second to 613.8 seconds. Note: The timer has an error of +/- 1
tick (0.6s).
Default: 0h
0h Reserved (RSVD)
63:0
RO
Default: 0h
0h Reserved (RSVD)
31:0
RO
§§
8 LPC Registers
This chapter documents the registers in Bus: 0, Device 31, Function 0.
8.1 ID — Offset 0h
0h
22:21 Device Identification 5 (DID_5): Device Identification 5 is hardwired to 2'b11.
RO/V
0h
15:0 Vendor Identification (VID): Indicates Intel.
RO
0h
15:11 Reserved (RSVD): Reserved
RO
0h
10 Interrupt Disable (ID): The LPC bridge has no interrupts to disable.
RO
0h
9 Fast Back to Back Enable (FBE): Reserved as 0 per PCI-Express spec.
RO
0h
8 SERR# Enable (SEE): The LPC bridge generates SERR# if this bit is set.
RW
0h
7 Wait Cycle Control (WCC): Reserved as 0 per PCI-Express spec.
RO
0h Parity Error Response Enable (PERE): When this bit is set to 1, it enables the LPC
6
RW bridge to response to parity errors detected on backbone interface.
0h
5 VGA Palette Snoop (VGA_PSE): Reserved as 0 per PCI-Express spec.
RO
0h
3 Special Cycle Enable (SCE): Reserved as 0 per PCI-Express spec.
RO
0h
2 Bus Master Enable (BME): Bus Masters cannot be disabled.
RO
0h
1 Memory Space Enable (MSE): Memory space cannot be disabled on LPC.
RO
0h
0 I/O Space Enable (IOSE): I/O space cannot be disabled on LPC.
RO
0h Detected Parity Error (DPE): Set when the bridge detects a parity error on the
15
RW/1C internal backbone. This bit gets set even if CMD.PERE is not set.
0h Signaled System Error (SSE): Set when the LPC bridge signals a system error to
14
RW/1C the internal SERR# logic.
0h Received Master Abort (RMA): Set when the bridge receives a completion with
13
RO unsupported request status from the backbone. LPC is a target only controller.
0h Received Target Abort (RTA): Set when the bridge receives a completion with
12
RO completer abort status from the backbone. LPC is a target only controller.
0h Signalled Target Abort (STA): Set when the bridge generates a completion packet
11
RW/1C with target abort status on the backbone.
0h DEVSEL# Timing Status (DTS): Indicates medium timing, although this has no
10:9
RO meaning on the backbone.
0h Data Parity Error Detected (DPD): Set when the bridge receives a completion
8 packet from the backbone from a previous request, and detects a parity error, and
RW/1C CMD.PERE is set.
0h Fast Back to Back Capable (FBC): Reserved - bit has no meaning on internal
7
RO backbone.
0h
6 Reserved (RSVD): Reserved
RO
0h
5 66 MHz Capable (C66): Reserved - bit has no meaning on internal backbone.
RO
0h
4 Capabilities List (CLIST): There is a capabilities list in the LPC bridge.
RO
0h
3 Interrupt Status (IS): The LPC bridge does not generate interrupts.
RO
0h
2:0 Reserved (RSVD_1): Reserved
RO
0h Revision ID (RID): Indicates the part revision. This will reset to 0 but is expected to
7:0
RO/V be overridden by the SetID IOSF-SB message.
0h
31:24 Reserved (RSVD): Reserved
RO
0h
23:16 Base Class Code (BCC): Indicates the device is a bridge device.
RO
0h
15:8 Sub-Class Code (SCC): Indicates the device a PCI to ISA bridge.
RO
0h
7:0 RO Programming Interface (PI): The LPC bridge has no programming interface.
0h
7:3 Master Latency Count (MLC): Reserved per 3GIO spec.
RO
0h
2:0 Reserved (RSVD): Reserved
RO
0h
7 Multi-function Device (MFD): This bit is 1 to indicate a multifunction device.
RO
0h Header Type (HTYPE): Identifies the header layout of the configuration space, which
6:0
RO is a generic device.
0h
7:0 Capability Pointer (CP): Indicates the offset of the first Capability Item.
RO
0h
7 EN: When set, serial IRQs will be recognized.
RW
Mode (MD): When set, the serial IRQ machine will be in continuous mode. When
0h cleared, the serial IRQ machine will be in quiet mode. When setting the EN bit, this bit
6
RW must also be written as a one to guarantee that the first action of the serial IRQ
machine will be a start frame.
0h Frame Size (FS): Fixed field that indicates the size of the SERIRQ frame as 21
5:2
RO frames.
Start Frame Pulse Width (SFPW): This is the number of 33 MHz clocks that the
SERIRQ pin will be driven low by the Serial IRQ controller to signal a start frame. In
continuous mode, the controller will drive the start frame for the number of clocks
specified. In quiet mode, the controller will drive the start frame for the number of
0h clocks specified minus one, as the first clock was driven by the peripheral. Bits Clocks
1:0
RW • 00: 4
• 01: 6
• 10: 8
• 11: Reserved
8.11 B-Unit Copy of the I/O Decode Ranges Register for LPC
(B_CR_IOD_IOE_LPC) — Offset 80h
Affects B-Unit SAD for LPC regions.
0h
31:26 Reserved (RSVD): Reserved
RO
0h High Gameport Enable (HGE): Enables decoding of the I/O locations 208h to 20Fh
25
RW/V to LPC.
0h Low Gameport Enable (LGE): Enables decoding of the I/O locations 200h to 207h to
24
RW/V LPC.
0h
23:20 Reserved (RSVD): Reserved
RO
0h Floppy Drive Enable (FDE): Enables decoding of the FDD range to LPC. Range is
19
RW/V selected by LIOD.FDE.
0h Parallel Port Enable (PPE): Enables decoding of the LPT range to LPC. Range is
18
RW/V selected by LIOD.LPT.
0h Com Port B Enable (CBE): Enables decoding of the ComB range to LPC. Range is
17
RW/V selected LIOD.CB.
0h Com Port A Enable (CAE): Enables decoding of the ComA range to LPC. Range is
16
RW/V selected LIOD.CA.
0h
15:13 Reserved (RSVD): Reserved
RO
FDD: The following table describes which range to decode for the FDD Port.
0h
12 • 0 => 3F0h-3F5h, 3F7h (Primary)
RW/V
• 1 => 370h-375h, 377h (Secondary)
0h
11:10 Reserved (RSVD): Reserved
RO
LPT: The following table describes which range to decode for the LPT Port.
• 00: 378h-37Fh and 778h-77Fh
0h
9:8 • 01: 278h-27Fh (port 279h is read only) and 678h-67Fh
RW/V
• 10: 3BCh-3BEh and 7BCh-7BEh
• 11: Reserved
0h
7 Reserved (RSVD): Reserved
RO
ComB Range (CB): The following table describes which range to decode for the
ComB Port.
• 000: 3F8h-3FFh (COM 1)
• 001: 2F8h-2FFh (COM 2)
0h • 010: 220h-227h
6:4
RW/V • 011: 228h-22Fh
• 100: 238h-23Fh
• 101: 2E8h-2EFh (COM 4)
• 110: 338h-33Fh
• 111: 3E8h-3EFh (COM 3)
0h
3 Reserved (RSVD): Reserved
RO
ComA Range (CA): The following table describes which range to decode for the
ComA Port.
• 000: 3F8h-3FFh (COM 1)
• 001: 2F8h-2FFh (COM 2)
0h • 010: 220h-227h
2:0
RW/V • 011: 228h-22Fh
• 100: 238h-23Fh
• 101: 2E8h-2EFh (COM 4)
• 110: 338h-33Fh
• 111: 3E8h-3EFh (COM 3)
0h
15:14 Reserved (RSVD): Reserved
RO
0h Microcontroller Enable #2 (ME2): Enables decoding of I/O locations 4Eh and 4Fh
13
RW to LPC.
0h
12 SuperI/O Enable (SE): Enables decoding of I/O locations 2Eh and 2Fh to LPC.
RW
0h Microcontroller Enable #1 (ME1): Enables decoding of I/O locations 62h and 66h
11
RW to LPC.
0h
10 KE: Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
RW
0h High Gameport Enable (HGE): Enables decoding of the I/O locations 208h to 20Fh
9
RW to LPC.
0h Low Gameport Enable (LGE): Enables decoding of the I/O locations 200h to 207h to
8
RW LPC.
0h
7:4 Reserved (RSVD_1): Reserved
RO
0h Floppy Drive Enable (FDE): Enables decoding of the FDD range to LPC. Range is
3
RW selected by LIOD.FDE
0h Parallel Port Enable (PPE): Enables decoding of the LPT range to LPC. Range is
2
RW selected by LIOD.LPT.
0h Com Port B Enable (CBE): Enables decoding of the COMB range to LPC. Range is
1
RW selected LIOD.CB.
0h Com Port A Enable (CAE): Enables decoding of the COMA range to LPC. Range is
0
RW selected LIOD.CA.
0h
31:24 Reserved (RSVD): Reserved
RO
Address [7:2] Mask (ADDR_MASK_7_2): A '1' in any bit position indicates that
0h any value in the corresponding address bit in a received cycle will be treated as a
23:18 match. The corresponding bit in the Address field, below, is ignored. The mask is only
RW/V provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
0h Address [15:2] (ADDR_15_2): DWord-aligned address. Note that PCH does not
15:2
RW/V provide decode down to the word or byte level.
0h
1 Reserved (RSVD): Reserved
RO
0h LPC Decode Enable (EN): When this bit is set to '1', then the range specified in this
0
RW/V register is enabled for decoding to LPC.
0h
31:24 Reserved (RSVD): Reserved
RO
Address [7:2] Mask (ADDR_MASK_7_2): A '1' in any bit position indicates that
0h any value in the corresponding address bit in a received cycle will be treated as a
23:18 match. The corresponding bit in the Address field, below, is ignored. The mask is only
RW/V provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
0h
17:16 Reserved (RSVD): Reserved
RO
0h Address [15:2] (ADDR_15_2): DWord-aligned address. Note that PCH does not
15:2
RW/V provide decode down to the word or byte level.
0h
1 Reserved (RSVD): Reserved
RO
0h LPC Decode Enable (EN): When this bit is set to '1', then the range specified in this
0
RW/V register is enabled for decoding to LPC.
0h
31:24 Reserved (RSVD): Reserved
RO
Address [7:2] Mask (ADDR_MASK_7_2): A '1' in any bit position indicates that
0h any value in the corresponding address bit in a received cycle will be treated as a
23:18 match. The corresponding bit in the Address field, below, is ignored. The mask is only
RW/V provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
0h
17:16 Reserved (RSVD): Reserved
RO
0h Address [15:2] (ADDR_15_2): DWord-aligned address. Note that PCH does not
15:2
RW/V provide decode down to the word or byte level.
0h
1 Reserved (RSVD): Reserved
RO
0h LPC Decode Enable (EN): When this bit is set to '1', then the range specified in this
0
RW/V register is enabled for decoding to LPC.
0h
31:24 Reserved (RSVD): Reserved
RO
Address [7:2] Mask (ADDR_MASK_7_2): A '1' in any bit position indicates that
0h any value in the corresponding address bit in a received cycle will be treated as a
23:18 match. The corresponding bit in the Address field, below, is ignored. The mask is only
RW/V provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
0h
17:16 Reserved (RSVD): Reserved
RO
0h Address [15:2] (ADDR_15_2): DWord-aligned address. Note that PCH does not
15:2
RW/V provide decode down to the word or byte level.
0h
1 Reserved (RSVD): Reserved
RO
0h LPC Decode Enable (EN): When this bit is set to '1', then the range specified in this
0
RW/V register is enabled for decoding to LPC.
0h
31:16 Reserved (RSVD): Reserved
RO
0h
14 Reserved (RSVD_1): Reserved
RO
0h
13 Reserved (RSVD_2): Reserved
RW
0h
12 Reserved (RSVD_3): Reserved
RO
SMI Caused by Port 64 Write (TRAPBY64W): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 3, then this bit will still be
11 active. It is up to the SMM code to use the enable bit to determine the exact cause of
RW/1C the SMI#. Writing a 1 to this bit will clear the latch. Note that the A20Gate Pass-
Through Logic allows specific port 64h Writes to complete without setting this bit.
SMI Caused by Port 64 Read (TRAPBY64R): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 2, then this bit will still be
10
RW/1C active. It is up to the SMM code to use the enable bit to determine the exact cause of
the SMI#. Writing a 1 to this bit will clear the latch.
SMI Caused by Port 60 Write (TRAPBY60W): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 1, then this bit will still be
9 active. It is up to the SMM code to use the enable bit to determine the exact cause of
RW/1C the SMI#. Writing a 1 to this bit will clear the latch. Note that the A20Gate Pass-
Through Logic allows specific port 60h Writes to complete without setting this bit.
SMI Caused by Port 60 Read (TRAPBY60R): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 0, then this bit will still be
8
RW/1C active. It is up to the SMM code to use the enable bit to determine the exact cause of
the SMI#. Writing a 1 to this bit will clear the latch.
0h Pass Through State (PSTATE): This read-only bit indicates that the state machine
6 is in the middle of an A20GATE pass-through sequence. If software needs to reset this
RO bit, it should set Bit 5 0.
0h
4 Reserved (RSVD_4): Reserved
RW
0h SMI on Port 64 Writes Enable (S64WEN): When set, a 1 in bit 11 will cause an
3
RW SMI event.
0h SMI on Port 64 Reads Enable (S64REN): When set, a 1 in bit 10 will cause an SMI
2
RW event.
0h SMI on Port 60 Writes Enable (S60WEN): When set, a 1 in bit 9 will cause an SMI
1
RW event.
0h SMI on Port 60 Reads Enable (S60REN): When set, a 1 in bit 8 will cause an SMI
0
RW event.
8.18 B-Unit Copy of the LPC Generic Memory Range Register for
LPC (B_CR_LGMR_LPC) — Offset 98h
Affects B-Unit SAD for LPC regions.
0h
15:1 Reserved (RSVD): Reserved
RO
0h LPC Memory Range Decode Enable (EN): When this bit is set to '1', then the range
0
RW/V specified in this register is enabled for decoding to LPC.
0h
31:0 Reserved (RSVD): Reserved
RO
0h
31:24 Reserved (RSVD): Reserved
RO
Address [7:2] Mask (ADDR_MASK_7_2): A '1' in any bit position indicates that
0h any value in the corresponding address bit in a received cycle will be treated as a
23:18 match. The corresponding bit in the Address field, below, is ignored. The mask is only
RW/V provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
0h
17:16 Reserved (RSVD): Reserved
RO
0h
1 Reserved (RSVD): Reserved
RO
0h LPC Decode Enable (EN): When this bit is set to '1', then the range specified in this
0
RW/V register is enabled for decoding to LPC (eSPI).
0h
15:1 Reserved (RSVD): Reserved
RO
0h LPC Memory Range Decode Enable (EN): When this bit is set to '1', then the range
0
RW/V specified in this register is enabled for decoding to LPC (eSPI).
0h
31:28 F8-FF IDSEL (IF8): IDSEL to use in FWH cycle for range enabled by BDE.EF8.
RO
0h
27:24 F0-F7 IDSEL (IF0): IDSEL to use in FWH cycle for range enabled by BDE.EF0.
RW
0h
23:20 E8-EF IDSEL (IE8): IDSEL to use in FWH cycle for range enabled by BDE.EE8.
RW
0h
19:16 E0-E7 IDSEL (IE0): IDSEL to use in FWH cycle for range enabled by BDE.EE0.
RW
0h
15:12 D8-DF IDSEL (ID8): IDSEL to use in FWH cycle for range enabled by BDE.ED8.
RW
0h
11:8 D0-D7 IDSEL (ID0): IDSEL to use in FWH cycle for range enabled by BDE.ED0.
RW
0h
7:4 C8-CF IDSEL (IC8): IDSEL to use in FWH cycle for range enabled by BDE.EC8.
RW
0h
3:0 C0-C7 IDSEL (IC0): IDSEL to use in FWH cycle for range enabled by BDE.EC0.
RW
0h
15:12 70-7F IDSEL (I70): IDSEL to use in FWH cycle for range enabled by BDE.E70.
RW
0h
11:8 60-6F IDSEL (I60): IDSEL to use in FWH cycle for range enabled by BDE.E60.
RW
0h
7:4 50-5F IDSEL (I50): IDSEL to use in FWH cycle for range enabled by BDE.E50.
RW
0h
3:0 40-4F IDSEL (I40): IDSEL to use in FWH cycle for range enabled by BDE.E40.
RW
8.24 B-Unit Copy of the BIOS Decode Enable Register for LPC
(B_CR_BDE_LPC) — Offset D8h
Affects B-Unit SAD for BIOS regions only when BIOS is resident in LPC.
0h
31:16 Reserved (RESERVED_0): Reserved
RO
1h F8-FF Enable (EF8): Enables decoding of 512K of the following BIOS ranges:
15
RO FFF80000h-FFFFFFFFh and FFB80000h-FFBFFFFFh.
1h F0-F8 Enable (EF0): Enables decoding of 512K of the following BIOS ranges:
14
RW/V FFF00000h-FFF7FFFFh and FFB00000h-FFB7FFFFh.
1h E8-EF Enable (EE8): Enables decoding of 512K of the following BIOS ranges:
13
RW/V FFE80000h-FFEFFFFFh and FFA80000h-FFAFFFFFh.
1h E0-E8 Enable (EE0): Enables decoding of 512K of the following BIOS ranges:
12
RW/V FFE00000h-FFE7FFFFh and FFA00000h-FFA7FFFFh.
1h D8-DF Enable (ED8): Enables decoding of 512K of the following BIOS ranges:
11
RW/V FFD80000h-FFDFFFFFh and FF980000h-FF9FFFFFh.
1h D0-D7 Enable (ED0): Enables decoding of 512K of the following BIOS ranges:
10
RW/V FFD00000h-FFD7FFFFh and FF900000h-FF97FFFFh.
1h C8-CF Enable (EC8): Enables decoding of 512K of the following BIOS ranges:
9
RW/V FFC80000h-FFCFFFFFh and FF880000h-FF8FFFFFh.
1h C0-C7 Enable (EC0): Enables decoding of 512K of the following BIOS ranges:
8
RW/V FFC00000h-FFC7FFFFh and FF800000h-FF87FFFFh.
1h Legacy F Segment Enable (LFE): This enables the decoding of the legacy 64KB
7
RW/V range at F0000h-FFFFFh.
1h Legacy E Segment Enable (LEE): This enables the decoding of the legacy 64KB
6
RW/V range at E0000h-EFFFFh.
0h
5:4 Reserved (RESERVED_1): Reserved
RO
1h 70-7F Enable (E70): Enables decoding of 1MB of the following BIOS ranges:
3
RW/V FF700000h-FF7FFFFFh and FF300000h-FF3FFFFFh.
1h 60-6F Enable (E60): Enables decoding of 1MB of the following BIOS ranges:
2
RW/V FF600000h-FF6FFFFFh and FF200000h-FF2FFFFFh.
1h 50-5F Enable (E50): Enables decoding of 1MB of the following BIOS ranges:
1
RW/V FF500000h-FF5FFFFFh and FF100000h-FF1FFFFFh.
1h 40-4F Enable (E40): Enables decoding of 1MB of the following BIOS ranges:
0
RW/V FF400000h-FF4FFFFFh and FF000000h-FF0FFFFFh.
BIOS Interface Lock-Down (BILD): When set, prevents BC.TS and BC.BBS from
0h being changed. This bit can only be written from 0 to 1 once. BIOS Note: This bit is not
7
RW/1L backed up in the RTC well. This bit should also be set in the BUC register in the RTC
device to record the last state of this value following a cold reset.
Boot BIOS Strap (BBS): This field determines the destination of accesses to the
BIOS memory range.
0h • 0: SPI
6 • 1: LPC
RW/L
When SPI or LPC is selected, the range that is decoded is further qualified by other
configuration bits. The value in this field can be overwritten by software as long as the
BIOS Interface Lock-Down is not set.
Enable InSMM.STS (EISS): When this bit is set, the BIOS region is not writable until
0h SMM sets the InSMM.STS bit. Today BIOS Flash is writable if WPD is a 1. If this bit [5]
5 is set, then WPD must be a 1 and InSMM.STS (0xFED3_0880[0]) must be 1 also. If this
RW/L bit [5] is clear, then BIOS is writable based only on WPD = 1 and the InSMM.STS is a
don't care.
Top Swap (TS): When set, PCH will invert either A16, A17, or A18 for cycles going to
the BIOS space (but not the feature space) in the FWH. When cleared, PCH will not
invert A16. If booting from LPC (FWH), then the Boot Block size is 64KB and A16 is
0h inverted if Top Swap is enabled. If booting from SPI, then the BOOT_BLOCK_SIZE soft
4
RO strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. *If PCH
is strapped for Top-Swap (GNT[3]# is low at rising edge of PWROK), then this bit
cannot be cleared by software. The strap jumper should be removed and the system
rebooted. BIOS Note: [list=1]
Access Method
Default: 0h
0h Res_rbr (Res_rbr)
31:8
NA
0h rbr (rbr)
7:0
RO
Access Method
Default: 0h
0h Res_thr (Res_thr)
31:8
NA
0h thr (thr)
7:0
WO
Default: 0h
0h Res_dll (Res_dll)
31:8
NA
0h dll (dll)
7:0
RW
Default: 0h
0h Res_31_8 (Res_31_8)
31:8
NA
0h PTIME (PTIME)
7
RW
0h Res_6_4 (Res_6_4)
6:4
NA
0h EDSSI (EDSSI)
3
RW
0h ELSI (ELSI)
2
RW
0h ETBEI (ETBEI)
1
RW
0h ERBFI (ERBFI)
0
RW
Default: 0h
0h Res_31_8 (Res_31_8)
31:8
NA
0h dlh (dlh)
7:0
RW
Default: 1h
0h Res_31_8 (Res_31_8)
31:8
NA
0h FIFOSE (FIFOSE)
7:6
RO
0h Res_5_4 (Res_5_4)
5:4
NA
1h IID (IID)
3:0
RO
Default: 1h
0h Res_31_8 (Res_31_8)
31:8
NA
0h RCVR (RCVR)
7:6
WO
0h TET (TET)
5:4
WO
0h DMAM (DMAM)
3
WO
0h XFIFOR (XFIFOR)
2
WO
0h RFIFOR (RFIFOR)
1
WO
1h FIFOE (FIFOE)
0
WO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:6 Reserved.
RO
Access Method
Default: 60h
0h
31:8 Reserved.
RO
RFE (RFE): Receiver FIFO Error bit. This bit is only relevant when
FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one).
This is used to indicate if there is at least one parity error, framing
0h
7 error, or break indication in the FIFO. 0 = no error in RX FIFO 1 =
RW
error in RX FIFO This bit is cleared when the LSR is read and the
character with the error is at the top of the receiver FIFO and there
are no subsequent errors in the FIFO. Reset Value: 0x0
TEMT (TEMT): Transmitter Empty bit. If in FIFO mode
(FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this
1h bit is set whenever the Transmitter Shift Register and the FIFO are
6
RW both empty. If in non-FIFO mode or FIFOs are disabled, this bit is
set whenever the Transmitter Holding Register and the Transmitter
Shift Register are both empty. Reset Value: 0x1
Access Method
Default: 0h
0h
31:8 Reserved.
RO
0h DCD (DCD)
7
RO
0h RI (RI)
6
RO
0h DSR (DSR)
5
RO
0h CTS (CTS)
4
RO
0h DDCD (DDCD)
3
RO
0h TERI (TERI)
2
RO
0h DDSR (DDSR)
1
RO
0h DCTS (DCTS)
0
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 0h
0h
31:1 Reserved.
RO
Access Method
Default: 0h
0h
31:8 Reserved.
RO
tfr (tfr): Transmit FIFO Read. These bits are only valid when FIFO
access mode is enabled (FAR[0] is set to one). When FIFOs are
implemented and enabled, reading this register gives the data at
0h
7:0 the top of the transmit FIFO. Each consecutive read pops the
RW
transmit FIFO and gives the next data value that is currently at the
top of the FIFO. When FIFOs are not implemented or not enabled,
reading this register gives the data in the THR. Reset Value: 0x0
Access Method
Default: 0h
0h Reserved (Res_31_10)
31:10
NA
0h RFFE (RFFE)
9
WO
0h RFPE (RFPE)
8
WO
0h RFWD (RFWD)
7:0
WO
Access Method
Default: 6h
0h
31:5 Reserved.
RO
RFF (RFF): Receive FIFO Full. This bit is only valid when
0h FIFO_STAT == YES. This is used to indicate that the receive FIFO is
4
RO completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This
bit is cleared when the RX FIFO is no longer full. Reset Value: 0x0
RFNE (RFNE): Receive FIFO Not Empty. This bit is only valid when
FIFO_STAT == YES. This is used to indicate that the receive FIFO
0h
3 contains one or more entries. 0 = Receive FIFO is empty 1 =
RO
Receive FIFO is not empty This bit is cleared when the RX FIFO is
empty. Reset Value: 0x0
TFE (TFE): Transmit FIFO Empty. This bit is only valid when
FIFO_STAT == YES. This is used to indicate that the transmit FIFO
1h
2 is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit
RO
FIFO is empty This bit is cleared when the TX FIFO is no longer
empty. Reset Value: 0x1
TFNF (TFNF): Transmit FIFO Not Full. This bit is only valid when
1h FIFO_STAT == YES. This is used to indicate that the transmit FIFO
1
RO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full. Reset Value: 0x1
BUSY (BUSY): UART Busy. This bit is valid only when
UART_16550_COMPATIBLE == NO and indicates that a serial
transfer is in progress, ; when cleared, indicates that the
DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or
inactive 1 = DW_apb_uart is busy (actively transferring data)
NOTE: It is possible for the UART Busy bit to be cleared even
though a new character may have been sent from another device.
0h
0 That is, if the DW_apb_uart has no data in THR and RBR and there
RO
is no transmission in progress and a start bit of a new character has
just reached the DW_apb_uart. This is due to the fact that a valid
start is not seen until the middle of the bit period and this duration
is dependent on the baud divisor that has been programmed. If a
second system clock has been implemented (CLOCK_MODE ==
Enabled), the assertion of this bit is also delayed by several cycles
of the slower clock. Reset Value: 0x0
Access Method
Default: 0h
0h
31:5 Reserved.
RO
0h tfl (tfl): Transmit FIFO Level. This is indicates the number of data
4:0
RO entries in the transmit FIFO. Reset Value: 0x0
Access Method
Default: 0h
0h
31:5 Reserved.
RO
0h rfl (rfl): Receive FIFO Level. This is indicates the number of data
4:0
RO entries in the receive FIFO. Reset Value: 0x0
Access Method
Default: 0h
0h
31:3 Reserved.
RO
XFR (XFR): XMIT FIFO Reset. This is a shadow register for the
XMIT FIFO Reset bit (FCR[2]). This can be used to remove the
burden on software having to store previously written FCR values
(which are pretty static) just to reset the transmit FIFO. This resets
0h the control portion of the transmit FIFO and treats the FIFO as
2
RW empty. This also de-asserts the DMA TX request and single signals
when additional DMA handshaking signals are selected
(DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not
necessary to clear this bit. Reset Value: 0x0 Dependencies: Writes
have no effect when FIFO_MODE == None.
RFR (RFR): RCVR FIFO Reset. This is a shadow register for the
RCVR FIFO Reset bit (FCR[1]). This can be used to remove the
burden on software having to store previously written FCR values
(which are pretty static) just to reset the receive FIFO This resets
0h the control portion of the receive FIFO and treats the FIFO as
1
RW empty. This also de-asserts the DMA RX request and single signals
when additional DMA handshaking signals are selected
(DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not
necessary to clear this bit. Reset Value: 0x0 Dependencies: Writes
have no effect when FIFO_MODE == None.
UR (UR): UART Reset. This asynchronously resets the
0h DW_apb_uart and synchronously removes the reset assertion. For
0
RW a two clock implementation both pclk and sclk domains are reset.
Reset Value: 0x0
Access Method
Default: 0h
0h
31:1 Reserved.
RO
Access Method
Default: 0h
0h
31:1 Reserved.
RO
0
0h sbcb (sbcb): Shadow Break Control Register
RW
Access Method
Default: 0h
0h
31:1 Reserved.
RO
Access Method
Default: 0h
0h
31:1 Reserved.
RO
sfe (sfe): Shadow FIFO Enable. This is a shadow register for the
FIFO enable bit (FCR[0]). This can be used to remove the burden of
having to store the previously written value to the FCR in memory
0h and having to mask this value so that only the FIFO enable bit gets
0
RW updated.This enables/disables the transmit (XMIT) and receive
(RCVR) FIFOs. If this bit is set to zero (disabled) after being
enabled then both the XMIT and RCVR controller portion of FIFOs
are reset. Reset Value: 0x0
Access Method
Default: 0h
0h
31:2 Reserved.
RO
srt (srt): Shadow RCVR Trigger. This is a shadow register for the
RCVR trigger bits (FCR[7:6]). This can be used to remove the
burden of having to store the previously written value to the FCR in
memory and having to mask this value so that only the RCVR
0h trigger bit gets updated. This is used to select the trigger level in
1:0
RW the receiver FIFO at which the Received Data Available Interrupt is
generated. It also determines when the dma_rx_req_n signal is
asserted when DMA Mode (FCR[3]) = 1. The following trigger levels
are supported: 00 = 1 character in the FIFO 01 = FIFO full 10 =
FIFO full 11 = FIFO 2 less than full Reset Value: 0x0
Access Method
Default: 0h
0h
31:2 Reserved.
RO
1:0
0h stet (stet): Shadow TX Empty Trigger
RW
Access Method
Default: 0h
0h
31:1 Reserved.
RO
Access Method
Default: 0h
0h
31:1 Reserved.
RO
Access Method
Default: 43F32h
0h
31:24 Reserved.
RO
13
1h DMA_EXTRA (DMA_EXTRA): 0 = FALSE, 1 = TRUE
RO
1h UART_ADD_ENCODED_PARAMS
12
RO (UART_ADD_ENCODED_PARAMS): 0 = FALSE, 1 = TRUE
11
1h SHADOW (SHADOW): 0 = FALSE, 1 = TRUE
RO
10
1h FIFO_STAT (FIFO_STAT): 0 = FALSE, 1 = TRUE
RO
9
1h FIFO_ACCESS (FIFO_ACCESS): 0 = FALSE, 1 = TRUE
RO
7
0h SIR_LP_MODE (SIR_LP_MODE): 0 = FALSE, 1 = TRUE
RO
6
0h SIR_MODE (SIR_MODE): 0 = FALSE, 1 = TRUE
RO
5
1h THRE_MODE (THRE_MODE): 0 = FALSE, 1 = TRUE
RO
4
1h AFCE_MODE (AFCE_MODE): 0 = FALSE, 1 = TRUE
RO
0h
3:2 Reserved.
RO
Access Method
Default: 3331342Ah
Access Method
Default: 44570110h
Access Method
Default: 0h
31:8
0h Reserved0: Reserved
RO
7:0
0h RID: Revision ID of the Bridge.
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Default: 608086h
15:0
8086h Vendor Identification (VID): Indicates Intel.
RO
Default: 7h
15:11
0h Reserved (RSVD): Reserved.
RO
7
0h Wait Cycle Control (WCC): Reserved as 0 per PCI-Express spec.
RO
3
0h Special Cycle Enable (SCE): Reserved as 0 per PCI-Express spec.
RO
2
1h Bus Master Enable (BME): Bus Masters cannot be disabled.
RO
0
1h I/O Space Enable (IOSE): I/O space cannot be disabled on LPC.
RO
Default: 200h
6
0h Reserved (RSVD): Reserved.
RO
2:0
0h Reserved (RSVD_1): Reserved.
RO
Default: 0h
Default: 60100h
0h
31:24 Reserved.
RO
23:16
6h Base Class Code (BCC): Indicates the device is a bridge device.
RO
15:8
1h Sub-Class Code (SCC): Indicates the device a PCI to ISA bridge.
RO
Default: 0h
7:3
0h Master Latency Count (MLC): Reserved per 3GIO spec.
RO
2:0
0h Reserved (RSVD): Reserved.
RO
Default: 80h
Access Method
Default: 0h
Default: 0h
Default: 10h
7
0h Enable (EN): When set, serial IRQs will be recognized.
RW
4h Frame Size (FS): Fixed field that indicates the size of the SERIRQ
5:2
RO frame as 21 frames.
Start Frame Pulse Width (SFPW): This is the number of 33 MHz clocks that the
SERIRQ pin will be driven low by the Serial IRQ controller to signal a start frame. In
continuous mode, the controller will drive the start frame for the number of clocks
specified. In quiet mode, the controller will drive the start frame for the number of
clocks specified minus one, as the first clock was driven by the peripheral. Bits Clocks
0h
1:0 • 00: 4
RW
• 01: 6
• 10: 8
• 11: Reserved
Default: 0h
15:13
0h Reserved (RSVD): Reserved.
RO
FDD Range (FDD): The following table describes which range to decode for the FDD
Port. Bits Decode Range
0h
12 • 0 3F0h - 3F5h, 3F7h (Primary)
RW
• 1 370h - 375h, 377h (Secondary)
11:10
0h Reserved (RSVD_1): Reserved.
RO
LPT Range (LPT): The following table describes which range to decode for the LPT
Port: Bits Decode Range
• 00 378h - 37Fh and 778h - 77Fh
0h
9:8 • 01 278h - 27Fh (port 279h is read only) and 678h - 67Fh
RW
• 10 3BCh - 3BEh and 7BCh - 7BEh
• 11 Reserved
7
0h Reserved (RSVD_2): Reserved.
RO
ComB Range (CB): The following table describes which range to decode for the COMB
Port. Bits Decode Range
• 000 3F8h - 3FFh (COM 1)
• 001 2F8h - 2FFh (COM 2)
• 010 220h - 227h
0h
6:4 • 011 228h - 22Fh
RW
• 100 238h - 23Fh
• 101 2E8h - 2EFh (COM 4)
• 110 338h - 33Fh
• 111 3E8h - 3EFh (COM 3)
3
0h Reserved (RSVD_3): Reserved.
RO
ComA Range (CA): The following table describes which range to decode for the COMA
Port. Bits Decode Range
• 000 3F8h - 3FFh (COM 1)
• 001 2F8h - 2FFh (COM 2)
• 010 220h - 227h
0h
2:0 • 011 228h - 22Fh
RW
• 100 238h - 23Fh
• 101 2E8h - 2EFh (COM 4)
• 110 338h - 33Fh
• 111 3E8h - 3EFh (COM 3)
Default: 0h
15:14
0h Reserved (RSVD): Reserved.
RO
7:4
0h Reserved (RSVD_1): Reserved
RO
Default: 0h
31:24
0h Reserved (RSVD): Reserved.
RO
17:16
0h Reserved (RSVD_1): Reserved.
RO
1
0h Reserved (RSVD_2): Reserved.
RO
Default: 0h
31:24
0h Reserved (RSVD): Reserved.
RO
17:16
0h Reserved (RSVD_1): Reserved.
RO
1
0h Reserved (RSVD_2): Reserved.
RO
Default: 0h
31:24
0h Reserved (RSVD): Reserved.
RO
17:16
0h Reserved (RSVD_1): Reserved.
RO
1
0h Reserved (RSVD_2): Reserved.
RO
Default: 0h
31:24
0h Reserved (RSVD): Reserved.
RO
17:16
0h Reserved (RSVD_1): Reserved.
RO
1
0h Reserved (RSVD_2): Reserved.
RO
Default: 0h
31:16
0h Reserved (RSVD): Reserved.
RO
14
0h Reserved (RSVD_1): Reserved.
RO
13
0h Reserved (RSVD_2): Reserved.
RW
12
0h Reserved (RSVD_3): Reserved.
RO
4
0h Reserved (RSVD_4): Reserved.
RW
Default: 0h
15:1
0h Reserved (RSVD): Reserved.
RO
Access Method
Default: 0h
31:0
0h Reserved (RSVD): Reserved.
RO
Access Method
Default: 112233h
0h F8-FF IDSEL (IF8): IDSEL to use in FWH cycle for range enabled
31:28
RO by BDE.EF8.
0h F0-F7 IDSEL (IF0): IDSEL to use in FWH cycle for range enabled
27:24
RW by BDE.EF0.
1h E8-EF IDSEL (IE8): IDSEL to use in FWH cycle for range enabled
23:20
RW by BDE.EE8.
1h E0-E7 IDSEL (IE0): IDSEL to use in FWH cycle for range enabled
19:16
RW by BDE.EE0.
2h D8-DF IDSEL (ID8): IDSEL to use in FWH cycle for range enabled
15:12
RW by BDE.ED8.
2h D0-D7 IDSEL (ID0): IDSEL to use in FWH cycle for range enabled
11:8
RW by BDE.ED0.
3h C8-CF IDSEL (IC8): IDSEL to use in FWH cycle for range enabled
7:4
RW by BDE.EC8.
3h C0-C7 IDSEL (IC0): IDSEL to use in FWH cycle for range enabled
3:0
RW by BDE.EC0.
Access Method
Default: 4567h
4h 70-7F IDSEL (I70): IDSEL to use in FWH cycle for range enabled
15:12
RW by BDE.E70.
5h 60-6F IDSEL (I60): IDSEL to use in FWH cycle for range enabled
11:8
RW by BDE.E60.
6h 50-5F IDSEL (I50): IDSEL to use in FWH cycle for range enabled
7:4
RW by BDE.E50.
7h 40-4F IDSEL (I40): IDSEL to use in FWH cycle for range enabled
3:0
RW by BDE.E40.
Access Method
Default: FFCFh
F8-FF Enable (EF8): Enables decoding of 512K of the following: BIOS range:
1h
15 • Data space: FFF80000h - FFFFFFFFh
RO
• Feature space: FFB80000h - FFBFFFFFh
F0-F8 Enable (EF0): Enables decoding of 512K of the following: BIOS range:
1h
14 • Data space: FFF00000h - FFF7FFFFh
RW
• Feature space: FFB00000h - FFB7FFFFh
E8-EF Enable (EE8): Enables decoding of 512K of the following: BIOS range:
1h
13 • Data space: FFE80000h - FFEFFFFFh
RW
• Feature space: FFA80000h - FFAFFFFFh
E0-E8 Enable (EE0): Enables decoding of 512K of the following: BIOS range:
1h
12 • Data space: FFE00000h - FFE7FFFFh
RW
• Feature Space: FFA00000h - FFA7FFFFh
D8-DF Enable (ED8): Enables decoding of 512K of the following: BIOS range:
1h
11 • Data space: FFD80000h - FFDFFFFFh
RW
• Feature space: FF980000h - FF9FFFFFh
D0-D7 Enable (ED0): Enables decoding of 512K of the following: BIOS range:
1h
10 • Data space: FFD00000h - FFD7FFFFh
RW
• Feature space: FF900000h - FF97FFFFh
C8-CF Enable (EC8): Enables decoding of 512K of the following: BIOS range:
1h
9 • Data space: FFC80000h - FFCFFFFFh
RW
• Feature space: FF880000h - FF8FFFFFh
C0-C7 Enable (EC0): Enables decoding of 512K of the following: BIOS range:
1h
8 • Data space: FFC00000h - FFC7FFFFh
RW
• Feature space: FF800000h - FF87FFFFh
Legacy F Segment Enable (LFE): This enables the decoding of
1h the legacy 64KB range at F0000h - FFFFFh. Note that decode for
7
RW the BIOS legacy F segment is enabled by the LFE bit only, it is not
affected by the GEN_PMCON_1.iA64_EN bit.
Legacy E Segment Enable (LEE): This enables the decoding of
1h the legacy 64KB range at E0000h - EFFFFh. Note that decode for
6
RW the BIOS legacy E segment is enabled by the LEE bit only, it is not
affected by the GEN_PMCON_1.iA64_EN bit.
5:4
0h Reserved (RSVD): Reserved.
RO
70-7F Enable (E70): Enables decoding of 1MB of the following: BIOS range:
1h
3 • Data space: FF700000h - FF7FFFFFh
RW
• Feature space: FF300000h - FF3FFFFFh
60-6F Enable (E60): Enables decoding of 1MB of the following: BIOS range:
1h
2 • Data space: FF600000h - FF6FFFFFh
RW
• Feature Space: FF200000h - FF2FFFFFh
50-5F Enable (E50): Enables decoding of 1MB of the following: BIOS range:
1h
1 • Data space: FF500000h - FF5FFFFFh
RW
• Feature space: FF100000h - FF1FFFFFh
40-4F Enable (E40): Enables decoding of 1MB of the following: BIOS range:
1h
0 • Data space: FF400000h - FF4FFFFFh
RW
• Feature space: FF000000h - FF0FFFFFh
Default: 20h
Enable InSMM.STS (EISS): When this bit is set, the BIOS region
is not writable until SMM sets the InSMM.STS bit. Today BIOS Flash
1h is writable if WPD is a 1. If this bit [5] is set, then WPD must be a 1
5
RW/L and InSMM.STS (0xFED3_0880[0]) must be 1 also. If this bit [5] is
clear, then BIOS is writable based only on WPD = 1 and the
InSMM.STS is a don't care.
Top Swap (TS): When set, PCH will invert either A16, A17, or A18 for cycles going to
the BIOS space (but not the feature space) in the FWH. When cleared, PCH will not
invert A16. If booting from LPC (FWH), then the Boot Block size is 64KB and A16 is
inverted if Top Swap is enabled. If booting from SPI, then the BOOT_BLOCK_SIZE soft
strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. *If PCH
is strapped for Top-Swap (GNT[3]# is low at rising edge of PWROK), then this bit
cannot be cleared by software. The strap jumper should be removed and the system
rebooted. BIOS Note:
0h
4 1. This bit provides a read-only path to view the state of the Top
RO
Swap strap. It is backed up and driven from the RTC well. Bios
will need to program the corresponding register in the RTC
Controller (in RTC well), which will be reflected in this register.
2. The Register portion of the Top Swap is lockable by the Bios
Interface Lockdown Bit (BC.BILD) but unlockable by SPI Flash
Protected Range and Top Swap Override (uCode.PRR_TS_OVR).
SPI Read Configuration (SRC): This 2-bit field controls two policies related to BIOS
reads on the SPI interface:
1. Bit 3: Prefetch Enable
2. Bit 2: Cache Disable
Settings are summarized below:
• Bits 3:2 Description
• 00: No prefetching, but caching enabled. Direct Memory reads
load the read buffer cache with valid data, allowing repeated
0h reads to the same range to complete quickly.
3:2
RW
• 01: No prefetching and no caching. One-to-one correspondence
of host BIOS reads to SPI cycles. This value can be used to
invalidate the cache.
• 10: Prefetching and Caching enabled. This mode is used for
long sequences of short reads to consecutive addresses (i.e.
shadowing)
• 11: Illegal. Caching must be enabled when Prefetching is
enabled. This eliminates the need for a complex prefetch-
flushing mechanism.
Lock Enable (LE): When set, setting the WP bit will cause SMI.
0h When cleared, setting the WP bit will not cause SMI. Once set, this
1
RW/1L bit can only be cleared by a PLTRST#. When this bit is set, EISS -
bit [5] of this register is locked down.
Write Protect Disable (WPD): When set, access to the BIOS
space is enabled for both read and write cycles to BIOS. When
0h cleared, only read cycles are permitted to the FWH or SPI flash.
0
RW When this bit is written from a 0 to a 1 and the LE bit is also set, an
SMI# is generated. This ensures that only SMM code can update
BIOS.
Default: 0h
31:10
0h Reserved (RSVD): Reserved.
RO
1
0h Reserved (RSVD_1): Reserved.
RW
Access Method
Default: F00h
31:28
0h Reserved (RSVD): Reserved.
RO
27:24
0h Dot portion of Process ID: (PD): Indicates the dot process
RO/V
15:8
Fh Manufacturing Identifier (MID): 0Fh = Intel
RO/V
§§
9 eSPI Registers
This chapter documents the registers in Bus: 0, Device 31, Function 0.
3197h Device Identification (DID): The default value of this is hardwired. The upper 8-bits
31:16 of this field can be overridden by the SetID IOSF-SB Message. Note:Refer to chapter 6s
RO/V global DevID table for details .
8086h
15:0 Vendor Identification (VID): Indicates Intel
RO
0h Detected Parity Error (DPE): Set when the bridge detects a parity error on the
31
RW/1C/V internal backbone. This bit gets set even if CMD.PERE is not set.
0h Signaled System Error (SSE): Set when the LPC bridge signals a system error to
30
RW/1C/V the internal SERR# logic.
0h Received Master Abort (RMA): Set when the bridge receives a completion with
29
RW/1C/V unsupported request status from the backbone.
0h Received Target Abort (RTA): Set when the bridge receives a completion with
28
RW/1C/V completer abort status from the backbone.
0h Signaled Target Abort (STA): Set when the bridge generates a completion packet
27
RW/1C/V with target abort status on the backbone.
0h DEVSEL# Timing Status (DTS): Indicates medium timing, although this has no
26:25
RO meaning on the backbone.
0h Data Parity Error Detected (DPD): Set when the bridge receives a completion
24 packet from the backbone from a previous request, and detects a parity error, and
RW/1C/V CMD.PERE is set.
0h Fast Back to Back Capable (FBC): Reserved - bit has no meaning on internal
23
RO backbone.
0h
22 Reserved (RSVD_1): Reserved
RO
0h
21 66 MHz Capable (C66): Reserved - bit has no meaning on internal backbone.
RO
0h
20 Capabilities List (CLIST): There is a capabilities list in the LPC bridge.
RO
0h
19 Interrupt Status (IS): The LPC bridge does not generate interrupts.
RO
0h
18:11 Reserved (RSVD): Reserved
RO
1h
10 Interrupt Disable (ID): The LPC bridge has no interrupts to disable
RO
0h
9 Fast Back to Back Enable (FBE): Reserved as 0 per PCI-Express spec.
RO
0h
8 SERR# Enable (SEE): The LPC bridge generates SERR# if this bit is set.
RW
0h
7 Wait Cycle Control (WCC): Reserved as 0 per PCI-Express spec.
RO
0h Parity Error Response Enable (PERE): When this bit is set to 1, it enables the LPC
6
RW bridge to response to parity errors detected on backbone interface.
0h
5 VGA Palette Snoop (VGA_PSE): Reserved as 0 per PCI-Express spec.
RO
0h
3 Special Cycle Enable (SCE): Reserved as 0 per PCI-Express spec.
RO
0h
2 Bus Master Enable (BME): Bus Masters cannot be disabled.
RW
1h
1 Memory Space Enable (MSE): Memory space cannot be disabled on LPC.
RO
1h
0 I/O Space Enable (IOSE): I/O space cannot be disabled on LPC.
RO
6h
31:24 Base Class Code (BCC): Indicates the device is a bridge device.
RO
1h
23:16 Sub-Class Code (SCC): Indicates the device a PCI to ISA bridge.
RO
0h
15:8 Programming Interface (PI): The LPC bridge has no programming interface.
RO
0h Revision ID (RID): Indicates the part revision This will reset to 0 but is expected to
7:0
RO/V be overridden by the SetID IOSF-SB message.
0h
31:24 Reserved (RSVD): Reserved
RO
1h Multi-function Device (MFD): This bit is 1 to indicate that this PCI function is part of
23
RO a multi-function device.
0h Header Type (HTYPE): Identifies the header layout of the configuration space, which
22:16
RO is a generic device.
0h
15:11 Master Latency Count (MLC): Reserved
RO
0h
10:0 Reserved (RSVD): Reserved
RO
0h Memory BAR (MEMBAR): Software programs this register with the base address of
31:12
RW the device's memory region
0h
11:4 Memory Size (MEMSIZE): Hard wired to 0 to indicate 4KB of memory space
RO
1h
3 PREFETCH: Set to '1' to indicate there are no side-effects on reads
RO
0h
2:1 TYP: Set to '00' to allow mapping anywhere in 32-bit address space
RO
0h
0 Memory Space Indicator (MEMSPACE): Set to 0 for Memory Space
RO
0h
31:8 Reserved (RSVD): Reserved
RO
0h
7:0 Capability Pointer (CP): Indicates the offset of the first Capability Item.
RO
0h
31:8 Reserved (RSVD): Reserved
RO
44h Capabilities Pointer (CAPP): Indicates the pointer for the first entry in the
7:0
RO capabilities list
0h
31:25 Reserved (RSVD): Reserved
RO
0h Per Vector Masking Capable (PVMC): This function does not support MSI per
24
RO vector masking
0h 64 bit address capable (XAC): This function is not capable of sending 64 bit
23
RO message address
0h MSI Enable (MSIE): If set (1) CXME MSI interrupt delivery is enabled. When this bit
16 is cleared, prior to returning the configuration write completion, the device must send
RW any pending MSI(s).
50h Next Item Pointer (NXTP): Indicates the pointer for the next entry in the
15:8
RO capabilities list. Hardwired to 50h to point to the PM Capability list.
5h Capability ID (CAPID): Hardwired to 05h to indicate the linked list item as being the
7:0
RO MSI Capability registers
0h
31:2 Message Address (MADDR): DW aligned MSI message address.
RW
0h
1:0 Reserved (RSVD): Reserved
RO
0h
31:16 Reserved (RSVD): Reserved
RO
0h
15:0 Message Data (MDAT): MSI Message Data
RW
PME Support (PMES): This 5-bit field indicates the power states in which the
function may assert PME#. A value of 0b for any bit indicates that the function is not
8h capable of asserting the PME# signal while in that power state. bit(11) X XXX1b -
31:27
RO PME# can be asserted from D0 bit(12) X XX1Xb - PME# can be asserted from D1
bit(13) X X1XXb - PME# can be asserted from D2 bit(14) X 1XXXb - PME# can be
asserted from D3hot bit(15) 1 XXXXb - PME# can be asserted from D3cold
0h
26 D2 Support (D2S): This device does not support D2
RO
0h
25 D1 Support (D1S): This device does not support D1
RO
0h
24:22 Aux Current (AUXC): Not Applicable
RO
0h
20 Reserved (RSVD): Reserved
RO
0h
19 PME Clock (PMECLK): Not Applicable
RO
3h VER: Value of 011b indicates that this function complies with rev 1.2 of PCI Power
18:16
RO Management Interface Spec
0h Next Item Pointer (NXTP): Indicates the pointer for the next entry in the
15:8
RO capabilities list. Hardwired to 0 to indicate no more linked list item.
1h Capability ID (CAPP): Hardwired to 01h to indicate the linked list item as being the
7:0
RO PCI Power Management registers
0h
31:24 DATA: Not implemented. Hardwired to 0.
RO
0h
23:16 Reserved (RSVD): Reserved
RO
PME Status (PMESTS): This bit is set when the function would normally assert the
0h PME signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear
15 it and cause the function to stop asserting a PME (if enabled). Writing a 0 has no effect.
RW/1C/V/P If the function supports PME from D3cold, then this bit is sticky and must be explicitly
cleared by the operating system each time the operating system is initially loaded
0h
14:13 Data Scale (DS): Not Applicable
RO
0h
12:9 Data Select (DSEL): Not Applicable
RO
PME Enable (PMEEN): A 1 enables the function to assert PME. When 0, PME
0h assertion is disabled. This bit defaults to 0 if the function does not support PME
8
RW generation from D3cold. If the function supports PME from D3cold then this bit is sticky
and must be explicitly cleared by the operating system each time it is initially loaded.
0h
7:4 Reserved (RSVD1): Reserved
RO
No Soft Reset (NSR): When set to 1, this bit indicates that devices transitioning from
1h D3hot to D0 because of PowerState commands do not perform an internal reset.
3 Configuration Context is preserved. Upon transition from the D3hot to the D0
RO Initialized state, no additional operating system intervention is required to preserve
Configuration Context beyond writing the PowerState bits.
0h
2 Reserved (RSVD2): Reserved
RO
Power State (PWRST): This 2-bit field is used both to determine the current power
state of a function and to set the function into a new power state. The definition of the
0h field values is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software
1:0
RW attempts to write an unsupported, optional state to this field, the write operation must
complete normally on the bus; however, the data is discarded and no state change
occurs.
0h
31:0 Reserved (RSVD): Reserved
RO
0h
31:30 Reserved (RSVD_5): Reserved
RO
0h Microcontroller Enable #2 (ME2): Enables decoding of I/O locations 4Eh and 4Fh
29
RW to LPC.
0h
28 SuperI/O Enable (SE): Enables decoding of I/O locations 2Eh and 2Fh to LPC.
RW
0h Microcontroller Enable #1 (ME1): Enables decoding of I/O locations 62h and 66h
27
RW to LPC.
0h
26 KE: Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
RW
0h High Gameport Enable (HGE): Enables decoding of the I/O locations 208h to 20Fh
25
RW to LPC.
0h Low Gameport Enable (LGE): Enables decoding of the I/O locations 200h to 207h to
24
RW LPC.
0h
23:20 Reserved (RSVD_4): Reserved
RO
0h Floppy Drive Enable (FDE): Enables decoding of the FDD range to LPC. Range is
19
RW selected by LIOD.FDE
0h Parallel Port Enable (PPE): Enables decoding of the LPT range to LPC. Range is
18
RW selected by LIOD.LPT.
0h Com Port B Enable (CBE): Enables decoding of the COMB range to LPC. Range is
17
RW selected LIOD.CB.
0h Com Port A Enable (CAE): Enables decoding of the COMA range to LPC. Range is
16
RW selected LIOD.CA.
0h
15:13 Reserved (RSVD_3): Reserved
RO
0h FDD: The following table describes which range to decode for the FDD Port Bits
12
RW Decode Range 0 3F0h - 3F5h, 3F7h (Primary) 1 370h - 375h, 377h (Secondary)
0h
11:10 Reserved (RSVD_2): Reserved
RO
0h LPT: The following table describes which range to decode for the LPT Port: Bits
9:8 Decode Range 00 378h - 37Fh and 778h - 77Fh 01 278h - 27Fh (port 279h is read
RW only) and 678h - 67Fh 10 3BCh - 3BEh and 7BCh - 7BEh 11 Reserved
0h
7 Reserved (RSVD_1): Reserved
RO
ComB Range (CB): The following table describes which range to decode for the
0h COMB Port Bits Decode Range 000 3F8h - 3FFh (COM 1) 001 2F8h - 2FFh (COM 2) 010
6:4
RW 220h - 227h 011 228h - 22Fh 100 238h - 23Fh 101 2E8h - 2EFh (COM 4) 110 338h -
33Fh 111 3E8h - 3EFh (COM 3)
0h
3 Reserved (RSVD): Reserved
RO
ComA Range (CA): The following table describes which range to decode for the
0h COMA Port Bits Decode Range 000 3F8h - 3FFh (COM 1) 001 2F8h - 2FFh (COM 2) 010
2:0
RW 220h - 227h 011 228h - 22Fh 100 238h - 23Fh 101 2E8h - 2EFh (COM 4) 110 338h -
33Fh 111 3E8h - 3EFh (COM 3)
0h
31:24 Reserved (RSVD): Reserved
RO
Address[7:2] Mask (ADDR_MASK): A 1 in any bit position indicates that any value
0h in the corresponding address bit in a received cycle will be treated as a match. The
23:18 corresponding bit in the Address field, below, is ignored. The mask is only provided for
RW the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in
size.
0h
17:16 Reserved (RSVD_1): Reserved
RO
0h ADDR: DWord-aligned address. Note that PCH does not provide decode down to the
15:2
RW word or byte level.
0h
1 Reserved (RSVD_2): Reserved
RO
0h LPC Decode Enable (LDE): When this bit is set to 1, then the range specified in this
0
RW register is enabled for decoding to LPC.
0h
31:24 Reserved (RSVD): Reserved
RO
Address[7:2] Mask (ADDR_MASK): A 1 in any bit position indicates that any value
0h in the corresponding address bit in a received cycle will be treated as a match. The
23:18 corresponding bit in the Address field, below, is ignored. The mask is only provided for
RW the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in
size.
0h
17:16 Reserved (RSVD_1): Reserved
RO
0h ADDR: DWord-aligned address. Note that PCH does not provide decode down to the
15:2
RW word or byte level.
0h
1 Reserved (RSVD_2): Reserved
RO
0h LPC Decode Enable (LDE): When this bit is set to 1, then the range specified in this
0
RW register is enabled for decoding to LPC.
0h
31:24 Reserved (RSVD): Reserved
RO
Address[7:2] Mask (ADDR_MASK): A 1 in any bit position indicates that any value
0h in the corresponding address bit in a received cycle will be treated as a match. The
23:18 corresponding bit in the Address field, below, is ignored. The mask is only provided for
RW the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in
size.
0h
17:16 Reserved (RSVD_1): Reserved
RO
0h ADDR: DWord-aligned address. Note that PCH does not provide decode down to the
15:2
RW word or byte level.
0h
1 Reserved (RSVD_2): Reserved
RO
0h LPC Decode Enable (LDE): When this bit is set to 1, then the range specified in this
0
RW register is enabled for decoding to LPC.
0h
31:24 Reserved (RSVD): Reserved
RO
Address[7:2] Mask (ADDR_MASK): A 1 in any bit position indicates that any value
0h in the corresponding address bit in a received cycle will be treated as a match. The
23:18 corresponding bit in the Address field, below, is ignored. The mask is only provided for
RW the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in
size.
0h
17:16 Reserved (RSVD_1): Reserved
RO
0h ADDR: DWord-aligned address. Note that PCH does not provide decode down to the
15:2
RW word or byte level.
0h
1 Reserved (RSVD_2): Reserved
RO
0h LPC Decode Enable (LDE): When this bit is set to 1, then the range specified in this
0
RW register is enabled for decoding to LPC.
0h
31:16 Reserved (RSVD): Reserved
RO
0h
14 Reserved (RSVD_1): Reserved
RO
1h
13 Reserved (RSVD_2): Reserved
RW
0h
12 Reserved (RSVD_3): Reserved
RO
SMI Caused by Port 64 Write (TRAPBY64W): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 3, then this bit will still be
11 active. It is up to the SMM code to use the enable bit to determine the exact cause of
RW/1C/V the SMI#. Writing a 1 to this bit will clear the latch. Note that the A20Gate Pass-
Through Logic allows specific port 64h Writes to complete without setting this bit.
SMI Caused by Port 64 Read (TRAPBY64R): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 2, then this bit will still be
10
RW/1C/V active. It is up to the SMM code to use the enable bit to determine the exact cause of
the SMI#. Writing a 1 to this bit will clear the latch.
SMI Caused by Port 60 Write (TRAPBY60W): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 1, then this bit will still be
9 active. It is up to the SMM code to use the enable bit to determine the exact cause of
RW/1C/V the SMI#. Writing a 1 to this bit will clear the latch. Note that the A20Gate Pass-
Through Logic allows specific port 60h Writes to complete without setting this bit.
SMI Caused by Port 60 Read (TRAPBY60R): Indicates if the event occurred. Note
0h that even if the corresponding enable bit is not set in the Bit 0, then this bit will still be
8
RW/1C/V active. It is up to the SMM code to use the enable bit to determine the exact cause of
the SMI#. Writing a 1 to this bit will clear the latch.
0h Pass Through State (PSTATE): This read-only bit indicates that the state machine
6 is in the middle of an A20GATE pass-through sequence. If software needs to reset this
RO/V bit, it should set Bit 5 0.
1h
4 Reserved (RSVD_4): Reserved
RW
0h SMI on Port 64 Writes Enable (S64WEN): When set, a 1 in bit 11 will cause an
3
RW SMI event.
0h
SMI on Port 64 Reads Enable (S64REN): When set, a 1 in bit 10 will cause an SMI
2
event.
RW
0h SMI on Port 60 Writes Enable (S60WEN): When set, a 1 in bit 9 will cause an SMI
1
RW event.
0h SMI on Port 60 Reads Enable (S60REN): When set, a 1 in bit 8 will cause an SMI
0
RW event.
0h
15:1 Reserved (RSVD): Reserved
RO
0h LPC Memory Range Decode Enable (LGMRD_EN): When this bit is set to 1, then
0
RW the range specified in this register is enabled for decoding to LPC.
0h
31:15 Reserved (RSVD_1): Reserved
RO
0h Debug Port CS1# Routing Enable (DPRE): Enables routing of I/O locations 80h,
14
RO 84h-86h, 88h, 8Ch-8Eh, 90h, 94h-96h, 98h, 9Ch-9Eh to eSPI CS1#.
0h SuperI/O CS1# Routing Enable (SRE): Enables routing of I/O locations 2Eh and
12
RO 2Fh to eSPI CS1#.
0h Keyboard CS1# Routing Enable (KRE): Enables routing of the keyboard I/O
10
RO locations 60h and 64h to eSPI CS1#.
0h High Gameport CS1# Routing Enable (HGRE): Enables routing of the I/O locations
9
RO 208h to 20Fh to eSPI CS1#.
0h Low Gameport CS1# Routing Enable (LGRE): Enables routing of the I/O locations
8
RO 200h to 207h to eSPI CS1#.
0h
7:4 Reserved (RSVD_2): Reserved
RO
0h Floppy Drive CS1# Routing Enable (FDRE): Enables routing of the FDD range to
3
RO eSPI CS1#. Range is selected by LIOD.FDE
0h Parallel Port CS1# Routing Enable (PPRE): Enables routing of the LPT range to
2
RO eSPI CS1#. Range is selected by LIOD.LPT.
0h Com Port B CS1# Routing Enable (CBRE): Enables routing of the COMB range to
1
RO eSPI CS1#. Range is selected by LIOD.CB.
0h Com Port A CS1# Routing Enable (CARE): Enables routing of the COMA range to
0
RO eSPI CS1#. Range is selected by LIOD.CA.
0h
31:24 Reserved (RSVD): Reserved
RO
Address[7:2] Mask (ADDR_MASK): A 1 in any bit position indicates that any value
0h in the corresponding address bit in a received cycle will be treated as a match. The
23:18 corresponding bit in the Address field, below, is ignored. The mask is only provided for
RW the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in
size.
0h
17:16 Reserved (RSVD_1): Reserved
RO
0h ADDR: DWord-aligned address. Note that PCH does not provide decode down to the
15:2
RW word or byte level.
0h
1 Reserved (RSVD_2): Reserved
RO
0h LPC Decode Enable (LDE): When this bit is set to 1, then the range specified in this
0
RW register is enabled for decoding to LPC.
0h
15:1 Reserved (RSVD): Reserved
RO
0h LPC Memory Range Decode Enable (LGMRD_EN): When this bit is set to 1, then
0
RW the range specified in this register is enabled for decoding to LPC.
0h
31:0 Reserved (RSVD): Reserved
RO
0h
31:0 Reserved (RSVD): Reserved
RO
0h
31:16 Reserved (RSVD_1): Reserved
RO
1h F8-FF Enable (EF8): Enables decoding of 512K of the following BIOS range: Data
15
RO space: FFF80000h - FFFFFFFFh Feature space: FFB80000h - FFBFFFFFh
1h F0-F8 Enable (EF0): Enables decoding of 512K of the following BIOS range: Data
14
RW space: FFF00000h - FFF7FFFFh Feature space: FFB00000h - FFB7FFFFh
1h E8-EF Enable (EE8): Enables decoding of 512K of the following BIOS range: Data
13
RW space: FFE80000h - FFEFFFFFh Feature space: FFA80000h - FFAFFFFFh
1h E0-E8 Enable (EE0): Enables decoding of 512K of the following BIOS range: Data
12
RW space: FFE00000h - FFE7FFFFh Feature Space: FFA00000h - FFA7FFFFh
1h D8-DF Enable (ED8): Enables decoding of 512K of the following BIOS range: Data
11
RW space: FFD80000h - FFDFFFFFh Feature space: FF980000h - FF9FFFFFh
1h D0-D7 Enable (ED0): Enables decoding of 512K of the following BIOS range: Data
10
RW space: FFD00000h - FFD7FFFFh Feature space: FF900000h - FF97FFFFh
1h C8-CF Enable (EC8): Enables decoding of 512K of the following BIOS range: Data
9
RW space: FFC80000h - FFCFFFFFh Feature space: FF880000h - FF8FFFFFh
1h C0-C7 Enable (EC0): Enables decoding of 512K of the following BIOS range: Data
8
RW space: FFC00000h - FFC7FFFFh Feature space: FF800000h - FF87FFFFh
1h Legacy F Segment Enable (LFE): This enables the decoding of the legacy 64KB
7 range at F0000h - FFFFFh Note that decode for the BIOS legacy F segment is enabled
RW by the LFE bit only, it is not affected by the GEN_PMCON_1.iA64_EN bit.
1h Legacy E Segment Enable (LEE): This enables the decoding of the legacy 64KB
6 RW range at E0000h - EFFFFh Note that decode for the BIOS legacy E segment is enabled
by the LEE bit only, it is not affected by the GEN_PMCON_1.iA64_EN bit.
0h
5:4 Reserved (RSVD): Reserved
RO
1h 70-7F Enable (E70): Enables decoding of 1MB of the following BIOS range: Data
3
RW space: FF700000h - FF7FFFFFh Feature space: FF300000h - FF3FFFFFh
1h 60-6F Enable (E60): Enables decoding of 1MB of the following BIOS range: Data
2
RW space: FF600000h - FF6FFFFFh Feature Space: FF200000h - FF2FFFFFh
1h 50-5F Enable (E50): Enables decoding of 1MB of the following BIOS range: Data
1
RW space: FF500000h - FF5FFFFFh Feature space: FF100000h - FF1FFFFFh
1h 40-4F Enable (E40): Enables decoding of 1MB of the following BIOS range: Data
0
RW space: FF400000h - FF4FFFFFh Feature space: FF000000h - FF0FFFFFh
0h
31:12 Reserved (RSVD_1): Reserved
RO
BIOS Write Status (BWRS): HW sets this bit if a memory write access is detected to
a protected BIOS range. 1'b0: Memory write to BIOS region not attempted or
0h attempted with PCBC.WPD = 1. 1'b1: A memory write transaction to BIOS region has
10
RW/1C/V been received with PCBC.WPD = 0. Note: An Async-SMI message is generated to
report this event if PCBC.BWRE is set. Note: SW must write a 1 to this bit to clear it,
which will also deassert the Async-SMI, if PCBC.BWRE is set.
0h
9 Reserved (RSVD_2): Reserved
RO
BIOS Write Protect Disable Status (BWPDS): HW sets this bit if configuration
write access is detected to protected PCBC.WPD bit. 1'b0: No attempt has been made
to set PCBC.WPD with PCBC.LE = 1. 1'b1: A configuration write request has been
0h received to set PCBC.WPD (0 1) with PCBC.LE = 1. Note: An IOSF-SB Sync-SMI
8 (Assert_SSMI) message is generated to report this event if HW sets this bit. The
RW/1C/V unsuccessful completion for the configuration write is returned upon receiving the
SMI_Ack message response. Note: SW must write a 1 to this bit to clear it, which will
also deassert the Sync-SMI (IOSF-SB Deassert_SSMI message is generated). Note:
The Sync-SMI sets the PMC SMI_STS.TCO_STS register.
BIOS Interface Lock-Down (BILD): When set, prevents BC.TS and BC.BBS from
0h being changed. This bit can only be written from 0 to 1 once. BIOS Note: This bit is not
7
RW/L backed up in the RTC well. This bit should also be set in the BUC register in the RTC
device to record the last state of this value following a cold reset.
Boot BIOS Strap (BBS): This field determines the destination of accesses to the
0h BIOS memory range. Bits Description 0 SPI 1 LPC When SPI or LPC is selected, the
6 range that is decoded is further qualified by other configuration bits. The value in this
RW/V/L field can be overwritten by software as long as the BIOS Interface Lock-Down is not
set.
Enable InSMM.STS (EISS): When this bit is set, the BIOS region is not writable until
1h SMM sets the InSMM.STS bit. Today BIOS Flash is writable if WPD is a 1. If this bit (5)
5 is set, then WPD must be a 1 and InSMM.STS (0xFED3_0880(0)) must be 1 also. If this
RW/L bit (5) is clear, then BIOS is writable based only on WPD = 1 and the InSMM.STS is a
dont care.
Top Swap (TS): When set, PCH will invert either A16, A17, or A18 for cycles going to
the BIOS space (but not the Feature space) in the FWH. When cleared, PCH will not
invert A16. If booting from LPC (FWH) or eSPI, then the Boot Block Size is fixed at
64KB and A16 is inverted if Top Swap is enabled. If booting from SPI, then the
0h BOOT_BLOCK_SIZE soft strap determines if A16, A17, or A18 should be inverted if Top
4
RO/V Swap is enabled. Note: If the Top-Swap strap is asserted, then this bit cannot be
cleared by software. The strap jumper should be removed and the system rebooted.
BIOS Note: This bit provides a read-only path to view the state of the Top Swap strap.
It is backed up and driven from the RTC well. BIOS will need to program the
corresponding register in the RTC well, which will be reflected in this register.
0h
3 Reserved (RSVD): Reserved
RO
ESPI: eSPI Enable Pin Strap (ESPI): This field determines the destination of accesses
to the D31:F0 and related Fixed and Variable IO and Memory decode ranges, including
0h BIOS memory range. 1'b0: LPC is the D31:F0 target. 1'b1: eSPI is the D31:F0 target.
2 Note: This field, along with the PCBC.BBS strap setting, determines PCH configuration
RO/V as specified in Table 11. Note: This field cannot be overwritten by software (unlike the
PCBC.BBS field). Note: This bit is also reflected in the LPC (D31:F0) and SPI Flash
(D31:F5) PCI Configuration register Offset DCh.
0h Lock Enable (LE): When set, setting the WP bit will cause SMI. When cleared, setting
1 the WP bit will not cause SMI. Once set, this bit can only be cleared by a PLTRST#.
RW/L When this bit is set, EISS - bit (5) of this register is locked down.
Write Protect Disable (WPD): When set, access to the BIOS space is enabled for
0h both read and write cycles to BIOS. When cleared, only read cycles are permitted to
0
RW the FWH or SPI flash. When this bit is written from a 0 to a 1 and the LE bit is also set,
an SMI# is generated. This ensures that only SMM code can update BIOS.
0h
31:28 Reserved (RSVD_1): Reserved
RO
0h
27:24 Dot portion of Process ID: (PD): Indicates the dot process
RO/V
Fh
15:8 Manufacturing Identifier (MID): 0Fh = Intel
RO/V
0h Process portion of process ID (PID): Indicates the process. The dot portion of the
7:0
RO/V process is reflected in bits (27:24)
10 PMC Registers
This chapter documents the registers in Bus: 0, Device 13, Function 1.
0h
31:30 Reserved Field (RESERVED0): Reserved
RO
0h
29 STATUSCOMMAND- RMA Field (RMA): Received Master Abort
RW/1C/V
0h
28 STATUSCOMMAND- RTA Field (RTA): Received Target Abort
RW/1C/V
0h
27:21 Reserved Field (RESERVED1): Reserved
RO
1h STATUSCOMMAND- Cap List Field (CAPLIST): Capabilities List: Indicates that the
20
RO controller contains a capabilities pointer list
0h
18:16 Reserved Field (RESERVED2): Reserved
RO
0h
15:11 Reserved Field (RESERVED3): Reserved
RO
0h
9 Reserved Field (RESERVED4): Reserved
RO
0h
7:3 Reserved Field (RESERVED5): Reserved
RO
0h
2 STATUSCOMMAND- BME Field (BME): Bus Master Enable
RW
0h
1 STATUSCOMMAND- MSE Field (MSE): Memory Space Enable
RW
FF0000h REVCLASSCODE - Class code Field (CLASS_CODES): Class Code register is read-
31:8 only and is used to identify the generic function of the device and in some cases a
RO/V specific register-level programming interface
0h
31:24 Reserved Field (RESERVED0): Reserved
RO
0h
7:0 CLLATHEADERBIST - Cache Line Size Field (CACHELINE_SIZE): Cacheline Size
RW
0h BAR -Base Address Field (BASEADDR): Base Address Register Low Base address
31:12
RW of the OCP fabric memory space. Taken from Strap values as ones
0h BAR -Size Field (SIZEINDICATOR): Size Indicator RO Always returns 0 The size of
11:4
RO this register depends on the size of the memory space
0h BAR -Type Field (TYPE): If BAR_64b_EN is 0 then 00 indicates BAR lies in 32bit
2:1
RO address range If BAR_64b_EN is 1 then 10 Indicates BAR lies in 64 bit address range
0h
31:0 BAR -Base Address High Field (BASEADDR_HIGH): Base Address high - MSB
RW
0h BAR1 - Base Address Field (BASEADDR1): Base Address1 This field is present if
31:12
RW BAR1 is enabled through private configuration space.
0h
11:4 BAR1 -Size Field (SIZEINDICATOR1): Always is 0 as minimum size is 4K
RO
0h BAR1 -Type Field (TYPE1): If BAR_64b_EN is 0 then 00 indicates BAR lies in 32bit
2:1
RO address range If BAR_64b_EN is 1 then 10 Indicates BAR lies in 64 bit address range
0h
31:2 BASEADDR:
RW
0h
1 RESERVED0: Reserved
RO
0h
0 MESSAGE_SPACE:
RO
0h SUBSYSTEMID: Subsystem ID: This register is implemented for any function that can
31:16
RW/O be instantiated more than once in a given system.
0h
31:8 Reserved Field (RESERVED0): Reserved
RO
0h
15:12 Reserved Field (RESERVED0): Reserved
RO
9h POWERCAPID - PME Support Field (PMESUPPORT): This 5-bit field indicates the
31:27
RO power states in which the function can assert the PME#
0h
26:19 Reserved Field (RESERVED0): Reserved
RO
0h POWERCAPID - Next Cap Field (NXTCAP): Next Capability: Points to the next
15:8
RO capability structure.
0h
31:16 Reserved Field (RESERVED0): Reserved
RO
0h
15 PMECTRLSTATUS - PME Status Field (PMESTATUS): PME Status
RW/1C/V
0h
14:9 Reserved Field (RESERVED1): Reserved
RO
0h
8 PMECTRLSTATUS - PME Enable Field (PMEENABLE): PME Enable
RW
0h
7:4 Reserved Field (RESERVED2): Reserved
RO
0h
2 Reserved Field (RESERVED3): Reserved
RO
0h
15:8 PCIDEVIDLE_CAP_REG - Next Capability Field (NEXT_CAP): Next Capability
RO
9h
7:0 PCIDEVIDLE_CAP_REG - Capability ID Field (CAPID): Capability ID
RO
10h DEVID VENDOR SPECIFIC REG - Vendor Specific Length Field (VSECID):
15:0
RO Vendor Specific Extended Capability ID
0h
31:22 Reserved Field (RESERVED0): Reserved
RO
0h
20 Reserved Field (RESERVED1): Reserved
RO
0h
15:13 Reserved Field (RESERVED2): Reserved
RO
4000F1Ch Manufacturers ID - MAN ID (MANID): Manufacturer ID: Default value comes from
31:0
RO/V straps.
10.27 THREAD_STATUS
(P_CR_GT_THREAD_STATUS_0_2_0_GTTMMADR)—Offset
805Ch
Per thread status register THIS REGISTER IS DUPLICATED IN THE PCU IO SPACE, XML
CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 7FF07h
29:19
0h RESERVED_2 (RESERVED_2): reserved
RO
7
0h RESERVED_1 (RESERVED_1): Reserved.
RO
3
0h RESERVED_0 (RESERVED_0): Reserved.
RO
10.28 CORE_STATUS
(P_CR_GT_CORE_STATUS_0_2_0_GTTMMADR)—Offset
8060h
Per core (including GT) status register.
Used by Ucode/GT and P-Unit/PMA HW to communicate core status to Pcode. THIS
REGISTER IS DUPLICATED IN THE PCU IO SPACE, XML CHANGES MUST BE MADE IN
BOTH PLACES
Access Method
Default: 1100FF07h
29
0h RESERVED_3 (RESERVED_3): Reserved
RO
25
0h S1_ACK (S1_ACK): Reserved.
RO/V
22:16
0h RESERVED_2 (RESERVED_2): Reserved
RO
7
0h RESERVED_1 (RESERVED_1): Reserved.
RO
3
0h RESERVED_0 (RESERVED_0): Reserved.
RO
10.29 GT_SLICE_INFO
(P_CR_GT_SLICE_INFO_0_2_0_GTTMMADR)—Offset
8064h
Status register describing GT slice state.
Access Method
Default: 0h
0h
31:11 Reserved.
RO
Access Method
Default: 0h
31:24
0h Reserved3 (RSVD3): This field is reserved for future use
RW
23:16
0h Reserved2 (RSVD2): This field is reserved for future use
RW
15:8
0h Reserved1 (RSVD1): This field is reserved for future use
RW
10.31 GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR
(P_CR_GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR)—
Offset 8070h
GT memory bound counter. Holds the accumulated number of CS clks that GT has been
waiting for memory grants.
Access Method
Default: 0h
10.32 GT_SQ_OCCUPANCY_0_2_0_GTTMMADR
(P_CR_GT_SQ_OCCUPANCY_0_2_0_GTTMMADR)—Offset
8074h
Accumulated GT super queue (SQ) occupancy. This is accumulated by GT and pushed
to P-Unit from the GT PMA.
Access Method
Default: 0h
31:0
0h DATA (DATA): Accumulated SQ occupancy.
RO/V
10.33 GT_RW_DRAM_0_2_0_GTTMMADR
(P_CR_GT_RW_DRAM_0_2_0_GTTMMADR)—Offset 8078h
This register contains the the sum of the cycles GT has read or written DRAM. It
contains a 32-bit accumulation of data sent via the Pushbus. Values exceeding 32 bits
will wrap around.
Access Method
Default: 0h
31:0
0h DATA (DATA): RW GT cycles to DRAM
RO/V
10.34 GT_P_REQ
(P_CR_GT_THREAD_P_REQ_0_2_0_GTTMMADR)—Offset
807Ch
GT Pstate request. This register is written by driver/GT with the desired P-State
request. THIS REGISTER IS DUPLICATED IN THE PCU IO SPACE, XML CHANGES MUST
BE MADE IN BOTH PLACES
Access Method
Default: 0h
13:4
0h RESERVED_1 (RESERVED_1): Reserved
RO
10.35 GT_ARAT_TTT
(P_CR_GT_ARAT_TTT_0_2_0_GTTMMADR)—Offset 8080h
Always Running APIC Timer 'Timer Target Time' (TTT) value. This is an absolute desired
wakeup time. GT copies the local TTT to the P-Unit on RC6 entry. Pcode will wake GT
via IO_PCODE_WAKEUP_REQUEST, such that the wake is finished when the URT
reaches the value in this register.
To account for wake delay, Pcode will also take into account the prewake value that can
be written via driver into GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR.
If ARAT is invalid, GT will write all 1's (infinity).
GT writes this register via the MMIO alias GT_ARAT_TTT_0_2_0_GTTMMADR THIS
REGISTER IS DUPLICATED IN THE PCU IO SPACE, XML CHANGES MUST BE MADE IN
BOTH PLACES
Access Method
Default: 1FFFFFFFFFFFFFFFh
63:61
0h RESERVED_0 (RESERVED_0): Reserved
RO
1FFFFFFFFFF DATA (DATA): The 61 bits of the TTT. GT will update this field with
60:0 FFFFFh
TTT value before entering RC6.
RW
10.36 GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR
(P_CR_GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR)—
Offset 8088h
This register is used in conjuction with GT_ARAT_TTT. It contains the enable and value
for a prewake offset that the GT driver can program to prewake GT from C6 with
reference to its TTT.
Access Method
Default: 0h
31:16
0h RESERVED_0 (RESERVED_0): Reserved
RO
10.37 GT_DISP_PWRON_0_2_0_GTTMMADR
(P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR)—Offset
8090h
Used by GT driver to control aspects of PHY power-on (MIPIO, eDP, DDI).
Access Method
Default: 0h
31:4
0h RESERVED_0 (RESERVED_0): reserved
RO
10.38 GT_GFX_RC6_0_2_0_GTTMMADR
(P_CR_GT_GFX_RC6_0_2_0_GTTMMADR)—Offset 8108h
Wrapping counter containing the total GT RC6 residency time since boot.
Access Method
Default: 0h
10.39 GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMM
ADR)—Offset 8124h
Control and Status register for the GFXDRIVERtoPCODE mailbox. This mailbox is
implemented as a means for the GT Driver running on the IA cores to tune parameters
for specific GFX workloads. This register is used in conjunction with
GTDRIVER_MAILBOX_DATA_{HIGH and LOW}. THIS REGISTER IS DUPLICATED IN THE
PCU IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
10.40 GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMM
ADR)—Offset 8128h
Data register for lower 32b of data for the GTDRIVERtoPCODE mailbox. This mailbox is
implemented as a means for the GTDriver running on the IA cores to tune parameters
for specific GFX workloads. This register is used in conjunction with
GTDRIVER_MAILBOX_INTERFACE. THIS REGISTER IS DUPLICATED IN THE PCU IO
SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
0h DATA (DATA): This field contains the lower 32b of data associated
31:0
RW/V with specific commands.
10.41 GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMM
ADR)—Offset 812Ch
Data register for upper 32b of data for the GFXDRIVERtoPCODE mailbox. This mailbox
is implemented as a means for the GT Driver running on the IA cores to tune
parameters for specific GFX workloads. This register is used in conjunction with
GTDRIVER_MAILBOX_INTERFACE. THIS REGISTER IS DUPLICATED IN THE PCU IO
SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
0h DATA (DATA): This field contains the upper 32b of data associated
31:0
RW/V with specific commands.
10.42 P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTM
MADR)—Offset 8130h
Control and status register for the P24CtoPCODE mailbox. This mailbox is implemented
as a way for the GT P24C to contact the P-unit and is accessible via MMIO. This register
is used in conjunction with P24C_PCODE_MAILBOX_DATA. THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
10.43 P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR
)—Offset 8134h
Data register for the P24CtoPCODE mailbox. This register is used in conjunction with
P24C_PCODE_MAILBOX_INTERFACE THIS REGISTER IS DUPLICATED IN THE PCU IO
SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
0h DATA (DATA): This field contains the data associated with specific
31:0
RW/V commands.
10.44 PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTM
MADR)—Offset 8138h
Control and status register for the PCODEtoP24C mailbox. This mailbox is implemented
as a way for pcode to sendi commands to the P24C GT microcontroller. This register is
used in conjunction with PCODE_P24C_MAILBOX_DATA. THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
10.45 PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR
)—Offset 813Ch
Data register for the PCODEtoP24C mailbox. This register is used in conjunction with
PCODE_P24C_MAILBOX_INTERFACE. This register is duplicated in the PCU IO space,
XML changes must be made in both places
Access Method
Default: 0h
0h DATA (DATA): This field contains the data associated with specific
31:0
RW/V commands.
10.46 GT_PM_CONFIG_0_2_0_GTTMMADR
(P_CR_GT_PM_CONFIG_0_2_0_GTTMMADR)—Offset
8140h
Interface for GT driver to configure power management.
Access Method
Default: 0h
31:1
0h RESERVED_0 (RESERVED_0): Reserved
RO
Access Method
Default: 0h
0h
31:16 Reserved.
RO
VALID (VALID): This field qualifies the validity of the Value field in
0h
15 this register. If the valid bit is zero, then it is assumed that software
RW
has no constraints on wake latency (i.e., it supports infinity).
0h
14:13 Reserved.
RO
10.48 GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR)—
Offset 8160h
This extended capability allows PCODE to send an interrupt notification upon
completion of a mailbox command received from the GTDRIVER. It is enabled via the
GTDriver Mailbox. PCODE will set the appropriate bit in this register to 1 and will then
write to 0.2.0.GTTMMADR.PIM[PCU_MBOXE]. The GFX Driver will clear the appropriate
bit in this register by writing a 1 to the bit. THIS REGISTER IS DUPLICATED IN THE PCU
IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
0h
31:8 Reserved.
RO
7
0h EVENT7 (EVENT7): Placeholder for Event
RW/1C/V
6
0h EVENT6 (EVENT6): Placeholder for Event
RW/1C/V
5
0h EVENT5 (EVENT5): Placeholder for Event
RW/1C/V
4
0h EVENT4 (EVENT4): Placeholder for Event
RW/1C/V
3
0h EVENT3 (EVENT3): Placeholder for Event
RW/1C/V
2
0h EVENT2 (EVENT2): Placeholder for Event
RW/1C/V
1
0h EVENT1 (EVENT1): Placeholder for Event
RW/1C/V
10.49 GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR)—
Offset 8164h
This extended capability allows the GTDriver to send a request to PCODE. The GTDriver
will set the appropriate bit in this register to 1 when it wants to generate an event to
PCODE. This will pend a Fast Path event to pcode. PCODE will clear the appropriate bit
in this register after servicing the request. THIS REGISTER IS DUPLICATED IN THE PCU
IO SPACE, XML CHANGES MUST BE MADE IN BOTH PLACES
Access Method
Default: 0h
0h
31:8 Reserved.
RO
7
0h EVENT7 (EVENT7): Placeholder for Event
RW/1S/V
6
0h EVENT6 (EVENT6): Placeholder for Event
RW/1S/V
5
0h EVENT5 (EVENT5): Placeholder for Event
RW/1S/V
4
0h EVENT4 (EVENT4): Placeholder for Event
RW/1S/V
3
0h EVENT3 (EVENT3): Placeholder for Event
RW/1S/V
2
0h EVENT2 (EVENT2): Placeholder for Event
RW/1S/V
1
0h EVENT1 (EVENT1): Placeholder for Event
RW/1S/V
0
0h EVENT0 (EVENT0): Placeholder for Event
RW/1S/V
10.50 CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_2_0_GTTMM
ADR)—Offset 816Ch
PUNIT_MMIO: Core Frequency Capabilities
This register describes the frequency capabilities of the IA cores. Units are 100MHz
multiplied by the ratio.
Minimum and maximum ratio fields are initialized by pCode at reset. Last resolved ratio
is updated upon changes to the processing system frequency. The efficient ratio is
determined by firmware and may be updated dynamically depending on firmware
support.
Access Method
Default: 0h
MAX_SUPPORTED_FREQ (MAX_SUPPORTED_FREQ):
0h
23:16 Maximum ratio for the IA cores. Units are 100MHz multiplied by the
RO/V
ratio.
EFFICIENT_FREQ (EFFICIENT_FREQ): Firmware-calculated
0h
15:8 efficient ratio for the IA cores. Units are 100MHz multiplied by the
RO/V
ratio.
MIN_SUPPORTED_FREQ (MIN_SUPPORTED_FREQ): Minimum
0h
7:0 supported ratio for the IA cores. Units are 100MHz multiplied by the
RO/V
ratio.
10.51 GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_2_0_GT
TMMADR)—Offset 8170h
PUNIT_MMIO: Graphics Engine Frequency Capabilities
This register describes the frequency capabilities of the integrated graphics engine.
Units are 16.67MHz multiplied by the ratio.
Minimum and maximum ratio fields are initialized by pCode at reset. Last resolved ratio
is updated upon changes to the integrated graphics engine frequency. The efficient
ratio is determined by firmware and may be updated dynamically depending on
firmware support.
Access Method
Default: 0h
10.52 SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_2
_0_GTTMMADR)—Offset 8174h
PUNIT_MMIO: System Agent Frequency Capabilities
This register describes the frequency capabilities of the System Agent. Units are
16.666MHz multiplied by the ratio.
Last resolved ratio is updated upon changes to the System Agent frequency.
Access Method
Default: 0h
23:16
0h MAX_RATIO (MAX_RATIO): max ratio
RO/V
15:8
0h RESERVED_1 (RESERVED_1): Reserved
RO/V
7:0
0h MIN_RATIO (MIN_RATIO): min ratio
RO/V
Access Method
Default: 0h
23:16
0h RESERVED_2 (RESERVED_2): Reserved
RO/V
15:8
0h RESERVED_1 (RESERVED_1): Reserved
RO/V
7:0
0h RESERVED_0 (RESERVED_0): Reserved
RO/V
10.54 GT_PERF_LIMIT_REASONS
(P_CR_GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR)—
Offset 8184h
This register reports reasons for performance limitations on the integrated graphics
engine. Status bits are an instantaneous indication of an active constraint. Log bits
indicate that a constraint was enforced since the log bit was last cleared.
Access Method
Default: 0h
11
0h SPARE11_STATUS (SPARE11_STATUS): Spare status bit.
RO/V
0h VR_THERMALERT_STATUS (VR_THERMALERT_STATUS):
10
RO/V Frequency is limited due to a voltage regulator thermal excursion.
9
0h SPARE9_STATUS (SPARE9_STATUS): Spare status bit.
RO/V
8
0h SPARE8_STATUS (SPARE8_STATUS): Spare status bit.
RO/V
7
0h SPARE7_STATUS (SPARE7_STATUS): Spare status bit.
RO/V
6
0h SPARE6_STATUS (SPARE6_STATUS): Spare status bit.
RO/V
5
0h SPARE5_STATUS (SPARE5_STATUS): Spare status bit.
RO/V
4
0h SPARE4_STATUS (SPARE4_STATUS): Spare status bit.
RO/V
10.55 GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR
(P_CR_GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR)—
Offset 8190h
PUNIT_MMIO: GTDRIVER_HWP_REQUEST
This register allows the graphics driver to dictate the minimum and maximum
performance of the IA cores. The driver may also change the behavior of any
autonomous IA P-state controller, if supported by firmware. Non-zero values override
default firmware behavior.
Access Method
Default: 0h
63:42
0h RESERVED_0 (RESERVED_0): Reserved
RW
10.56 GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR
(P_CR_GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR)—
Offset 819Ch
GT video busy counter. Holds the accumulated number of CS clks that GT video
functions have been busy.
Access Method
Default: 0h
Access Method
Default: 0h
31:8
0h Reserved Field (Reserved0): Reserved
RO
7:0
0h RID - Bridge revision ID Field (RID): Revision ID of the Bridge.
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
31
0h Reserved (reserved4): Reserved.
RO
28:27
0h Reserved (reserved5): Reserved.
RO
RTC Alarm Enable (rtc_en): This is the RTC alarm enable bit. It
works in conjunction with the SCI_EN bit:
RTC_EN | SCI_EN | Effect when RTC_STS is set
0 | x | No SMI# or SCI. If system was in S1-S5, no wake even
occurs.
1 | 0 | SMI#. If system was in S1-S5, then a wake event occurs
before the SMI#.
0h
26 1 | 1 | SCI. If system was in S1-S5, then a wake event occurs
RW/V
before the SCI.
Note: To clarify, If rtc_en is set and and RTC_STS gets set during
S0/S0ix and SCI/SMI will be sent depending on the state of SCI_EN
and GBL_SMI_EN.
In addition to its normal reset conditions, PMC also clears this bit
due to emergency shutdown events: - Power button override - CPU
thermal trip.
25
0h Reserved (reserved6): Reserved.
RO
23:22
0h Reserved (reserved7): Reserved.
RO
0h Global Enable (gbl_en): The global enable bit. When both the
21
RW GBL_EN and the GBL_STS are set, PMC generates an SCI.
20:17
0h Reserved (reserved8): Reserved.
RO
Wake Status (wak_sts): This bit is set when the system is in one
of the Sleep states (via the SLP_EN bit) and an enabled Wake event
occurs. Upon setting this bit, the PMC will transition the system to
the ON state. This bit can only be set by hardware and can only be
cleared by writing a one to this bit position. If a power failure
0h occurs (such as removed batteries) without the SLP_EN bit set, the
15
RW/1C/V WAK_STS bit will not be set when the power returns if the
AFTER_G3 bit is 0. If the AFTER_G3 bit is 1, then the WAK_STS bit
will be set after waking from a power failure. If necessary, the BIOS
can clear the WAK_STS bit in this case.
According to ACPI spec 5.0 If the system does not support the S1
sleeping state, the WAK_STS bit can always return zero.
Reserved: PCI Express Wake Status
(rsvd_pciexp_wake_sts): Reference only: This bit is set by
hardware to indicate that the system woke due to a PCI Express
wakeup event. This event can be caused by the PCI Express
WAKE# pins (PMU_WAKE_B, PCI_WAKE1_B, PCI_WAKE2_B,
PCI_WAKE3_B) being active, or one or more of the PCI Express
ports being in beacon state, or receipt of a PCI Express PME
message at root port. This bit should only be set when one of these
events causes the system to transition from a non-S0 system
0h
14 power state to the S0 system power state. This bit is set
RO
independent of the PCIEXP_WAKE_DIS bit.
Software writes a 1 to clear this bit. If one of the WAKE# pins is still
active during the write or one or more PCI Express ports is in the
beacon state or PME message received indication is not cleared in
the root port, then the bit will remain Power Management active
(i.e. all inputs to this bit are level sensitive).
Note: This bit does not itself cause a wake event or prevent entry to
a sleeping state. Thus if the bit is 1 and the system is put into a
sleeping state, the system will not automatically wake.
Reserved: USB clockless Wake Status
(rsvd_usb_clkless_sts): Reference only: This bit is set by
0h
13 hardware to indicate that the system woke due to change in USB
RO
serial lines. This bit is set independent of the USB_CLKLESS_EN bit.
Software writes a 1 to clear this bit.
12
0h Reserved (rsvd): Reserved.
RO
9
0h Reserved (reserved1): Reserved.
RO
7:6
0h Reserved (reserved2): Reserved.
RO
4:1
0h Reserved (rserved3): Reserved.
RO
Default: 0h
31:14
0h Reserved (rsvd): Reserved.
RO
9:3
0h Reserved (reserved1): Reserved.
RO
1
0h BM RLD (bm_rld): This bit is treated as a scratch pad bit.
RW
SCI Enable (sci_en): Selects the SCI interrupt or the SMI# for
0h various events. When this bit is 1, then the events will generate an
0
RW SCI interrupt. When this bit is 0, these events will generate an
SMI#.
Default: 0h
31:24
0h Reserved (rsvd): Reserved.
RO
Access Method
Default: 0h
31:22
0h Reserved (rsvd31): Reserved.
RO
CSE SCI Status (cse_sci_sts): This bit will be set to 1 by the PMC
when CSE sends an Assert_SCI message to the PMC. Additionally, if
0h the CSE_SCI_EN and SCI_EN bits are set, and the system is in an
21
RW/1C/V S0 state, then the setting of the CSE_SCI_STS bit will generate an
SCI (or SMI# if SCI_EN is not set but GLB_SMI_EN is). This bit is
cleared by a software write of '1'.
eSPI SCI Status (espi_sci_sts): This bit will be set when an
0h agent attached to eSPI is requesting an SCI via an Assert_SCI
20
RW/1C/V message with tag 001b. Note: This source is not able to cause a SX
wake event.
SPI PME Status (spi_pme_sts): This bit will be set to 1 by the
PMC when eSPI sends a PME Virtual Wire message to the PMC with
VWIDX==12h, VWVLD[3]==1, VWLVL[3]==0 (PME#).
0h
19 Additionally, if the SPI_PME_EN and SCI_EN bits are set, and the
RW/1C/V
system is in an S0 state, then the setting of the SPI _PME_STS bit
will generate an SCI (or SMI# if SCI_EN is not set but GLB_SMI_EN
is). This bit is cleared by a software write of '1'.
5
0h Reserved (rsvd5): Reserved.
RO
1
0h Reserved (rsvd): Reserved.
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
31:22
0h Reserved (rsvd31): Reserved.
RO
5
0h Reserved (rsvd5): Reserved.
RO
1
0h Reserved (rsvd): Reserved.
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Default: 2h
31:30
0h Reserved (rsvd): Reserved.
RO
25
0h Reserved (rsvd25): Reserved.
RO
24:22
0h Reserved (reserved24_22): Reserved.
RO
9:8
0h Reserved (reserved5): Reserved.
RO
Default: 0h
31:30
0h Reserved (rsvd): Reserved.
RO
SPI SMI Status (spi_smi_sts): This bit will be set when the SPI
0h
26 logic is requesting an SMI# via a message sent from SPI to PMC#
RW/1C/V
with tag 111b.
25
0h Reserved (rsvd25): Reserved.
RO
24:22
0h Reserved (reserved2): Reserved.
RO
1:0
0h Reserved (reserved7): Reserved.
RO
Access Method
Default: 0h
31:16
0h Reserved (rsvd16): Reserved.
RO
15:13
0h Reserved (rsvd15): Reserved.
RO
12
0h Device Trap Status Bit 12 (d12_trp_sts): KBC (60/64h)
RW/1C/V
11:6
0h Reserved (rsvd11): Reserved.
RO
4:0
0h Reserved (rsvd4): Reserved.
RO
Default: 0h
31:18
0h Reserved (rsvd): Reserved.
RO
16:0
0h Reserved (reserved1): Reserved.
RO
Default: 0h
31:10
0h Reserved (rsvd): Reserved.
RO
TCO Timer Value (tco_val): Reading this register will return the
0h
9:0 current count of the TCO timer. Writing any value to this register
RO/V
will reload the timer to prevent the timeout.
Default: 0h
31:18
0h Reserved (reserved2): Reserved.
RO
16:4
0h Reserved (reserved1): Reserved.
RO
2:0
0h Reserved (rsvd): Reserved.
RO
Default: 0h
31:22
0h Reserved (rsvd): Reserved.
RO
19:13
0h Reserved (reserved2): Reserved.
RO
TCO Lock (tco_lock): When set to 1, this bit prevents writes from
changing the TCO_EN bit (in offset 30h of Power Management I/O
0h space). Once this bit is set to 1, it cannot be cleared by software
12
RW/L writing a 0 to this bit location. Reset is required to change this bit
from 1 to 0. This bit defaults to 0. On some prior platforms, this
field is reset on cold reset.
TCO Timer Halt (tco_tmr_halt): 1: The TCO timer will halt. It
will not count, and thus cannot reach a value that would cause an
0h
11 SMI# or to cause the SECOND_TO_STS bit to be set. This will also
RW
prevent rebooting.
0: The TCO timer is enabled to count. This is the default.
10:0
0h Reserved (reserved1): Reserved.
RO
Default: 40000h
31:26
0h Reserved (reserved1): Reserved.
RO
15:0
0h Reserved (rsvd): Reserved.
RO
Default: 0h
23:0
0h Reserved (rsvd): Reserved.
RO
Default: 0h
31:24
0h Reserved (reserved0): Reserved.
RO
15:0
0h Reserved (reserved1): Reserved.
RO
Default: 0h
31:10
0h Reserved (reserved0): Reserved.
RO
Access Method
Default: 0h
14:8
0h Reserved (reserved2): Reserved.
RO
5:0
0h Reserved (reserved1): Reserved.
RO
Access Method
Default: 0h
31:20
0h Reserved (reserved4): Reserved.
RO
15:10
0h Reserved (reserved3): Reserved.
RO
7:6
0h Reserved (reserved2): Reserved.
RO
2:0
0h Reserved (reserved1): Reserved.
RO
Access Method
Default: 0h
27:11
0h Reserved (reserved0): Reserved.
RO
9:0
0h Reserved (reserved1): Reserved.
RO
Access Method
Default: 0h
31:3
0h Reserved (rsvd): Reserved.
RO
0
0h Reserved (reserved1): Reserved.
RO
Default: 4004h
31:28
0h Reserved (reserved6): Reserved.
RO
22
0h Reserved (reserved5): Reserved.
RO
17
0h Reserved (reserved4): Reserved
RO
13:10
0h Reserved (Reserved3): Reserved
RO
8
0h Reserved (Reserved2): Reserved.
RO
5:3
0h Reserved (reserved1): Reserved.
RO
RTC Power Status (rps): Intel SOC will set this bit to 1 when
RTEST_B indicates a weak or missing battery. The bit will remain
set until the software clears it by writing a 0 back to this bit
1h
2 position. This bit is not cleared by any type of reset because a
RW/V
cleared shadowed value will be restored prior to this bit being
visible.
Note: Relevant only for no PMIC mode while SoC includes RTC well.
1
0h Reserved (reserved0): Reserved.
RO
Default: 3800h
31:14
0h Reserved (reserved1): Reserved.
RO
8:5
0h Reserved (reserved3): Reserved.
RO
3:2
0h Reserved (reserved4): Reserved.
RO
Default: 0h
31:13
0h Reserved (reserved1): Reserved.
RO
9:6
0h Reserved (reserved2): Reserved.
RO
2:0
0h Reserved (reserved3): Reserved.
RO
Default: 0h
31:2
0h Reserved (rsvd): Reserved.
RO
RID Select (rid_sel): Software writes this field to select the fuse
sets reflected in PCI config space Revision ID. The decoding is: 00:
Revision ID
0h
1:0 01: CRID 0
RW/L
10: CRID 1
11: CRID 2
(setid multicast sends this out)
Access Method
Default: 0h
30
0h SPI Disable (spi): Set by BIOS to inform PMC SPI is disabled.
RW/L
28
0h AVS Disable (avs): Set by BIOS to inform PMC AVS is disabled.
RW/L
24
0h ISH Disable (ish): Set by BIOS to inform PMC ISH is disabled.
RW/L
2
0h UFS Disable (ufs): Set by BIOS to inform PMC UFS is disabled.
RW/L
0
0h xDCI Disable (xdci): Set by BIOS to inform PMC xDCI is disabled.
RW/L
Access Method
Default: 0h
31:10
0h Reserved (rsvd31): Reserved.
RO
0
0h Reserved (rsvd0): Reserved.
RO
Default: 38000h
0h CF9h Lockdown (cf9lock): When set, this will lock the CF9h-
31
RW/L Global-Reset bit. When set, this register locks itself.
30:21
0h Reserved (reserved3): Reserved.
RO
CF9h Global Reset (cf9gr): When this bit is set, a CF9h write of
6h or Eh will cause a Global Reset (of the Host partition where the
designation is applicable). If this bit is cleared, a CF9h write of 6h
or Eh will only reset the Host partition (Cold or Warm reset were no
0h Host partition.) It is recommended that BIOS should set this bit
20
RW/L early on in the boot sequence, and then clear it and set the
CF9LOCK bit prior to loading the OS. When this bit is set, the
hardware assumes that bit 18 (CF9h Without Resume Well Reset
Enable) is cleared. This register is locked by the CF9 Lockdown
(CF9LOCK) bit.
19:18
0h Reserved (reserved2): Reserved.
RO
14:0
0h Reserved (reserved1): Reserved.
RO
05: SB_PORTID_GPNW_CORE
04: SB_PORTID_GPNW_CORE
03: SB_PORTID_GPNW_CORE
02: SB_PORTID_GPNW_CORE
01: SB_PORTID_GPIOSCC
00: SB_PORTID_GPIOSCC
Access Method
Default: 6300h
31:16
0h Reserved (rsvd31): Reserved.
RO
Access Method
Default: FF00h
31:16
0h Reserved (rsvd31): Reserved.
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
SCI IRQ Select (scis): Specifies on which IRQ the SCI will
internally appear. ACPI uses this field to fill the IRQ vector of the
De/Assert_IRQn message for IOAPIC IRQ for PMIC interrupts. If not
using the APIC, the SCI must be routed to IRQ[9-11], and that
interrupt is not shareable with the SERIRQ stream, but is shareable
0h with other PCI interrupts. If using the APIC, the SCI can also be
31:24
RW/L mapped to IRQ20-23, and can be shared with other interrupts.
This field fully defines the IRQ number to be sent.
When the interrupt is mapped to APIC interrupts 9, 10 or 11, the
APIC should be programmed for active-high reception. When the
interrupt is mapped to APIC interrupts 20 through 23, the APIC
should be programmed for active-low reception.
PMIC Direct IRQ Select (dir_irq_sel_pmic): ACPI uses this field
0h
23:16 to fill the IRQ vector of the De/Assert_IRQn message for IOAPIC
RW/L
IRQ for PMIC interrupts.
15:0
0h Reserved (rsvd): Reserved.
RO
Access Method
Default: 0h
31
0h Reserved Enable (rsvd31): Reserved.
RO
23
0h Reserved (rsvd23): Reserved.
RO
22
0h Reserved (rsvd22): Reserved.
RO
1
0h Reserved (rsvd1): Reserved.
RO
Access Method
Default: 0h
31:3
0h Reserved (rsvd31): Reserved.
RO
0h USF2 Enable (ufs2): If set by BIOS the named function (3rd lane
2
RW UFS) is exposed to the OS via ACPI
0h PMC PCI Enable (pmc_pci): If set by BIOS the named function is
1
RW exposed to the OS via ACPI.
0h P2SB Enable (p2sb): If set by BIOS the named function is
0
RW exposed to the OS via ACPI.
Default: 0h
Default: 0h
Default: 0h
Default: 0h
Access Method
Default: 0h
Default: 0h
Access Method
Default: 8h
31
0h Scratchpad 31 (scratchpad31): Scratchpad bit
RW/V
30
0h Scratchpad 30 (scratchpad30): Scratchpad bit
RW/V
29
0h Scratchpad 29 (scratchpad29): Scratchpad bit
RW/V
28
0h Scratchpad 28 (scratchpad28): Scratchpad bit
RW/V
27
0h Scratchpad 27 (scratchpad27): Scratchpad bit
RW
26
0h Scratchpad 26 (scratchpad26): Scratchpad bit
RW
25
0h Scratchpad 25 (scratchpad25): Scratchpad bit
RW
24
0h Scratchpad 24 (scratchpad24): Scratchpad bit
RW
23
0h Scratchpad 23 (scratchpad23): Scratchpad bit
RW
22
0h Scratchpad 22 (scratchpad22): Scratchpad bit
RW
21
0h Scratchpad 21 (scratchpad21): Scratchpad bit
RW
20
0h Scratchpad 20 (scratchpad20): Scratchpad bit
RW
19
0h Scratchpad 19 (scratchpad19): Scratchpad bit
RW
18
0h Scratchpad 18 (scratchpad18): Scratchpad bit
RW
17
0h Scratchpad 17 (scratchpad17): Scratchpad bit
RW
16
0h Scratchpad 16 (scratchpad16): Scratchpad bit
RW
15
0h Scratchpad 15 (scratchpad15): Scratchpad bit
RW
14
0h Scratchpad 14 (scratchpad14): Scratchpad bit
RW
13
0h Scratchpad 13 (scratchpad13): Scratchpad bit
RW
12
0h Scratchpad 12 (scratchpad12): Scratchpad bit
RW
11
0h Scratchpad 11 (scratchpad11): Scratchpad bit
RW
10
0h Scratchpad 10 (scratchpad10): Scratchpad bit
RW
9
0h Scratchpad 9 (scratchpad9): Scratchpad bit
RW
8
0h Scratchpad 8 (scratchpad8): Scratchpad bit
RW
7
0h Scratchpad 7 (scratchpad7): Scratchpad bit
RW
6
0h Scratchpad 6 (scratchpad6): Scratchpad bit
RW
5
0h Scratchpad 5 (scratchpad5): Scratchpad bit
RW
Access Method
Default: F0h
31:16
0h Reserved (rsvd): Reserved.
RO
Access Method
Default: 0h
31:30
0h rsvd: RESERVED
RO
27
0h force_host_opmode: Override enable for UTMI host opmode
RW
24
0h drive_host_linestate: Override enable for UTMI host line-state
RW
23
0h clr_host_fifo: Override bit to clear the host Tx fifo
RW
16
0h drive_gate_dev_clk: Override enable for device clock gating
RW
13
0h force_dev_xcvrsel: Override enable for UTMI device xcvrselect
RW
10
0h force_dev_opmode: Override enable for UTMI device opmode
RW
7
0h drive_dev_linestate: Override enable for UTMI device line-state
RW
6
0h clr_dev_fifo: Override bit to clear the device Tx fifo
RW
2
0h drive_dev_vbusvalid: Override enable for device vbusvalid
RW
0
0h drive_auxclk_req: Override enable for auxclk request
RW
Access Method
Default: 10h
31:16
0h rsvd: RESERVED
RO
3
0h drive_gate_host_clk: Override enable for host clock gating
RW
0
0h force_host_xcvrsel: Override enable for UTMI host xcvrselect
RW
Access Method
Default: 6450280Fh
Access Method
Default: 0h
31:14
0h Reserved (rsvd): Reserved.
RO
ESPI SMI Lock (espi_smi): When this bit is set, writes to the
0h acpi.smi_en.ESPI_SMI_EN bit will have no effect. Once the
13
RW/L LOCK.ESPI_SMI bit is set, writes of 0 to the LOCK.ESPI_SMI bit will
have no effect.
OBFF Lock (obff): Locks GCR.OBFF_CTL_STS.Tobff1, Tobff2,
0h Tobff3, PORT0_OBFF_DISABLE, PORT1_OBFF_DISABLE,
12
RW/L PORT2_OBFF_DISABLE, PORT3_OBFF_DISABLE. This field is also
self-locking.
0h Power Button Lock (pwrbtn): Locks
11
RW/L GCR.PMC_CFG2.pwrbtn_dis. This field is also self-locking.
0h LPC Loopback Clock Control Lock (lpc_lpb_clk_ctrl): Locks
10
RW/L GCR.GEN_PMCON2.lpc_lpb_clk_ctrl. This field is also self-locking.
ASLP Sx# Stretching Policy Lock-Down
(slpsx_str_pol_lock): When set to 1, this bit locks down the
following fields: GEN_PMCON3.DIS_SLP_X_STRCH_SUSPF
GEN_PMCON3.SLP_S3_MIN_ASST_WDTH
GEN_PMCON3.S4MAW
GEN_PMCON3.S4ASE
PM_CFG.SLP_A_MIN_ASST_WDTH (if applicable)
0h PM_CFG.SLP_LAN_MIN_ASST_WDTH (if applicable)
9
RW/L PM_CFG.PWR_CYC_DUR
Those bits become read-only. This bit becomes locked when a value
of 1b is written to it. Writes of 0 to this bit are always ignored. Once
locked by writing 1, the only way to clear this bit is to perform a
platform reset.
This lockdown bit is available in both desktop and mobile.
Note: Relevant only for no PMIC mode.
0h IRQ Select Lock (irq_sel)
8
RW/L
5
0h Reserved (rsvd_pcie): Reserved: PCIE lock.
RO
2
0h Reserved (s0ix): Reserved.
RW/L
0
0h Reserved (reserved0): Reserved.
RO
The IPC CMD register is used for conveying the type of commands to the IPC block.
This is a special kind of register and a write to this register always results in Interrupt
to the ARC and Setting of the busy bit in the IPC_STS register. The setting of busy bit in
the IPC_STS register results in blocking of all transaction from the IA host. The ARC FW
is expected to read the IPC_CMD register, whenever interrupted, interpret it and follow
the instructions as ordered by the IA host. The IA host may optionally prefer to be
interrupted, when the command is complete by sending an MSI. When the ARC FW is
done with the command, it is expected to update the IPC_STS register and clear the
busy bit.
Access Method
Default: 0h
31:24
0h Reserved (Reserved0): Reserved.
RW
Size (size): Size of the transaction in bytes. This 8-bit field can
potentially specify 256 Bytes, but the hardware based write_buffer
0h
23:16 and read_buffer are both only 16 bytes deep. So the size should not
RW
be greater than 16bytes for normal reads and normal write
operation. However, larger sizes can be used for indirect operations.
Command ID (cmd_ID): ID or Tag associated with this
0h
15:12 command. When the IPC command is completed, this value is
RW
copied in the IPC_STS register by the hardware.
11:9
0h Reserved (rsvd): Reserved.
RW
8
0h MSI (msi): Send an MSI once the command is executed.
RW
0h
• 02h: Indirect Read
7:0
RW • 03h: Reserved
• 04h: Read DMA
• 05h: Indirect write
• 06h: FFh - Reserved
Access Method
Default: 0h
31:24
0h Reserved (rsvd): Reserved.
RO
Error Code (error_code): If the err bit is set, this field may
0h
23:16 contain some error code. ARC FW is responsible for updating this
RW/V
value.
Initiator ID (Initiator_ID): ID of the initiator, whose command
was executed last. The initiator_ID information is available through
the CONNID OCP. This bits are captured by the IPC hardware and
0h placed in this field. This information could be used by the ARC FW
15:8
RO/V to figure out the initiator for any particular IPC command and
whether to service it or not. It may also be used for debug purpose,
when the ARC FW is unable to service some IPC command and sets
the error bit in the IPC_STC register.
Command ID (cmd_ID): ID of the last command. The PMU
0h
7:4 Hardware copies this same field from the IPC_CMD register and
RO/V
places it in this reg.
3
0h Reserved (rsvd1): Reserved.
RO/V
Access Method
Default: 0h
31:0
0h Source Pointer (SPTR): Read transaction source address.
RW
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
PWMCTRL controls the PWM and needs to be accessed in particular order to prevent
any blips. Below is the recommended flow for programming the PWMCTRL registers.
Initial Enable or First Activation:
Dynamic update while PWM is Enabled:
Access Method
Default: 400000h
31
0h Enable (ENABLE): Enable PWM output.
RW
Default: 8h
31:4
0h Reserved (Rsvd): Reserved.
RO
0h D0i3 (i3)
2
RW
Dynamic update while PWM is Enabled:
Access Method
Default: 400000h
31
0h Enable (ENABLE): Enable PWM output.
RW
Dynamic update while PWM is Enabled:
Access Method
Default: 400000h
31
0h Enable (ENABLE): Enable PWM output.
RW
Dynamic update while PWM is Enabled:
Access Method
Default: 400000h
31
0h Enable (ENABLE): Enable PWM output.
RW
§§
0h Device Identification (DID): The upper 8-bits of this field can be overridden by the
31:16
RO/V SetID IOSF-SB Message.
0h
15:0 Vendor Identification (VID): Indicates Intel
RO
0h
15:11 Reserved (RSVD): Reserved
RO
0h
10 Interrupt Disable (INTD): P2SB does not issue any interrupts on its own behalf
RO
0h
9 Fast Back to Back Enable (FB2BE): Not applicable
RO
0h
8 SERR# Enable (SEE): this will enable parity error reporting to IEH
RW
0h
7 Reserved (RSVD_1): Reserved
RO
0h Parity Error Response Enable (PEE): This bit controls the device's response to
6
RW parity error.
0h
5 VGA: Not applicable.
RO
0h
4 Memory Write & Invalidate Enable (MWIE): Not applicable.
RO
0h
3 Special Cycle Enable (SCE): Not applicable.
RO
0h
Bus Master Enable (BME): Bus mastering cannot be disabled as this device acts as a
2 RO
proxy for non-PCI devices.
0h Memory Space Enable (MSE): Will control the P2SB acceptance of PCI MMIO BARs
1
RW only. Other legacy regions are unaffected by this bit.
0h
0 I/O Space Enable (IOSE): Legacy regions are unaffected by this bit.
RW
0h
15 Detected Parity Error (DPE): This register bit is set when parity error is detected.
RO
0h Signaled System Error (SSE): This register will set when PCICMD.SE bit and
14
RO PCISTS.DPE bit is set
0h
13:0 Reserved (RSVD): Reserved
RO
0h Revision ID (RID): Indicates the part revision. This will reset to 0 but will overridden
7:0
RO/V by the SetID IOSFSB message during the power-up sequence
0h
31:24 Reserved (RSVD): Reserved
RO
0h
23:16 Base Class Code (BCC): Indicates a memory controller device class.
RO
0h
15:8 Sub-Class Code (SCC): Indicates an unspecified other memory controller.
RO
0h
7:0 Programming Interface (PI): No programming interface.
RO
0h
7:0 Reserved (RSVD): Reserved
RO
0h
7 Multi-Function Device (MFD): Indicates that this is part of a multi-function device.
RO
0h
6:0 Header Type (HTYPE): Indicates a generic device header.
RO
0h Register Base Address (RBA): Lower DWORD of the base address for the sideband
31:24
RW register access BAR.
0h
3 PREF: Indicates this is not prefetchable.
RO
0h
2:1 Address Type (ATYPE): Indicates that this can be placed anywhere in 64b space.
RO
0h
0 Space Type (STYPE): Indicates memory space
RO
0h Register Base Address (RBAH): Upper DWORD of the base address for the
31:0
RW sideband register access BAR.
0h
31:16 Subsystem ID (SSID): Written by BIOS. Not used by hardware.
RW/O
0h
15:0 Subsystem Vendor ID (SSVID): Written by BIOS. Not used by hardware.
RW/O
0h
15:8 BUS: VLW Bus Number
RW
0h
7:3 DEV: VLW Device Number
RW
0h
2:0 FUNC: VLW Function Number
RW
0h
15:8 BUS: ERROR Bus Number
RW
0h
7:3 DEV: ERROR Device Number
RW
0h
2:0 FUNC: ERROR Function Number
RW
0h
31:16 Reserved (RSVD): Reserved
RW
0h
7:1 Reserved (RSVD_1): Reserved
RW
0h RTC Shadow Enable (RSE): When set, all IO writes to the RTC will be also sent to
0
RW the PMC. This allows cases where the battery backed storage is in an external PMIC.
0h Address Enable (AE): When set, the P2SB will decode the High Performance Timer
7
RW memory address range selected by bits 1:0 below.
0h
6:2 Reserved (RSVD): Reserved
RO
Address Select (AS): This 2-bit field selects 1 of 4 possible memory address ranges
0h for the High Performance Timer functionality. The encodings are: 00 : FED0_0000h -
1:0
RW FED0_03FFFh 01 : FED0_1000h - FED0_13FFFh 10 : FED0_2000h - FED0_23FFFh 11 :
FED0_3000h - FED0_33FFFh
0h
15:9 Reserved (RSVD): Reserved
RO
0h Address Enable (AE): When set, the P2SB will decode the IOxAPIC memory address
8
RW range selected by bits 7:0 below.
0h APIC Range Select (ASEL): These bits define address bits 19:12 for the IOxAPIC
7:0 range. The default value of 00h enables compatibility with prior products as an initial
RW value. This value must not be changed unless the IOxAPIC Enable bit is cleared.
0h
15:8 BUS: IOxAPIC Bus Number
RW
0h
7:3 DEV: IOxAPIC Device Number
RW
0h
2:0 FUNC: IOxAPIC Function Number
RW
0h
15:8 BUS: HPET Bus Number
RO
0h
7:3 DEV: HPET Device Number
RO
0h
2:0 FUNC: HPET Function Number
RO
0h Sideband Register posted 0 (SBREGPOSTED0): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 31-0.
0h Sideband Register posted 1 (SBREGPOSTED1): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 63-32.
0h Sideband Register posted 0 (SBREGPOSTED2): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 95-64.
0h Sideband Register posted 3 (SBREGPOSTED3): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 127-96.
0h Sideband Register posted 4 (SBREGPOSTED4): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 159-128.
0h Sideband Register posted 5 (SBREGPOSTED5): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 191-160.
0h Sideband Register posted 6 (SBREGPOSTED6): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 223-192.
0h Sideband Register posted 7 (SBREGPOSTED7): One hot masks for setting SBREG
31:0
RW to posted posted for IOSF-SB endpoint IDs 255-224.
0h
31:19 Reserved (RSVD): Reserved
RO
0h Display Target Block (DTBLK): This register contains the Target BLK field that will
18:16
RW be used when sending RAVDM messages to the CPU Complex North Display.
0h
15:8 BUS: The bus number of the Display in the CPU Complex.
RW
0h
7:3 DEV: The bus number of the Display in the CPU Complex.
RW
0h
2:0 FUNC: The function number of the Display in the CPU Complex
RW
0h Modulator Control Address Offset (MODBASE): This specifies the upper 8b for the
15:8 16b address that will be used for sending RAVDM access that target the Modulator
RW Control range of the ICC (FFF00h - FFFFFh).
0h Buffer Address Offset (BUFBASE): This specifies the upper 8b for the 16b address
7:0 that will be used for sending RAVDM access that target the Buffer range of the ICC
RW (FFE00h - FFEFFh).
0h Endpoint Mask 0 (EPMASK0): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 31-0.
0h Endpoint Mask 1 (EPMASK1): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 63-32.
0h Endpoint Mask 2 (EPMASK2): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 95-64
0h Endpoint Mask 3 (EPMASK3): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 127-96
0h Endpoint Mask 4 (EPMASK4): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 128-159
0h Endpoint Mask 5 (EPMASK5): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 191-160
0h Endpoint Mask 6 (EPMASK6): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 223-192
0h Endpoint Mask 7 (EPMASK7): One hot masks for disabling IOSF-SB endpoint IDs
31:0
RW/V/L 255-224
0h Destination Port ID (DESTID): The content of this register field is sent in the IOSF
31:24
RW Sideband Message Register Access dest field.
0h
23:20 Reserved (RSVD): Reserved
RO
Root Space (RS): Destination IOSF-SB Root Space. *Note: This register may only be
0h written during manufacturing test. P2SB will only accept writes to this register from
19:16 transactions with a SAI equal to the SBI_RS_ACCESS_SAI parameter. This should be
RW assigned to the SAI used by the functional test module (typically TAM) that will perform
this register write on IOSF-P.
0h Address Offset (OFFSET): Register address offset. The content of this register field
15:0
RW is sent in the IOSF Sideband Message Register Access address(15:0) field.
0h DATA: The content of this register field is sent on the IOSF sideband Message Register
31:0
RW/V Access data(31:0) field.
0h
15:8 OPCODE: This is the Opcode sent in the IOSF sideband message.
RW
0h POSTED: When set to 1, the message will be send as a posted message instead of
7 non-posted. This should only be used if the receiver is known to support posted
RW operations for the specified operation.
0h
6:3 Reserved (RSVD): Reserved
RO
Initiate/ Ready# (INITRDY): 0: The IOSF sideband interface is ready for a new
transaction 1: The IOSF sideband interface is busy with the previous transaction. A
0h write to set this register bit to 1 will trigger an IOSF sideband message on the private
0
RW/1S IOSF sideband interface. The message will be formed based on the values programmed
in the Sideband Message Interface Register Access registers. Software needs to ensure
that the interface is not busy (SBISTAT.INITRDY is clear) before writing to this register.
0h First Byte Enable (FBE): The content of this field is sent in the IOSF Sideband
15:12
RW Register Access FBE field.
0h
11 Reserved (RSVD): Reserved
RO
0h Base Address Register (BAR): The contents of this field are sent in the IOSF
10:8 Sideband Register Access BAR field. This should be zero performing a Memory Mapped
RW operation to a PCI compliant device.
0h Function ID (FID): The contents of this field are sent in the IOSF Sideband Register
7:0 access FID field. This field should generally remain at zero unless specifically required
RW by a particular application.
0h Extended Address (ADDR): The content of this register field is sent on the IOSF
31:0 sideband Message Register Access address(48:32) field. This must be set to all 0 if 16b
RW addressing is desired.
0h SBI register Lock (SBILOCK): Once written, it will not be writeable until module
31 reset. Write once (1 or 0) to lock the Lock Bit. SBISTAT.INITRDY Register bit only lock if
RW/O SBILOCK Bit = 1
0h
30:27 Reserved (RSVD): Reserved
RW
0h Data Parity Error Enable (DPEE): IOSFP data parity error handling(EP bit) enabling
26
RW bit
0h Command Parity Error Enable (CPEE): IOSFP command parity error handling
25
RW enabling bit
0h Data Phase Parity Error Enable (DPPEE): IOSFP data phase parity error handling
24
RW enabling bit
0h
23:18 Reserved (RSVD_3): Reserved
RW
0h Endpoint Mask Lock (MASKLOCK): Locks the value of the EPMASK[0-7] registers.
17
RW/O Once this value is written to a one it may only be cleared by a reset.
0h PGCB Clock Gating Enable (PGCBCGE): When asserted the P2SB can de-assert the
16 clock request to disable the PGCB clock dynamically when it reaches the power down
RW idle state.
0h
15:9 Reserved: (RSVD_1): Reserved
RW
0h HIDE: When this bit is set, the P2SB will return 1s on any PCI Configuration Read on
8 IOSF-P. All other transactions including PCI Configuration Writes are unaffected by this.
RW This does not affect reads performed on the IOSF-SB interface.
0h
7:3 Reserved (RSVD_2): Reserved
RW
Max Writes Pending (MAXW): This controls the max number of outstanding writes
0h on IOSF-SB initiated by MMIO writes to the SBREG_BAR. Once the number of
2:0 SBREG_BAR writes issued but not completed on IOSF-SB is equal to this value no new
RW requests will be forwarded until completions are received. A value of zero will have the
same behavior as the value of one (single write outstanding).
0h
7:6 Reserved (RSVD): Reserved
RO
0h Hardware Autonomous Enable (HAE): When set, the P2SB will automatically
5
RW engage power gating when it has reached its idle condition.
0h
4:3 Reserved (RSVD_1): Reserved
RO
0h
2 D3-Hot Enable (D3HE): No support for D3 Hot power gating.
RO
0h
1 I3 Enable (I3E): No support for S0i3 power gating.
RO
0h PMC Power Gating Enable (PMCPG_EN): When set to 1, the P2SB will engage
0
RW power gating if it is idle and the pmc_p2sb_sw_pg_req_b signal is asserted.
0h
15:12 Reserved (RSVD): Reserved
RW
Primary Reset De-assert to Next State Time (TIRSTUP): Value representing the
0h number of delay clocks required between the deassertion of pgcb_force_prim_rst_b
11:10
RW and the next state in the FSM (varies). 00: 1 clock 01: 2 clocks (default) 10: 8 clocks
11: 256 clocks
0h Primary CLKREQ Hold-On (CKREQHO): Defines the amount of idle time required
15:12 between locking for power gate preparation and deassertion of the prim_clkreq signal.
RW This field defines the exponent such that the actual delay = 2^ CKREQHO.
Primary Domain Lock Hold-Off (LOCKHO): Defines the amount of idle time
0h required between local clock gating and locking for power gate preparation (if power
11:8
RW gating is enabled). This field defines the exponent such that the actual delay = 2^
LOCKHO.
0h Primary Clock Gating Hold-Off (CGATEHO): Defines the amount of idle time
7:4 required before local clock gating will be engaged (if enabled). This field defines the
RW exponent such that the actual delay = 2^ CGATEHO.
0h
3:2 Reserved (RSVD): Reserved
RW
0h
1 Primary CLKREQ DISABLE (CKREQD): Primary CLKREQ DISABLE
RW
0h Primary Clock Gating Disable (CGD): When set to 1, the local clock gating for the
0
RW IOSF-P clock domain within the P2SB will be disabled.
0h Sideband CLKREQ Hold-On (CKREQHO): Defines the amount of idle time required
15:12 between locking for power gate preparation and deassertion of the prim_clkreq signal.
RW This field defines the exponent such that the actual delay = 2^ SCKREQHO.
Sideband Domain Lock Hold-Off (LOCKHO): Defines the amount of idle time
0h required between local clock gating and locking for power gate preparation (if power
11:8
RW gating is enabled). This field defines the exponent such that the actual delay = 2^
PLOCKHO.
0h Sideband Clock Gating Hold-Off (CGATEHO): Defines the amount of idle time
7:4 required before local clock gating will be engaged (if enabled). This field defines the
RW exponent such that the actual delay = 2^ CGATEHO.
0h
3:2 Reserved (RSVD): Reserved
RW
0h
1 Sideband CLKREQ DISABLE (CKREQD): Sideband CLKREQ DISABLE
RW
0h Sideband Clock Gating Disable (CGD): When set to 1, the local clock gating for the
0
RW IOSF-P clock domain within the P2SB will be disabled.
0h
31:9 Reserved (RSVD): Reserved
RO
0h
7:2 Reserved (RSVD_1): Reserved
RO
0h Unsupported Non-Posted Request Error Status (UNPE): When set, indicates that
1 P2SB has received unsupported non-posted request;Used only when ENABLE_AER is
RW/1C/P set
0h Unsupported Posted Request Error Status (UPE): When set, indicates that P2SB
0
RW/1C/P has received unsupported posted request;Used only when ENABLE_AER is set
0h
31:9 Reserved (RSVD): Reserved
RO
0h
7:1 Reserved (RSVD_1): Reserved
RO
0h Error Reporting Enable (ERE): When set, error logged in UES register will trigger
0
RW/P error reporting flow in P2SB; Used only when ENABLE_AER is set
0h
31:28 Reserved (RSVD): Reserved
RO
0h
27:24 DOT: Indicates the dot process
RO/V
0h
15:8 Manufacturing Identifier (MID): 0Fh = Intel
RO
0h
7:0 RO/V PROC: Indicates the process. The dot portion of the process is reflected in bits (27:24)
0h
31:0 SAI Policy Control 0 (SAIPOLCTRL0): SAI policy control register bits[31:0]
RW/V
0h
31:0 SAI Policy Control 1 (SAIPOLCTRL1): SAI policy control register bits[63:32]
RW/V
0h SAI Policy Access Control 0 (SAIPOLAC0): SAI policy Access control register
31:0
RW/V bits[31:0]
0h SAI Policy Access Control 1 (SAIPOLAC1): SAI policy Access control register
31:0
RW/V bits[63:32]
§§
12 PWM Registers
This chapter documents the registers in Bus: 0, Device 26, Function 0.
0h
31:30 Reserved Field (RESERVED0): Reserved
RO
0h
29 STATUSCOMMAND- RMA Field (RMA): Received Master Abort
RW/1C/V
0h
28 STATUSCOMMAND- RTA Field (RTA): Received Target Abort
RW/1C/V
0h
27:21 Reserved Field (RESERVED1): Reserved
RO
1h STATUSCOMMAND- Cap List Field (CAPLIST): Capabilities List: Indicates that the
20
RO controller contains a capabilities pointer list
0h
18:16 Reserved Field (RESERVED2): Reserved
RO
0h
15:11 Reserved Field (RESERVED3): Reserved
RO
0h
9 Reserved Field (RESERVED4): Reserved
RO
0h
7:3 Reserved Field (RESERVED5): Reserved
RO
0h
2 STATUSCOMMAND- BME Field (BME): Bus Master Enable
RW
0h
1 STATUSCOMMAND- MSE Field (MSE): Memory Space Enable
RW
C8000h REVCLASSCODE - Class code Field (CLASS_CODES): Class Code register is read-
31:8 only and is used to identify the generic function of the device and in some cases a
RO/V specific register-level programming interface
0h
31:24 Reserved Field (RESERVED0): Reserved
RO
0h
7:0 CLLATHEADERBIST - Cache Line Size Field (CACHELINE_SIZE): Cacheline Size
RW
0h BAR -Base Address Field (BASEADDR): Base Address Register Low Base address
31:12
RW of the OCP fabric memory space. Taken from Strap values as ones
0h BAR -Size Field (SIZEINDICATOR): Size Indicator RO Always returns 0 The size of
11:4
RO this register depends on the size of the memory space
0h BAR -Type Field (TYPE): If BAR_64b_EN is 0 then 00 indicates BAR lies in 32bit
2:1
RO address range If BAR_64b_EN is 1 then 10 Indicates BAR lies in 64 bit address range
0h
31:0 BAR -Base Address High Field (BASEADDR_HIGH): Base Address high - MSB
RW
0h BAR1 - Base Address Field (BASEADDR1): Base Address1 This field is present if
31:12
RW BAR1 is enabled through private configuration space.
0h
11:4 BAR1 -Size Field (SIZEINDICATOR1): Always is 0 as minimum size is 4K
RO
0h BAR1 -Type Field (TYPE1): If BAR_64b_EN is 0 then 00 indicates BAR lies in 32bit
2:1
RO address range If BAR_64b_EN is 1 then 10 Indicates BAR lies in 64 bit address range
0h
31:2 BASEADDR:
RW
0h
1 RESERVED0: Reserved
RO
0h
0 MESSAGE_SPACE:
RO
0h SUBSYSTEMID: Subsystem ID: This register is implemented for any function that can
31:16
RW/O be instantiated more than once in a given system.
0h
31:8 Reserved Field (RESERVED0): Reserved
RO
0h
15:12 Reserved Field (RESERVED0): Reserved
RO
9h POWERCAPID - PME Support Field (PMESUPPORT): This 5-bit field indicates the
31:27
RO power states in which the function can assert the PME#
0h
26:19 Reserved Field (RESERVED0): Reserved
RO
0h POWERCAPID - Next Cap Field (NXTCAP): Next Capability: Points to the next
15:8
RO capability structure.
0h
31:16 Reserved Field (RESERVED0): Reserved
RO
0h
15 PMECTRLSTATUS - PME Status Field (PMESTATUS): PME Status
RW/1C/V
0h
14:9 Reserved Field (RESERVED1): Reserved
RO
0h
8 PMECTRLSTATUS - PME Enable Field (PMEENABLE): PME Enable
RW
0h
7:4 Reserved Field (RESERVED2): Reserved
RO
0h
2 Reserved Field (RESERVED3): Reserved
RO
0h
15:8 PCIDEVIDLE_CAP_REG - Next Capability Field (NEXT_CAP): Next Capability
RO
9h
7:0 PCIDEVIDLE_CAP_REG - Capability ID Field (CAPID): Capability ID
RO
10h DEVID VENDOR SPECIFIC REG - Vendor Specific Length Field (VSECID):
15:0
RO Vendor Specific Extended Capability ID
0h
31:22 Reserved Field (RESERVED0): Reserved
RO
0h
20 Reserved Field (RESERVED1): Reserved
RO
0h
15:13 Reserved Field (RESERVED2): Reserved
RO
4000F1Ch Manufacturers ID - MAN ID (MANID): Manufacturer ID: Default value comes from
31:0
RO/V straps.
§§
NOTE: Register default values are taken from device SDMMC0 only. Refer Vol1 for
Device IDs.
0h
31:16 DEVICEID:
RO
8086h
15:0 VENDORID:
RO
0h
31:30 RESERVED0: Reserved
RO
0h
29 RMA:
RW/1C
0h
28 RTA:
RW/1C
0h
27:21 RESERVED1: Reserved
RO
1h
20 CAPLIST:
RO
0h
19 INTR_STATUS:
RO
0h
18:16 RESERVED2: Reserved
RO
0h
15:11 RESERVED3: Reserved
RO
0h
10 INTR_DISABLE:
RW
0h
9 RESERVED4: Reserved
RO
0h
8 SERR_ENABLE:
RW
0h
7:3 RESERVED5: Reserved
RO
0h
2 BME:
RW
0h
1 MSE:
RW
0h
0 RESERVED6: Reserved
RO
80501h
31:8 CLASS_CODES:
RO
0h
7:0 RID:
RO
0h
31:24 RESERVED0: Reserved
RO
0h
23 MULFNDEV:
RO
0h
22:16 HEADERTYPE:
RO
0h
15:8 LATTIMER:
RO
0h
7:0 CACHELINE_SIZE:
RW
0h
31:12 BASEADDR:
RW
0h
11:4 SIZEINDICATOR:
RO
0h
3 PREFETCHABLE:
RO
2h
2:1 TYPE:
RO
0h
0 MESSAGE_SPACE:
RO
0h
31:0 BASEADDR_HIGH:
RW
0h
31:12 BASEADDR1:
RW
0h
11:4 SIZEINDICATOR1:
RO
0h
3 PREFETCHABLE1:
RO
2h
2:1 TYPE1:
RO
0h
0 MESSAGE_SPACE1:
RO
0h
31:0 BASEADDR1_HIGH:
RW
0h
31:16 SUBSYSTEMID:
RW/O
0h
15:0 SUBSYSTEMVENDORID:
RW/O
0h
31:0 EXPANSION_ROM_BASE:
RO
0h
31:8 RESERVED0: Reserved
RO
80h
7:0 CAPPTR_POWER:
RO
0h
31:24 MAX_LAT:
RO
0h
23:16 MIN_GNT:
RO
0h
15:12 RESERVED0: Reserved
RO
0h
11:8 INTPIN:
RO
0h
7:0 INTLINE:
RW
0h
31:27 PMESUPPORT:
RO
0h
26:19 RESERVED0: Reserved
RO
3h
18:16 VERSION:
RO
90h
15:8 NXTCAP:
RO
1h
7:0 POWER_CAP:
RO
0h
31:16 RESERVED0: Reserved
RO
0h
15 PMESTATUS:
RW/1C
0h
14:9 RESERVED1: Reserved
RO
0h
8 PMEENABLE:
RW
0h
7:4 RESERVED2: Reserved
RO
1h
3 NO_SOFT_RESET:
RO
0h
2 RESERVED3: Reserved
RO
0h
1:0 POWERSTATE:
RW
Fh
31:28 VEND_CAP:
RO
0h
27:24 REVID:
RO
14h
23:16 CAP_LENGTH:
RO
0h
15:8 NEXT_CAP:
RO
9h
7:0 CAPID:
RO
14h
31:20 VSEC_LENGTH:
RO
0h
19:16 VSEC_REV:
RO
10h
15:0 VSECID:
RO
804h
31:4 SW_LAT_DWORD_OFFSET:
RO
0h
3:1 SW_LAT_BAR_NUM:
RO
1h
0 SW_LAT_VALID:
RO
81Ch
31:4 DWORD_OFFSET:
RO
0h
3:1 BAR_NUM:
RO
1h
0 VALID:
RO
0h
31:22 RESERVED0: Reserved
RO
1h
21 HAE:
RW
0h
20 RESERVED1: Reserved
RO
1h
19 SLEEP_EN:
RW
0h
18 PGE:
RW
0h
17 I3_ENABLE:
RW
1h
16 PMCRE:
RW
0h
15:13 RESERVED2: Reserved
RO
2h
12:10 POW_LAT_SCALE:
RW/O
0h
9:0 POW_LAT_VALUE:
RW/O
0h
31:0 GEN_REG_RW1:
RW
0h
31:0 GEN_REG_RW2:
RW
0h
31:0 GEN_REG_RW3:
RW
0h
31:0 GEN_REG_RW4:
RW
0h
31:0 GEN_REG_INPUT_RW:
RO
Fh
31:0 MANID
RO
Access Method
Default: 800h
0h
31:16 Reserved.
RO
9:0
0h Snoop_value (Snoop_value): 10-bit latency value
RW
Access Method
Default: 800h
0h
31:16 Reserved.
RO
14:13
0h Reserved_low field (Reserved_low): Reserved_low
RO
9:0
0h Snoop_value (Snoop_value): 10-bit latency value
RW
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 3041EF3Ch
0h
31:30 Reserved.
RO
Access Method
Default: 40040C8h
0h
31:27 Reserved.
RO
0h
15 Reserved.
RO
Access Method
Default: 8h
0h
31:4 Reserved.
RO
Access Method
Default: 500h
0h
31:15 Reserved.
RO
Access Method
Default: A18h
0h
31:15 Reserved.
RO
Access Method
Default: 1C2A1C00h
0h
31 Reserved.
RO
Access Method
Default: E0000h
0h
31 Reserved.
RO
Access Method
Default: 0h
0h
31:17 Reserved.
RO
Access Method
Default: 10000h
0h
31:18 Reserved.
RO
path pll (path_pll): Rx Path PLL #3 Delay value For Auto Tuning
0h
13:8 Mode 0-39 - Select the required delay, as a multiple of 125pSec.40
RW
63 Reserved
0h
7 Reserved.
RO
Access Method
Default: 1h
0h
31:25 Reserved.
RO
23
0h DLL lock (DLL_lock): Master DLL Lock Indication
RO
3
0h less (less): Phase Detection Less Indication
RO/V
2
0h more (more): Phase Detector More Indication
RO/V
Access Method
Default: 0h
0h
31:5 Reserved.
RO
4:0
0h Auto_tuning_val (Auto_tuning_val): Auto tuning value
RO/V
Access Method
Default: 0h
0h
31:1 Reserved.
RO
Access Method
Default: 800h
0h
31:16 Reserved.
RO
9:0
0h Snoop_value (Snoop_value): 10-bit latency value
RW
Access Method
Default: 800h
0h
31:16 Reserved.
RO
14:13
0h Reserved_low field (Reserved_low): Reserved_low
RO
9:0
0h Snoop_value (Snoop_value): 10-bit latency value
RW
Access Method
Default: 0h
0h
31:8 Reserved.
RO
Access Method
Default: 3041EF3Ch
0h
31:30 Reserved.
RO
Access Method
Default: 40040C8h
0h
31:27 Reserved.
RO
Access Method
Default: 8h
0h
31:4 Reserved.
RO
Access Method
Default: 500h
0h
31:15 Reserved.
RO
Access Method
Default: A18h
0h
31:15 Reserved.
RO
Access Method
Default: 1C2A1C00h
0h
31 Reserved.
RO
Access Method
Default: E0000h
0h
31 Reserved.
RO
Access Method
Default: 10000h
0h
31:18 Reserved.
RO
path pll (path_pll): Rx Path PLL #3 Delay value For Auto Tuning
0h
13:8 Mode 0-39 - Select the required delay, as a multiple of 125pSec.40
RW
63 Reserved
0h
7 Reserved.
RO
Access Method
Default: 0h
0h
31:5 Reserved.
RO
4:0
0h Auto_tuning_val (Auto_tuning_val): Auto tuning value
RO/V
Access Method
Default: 0h
Access Method
Default: 0h
0h
15 Reserved.
RO
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
0h
15:6 Reserved.
RO
Access Method
Default: 0h
0h
15:14 Reserved.
RO
0h command_responsetype (command_responsetype):
1:0
RW Response Type Select.
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
0h
31:29 Reserved.
RO
sdhcsdctrl_retuningreq_dsync
0h
3 (sdhcsdctrl_retuningreq_dsync): Host Controller may request
RO
Host Driver to execute re-tuning sequence by setting this bit.
0h sdhcdmactrl_datalineactive (sdhcdmactrl_datalineactive):
2
RO This bit indicates whether one of the DAT line on SD bus is in use.
presentstate_inhibitdat (presentstate_inhibitdat): This status
0h
1 bit is generated if either the DAT Line Active or the Read transfer
RO
Active is set to 1.
presentstate_inhibitcmd (presentstate_inhibitcmd): If this
bit is 0, it indicates the CMD line is not in use and the HC can issue
0h
0 a SD command using the CMD line. This bit is set immediately after
RO
the Command register (00Fh) is written. This bit is cleared when
the command response is received.
Access Method
Default: 0h
Access Method
Default: 0h
0h
7:5 Reserved.
RO
Access Method
Default: 80h
Access Method
Default: 0h
0h
7:3 Reserved.
RO
Access Method
Default: 0h
Access Method
Default: 0h
0h
7:4 Reserved.
RO
Access Method
Default: 0h
0h
7:3 Reserved.
RO
Access Method
Default: 0h
Access Method
Default: 0h
0h
15:13 Reserved.
RO
errorintrsts_cmdtimeouterror
0h
0 (errorintrsts_cmdtimeouterror): This bit is set if no response is
RW/1C
returned within 64 SDCLK cycles from the end bit of the command.
Access Method
Default: 0h
normalintrsts_enableregbit15
0h
15 (normalintrsts_enableregbit15): The HC shall control error
RW
Interrupts using the Error Interrupt Status Enable register.
normalintrsts_enableregbit14
0h
14 (normalintrsts_enableregbit14): This status is set if the boot
RW
operation gets terminated.
normalintrsts_enableregbit13
0h
13 (normalintrsts_enableregbit13): This status is set if the boot
RW
acknowledge is received from device.
normalintrsts_enableregbit12
0h
12 (normalintrsts_enableregbit12): This status is set if Re-Tuning
RW
Request in the Present State register changes from 0 to 1.
normalintrsts_enableregbit11
0h
11 (normalintrsts_enableregbit11): If this bit is set to 0, the Host
RW
Controller shall clear the interrupt request to the System.
normalintrsts_enableregbit10
0h
10 (normalintrsts_enableregbit10): If this bit is set to 0, the Host
RW
Controller shall clear the interrupt request to the System.
normalintrsts_enableregbit9
0h
9 (normalintrsts_enableregbit9): If this bit is set to 0, the Host
RW
Controller shall clear the interrupt request to the System.
sdhcregset_cardintstsena (sdhcregset_cardintstsena): If
0h this bit is set to 0, the HC shall clear Interrupt request to the
8
RW System. The Card Interrupt detection is stopped when this bit is
cleared and restarted when this bit is set to 1.
sdhcregset_cardremstsena (sdhcregset_cardremstsena):
0h
7 This status is set if the Card Inserted in the Present State register
RW
changes from 1 to 0.
Access Method
Default: 0h
0h
15:13 Reserved.
RO
0h errorintrsts_enableregbit12 (errorintrsts_enableregbit12):
12
RW Occurs when detecting ERROR in m_hresp(dma transaction)
0h
11 Reserved.
RO
errorintrsts_enableregbit10 (errorintrsts_enableregbit10):
0h
10 This status is set if INT_B is enabled and INT_B# pin is in low level.
RW
It is cleared by resetting
errorintrsts_enableregbit9 (errorintrsts_enableregbit9):
0h
9 This bit is set when the Host Controller detects errors during ADMA
RW
based data transfer.
errorintrsts_enableregbit8 (errorintrsts_enableregbit8):
0h
8 This bit is set when detecting that one of the bits D00-D04 in Auto
RW
CMD Error Status register has changed from 0 to 1.
errorintrsts_enableregbit7 (errorintrsts_enableregbit7): If
0h this bit is 1, it means that the HC is not supplying power to SD card
7
RW due to some failure.Reading 0 means that the HC is supplying
power and no error has occurred.
errorintrsts_enableregbit6 (errorintrsts_enableregbit6):
0h
6 Occurs when detecting 0 at the end bit position of read data which
RW
uses the DAT line or the end bit position of the CRC status.
errorintrsts_enableregbit5 (errorintrsts_enableregbit5):
0h Occurs when detecting CRC error when transferring read data
5
RW which uses the DAT line or when detecting the Write CRC Status
having a value of other than 010.
0h errorintrsts_enableregbit4 (errorintrsts_enableregbit4):
4
RW This status is set if Data Timeout error occurs.
errorintrsts_enableregbit3 (errorintrsts_enableregbit3):
0h
3 Occurs if a Command Index error occurs in the Command
RW
Response.
errorintrsts_enableregbit2 (errorintrsts_enableregbit2):
0h
2 Occurs when detecting that the end bit of a command response is
RW
0.
0h errorintrsts_enableregbit1 (errorintrsts_enableregbit1):
1
RW This bit is set when Command CRC Error is generated.
errorintrsts_enableregbit0 (errorintrsts_enableregbit0):
0h
0 This bit is set if no response is returned within 64 SDCLK cycles
RW
from the end bit of the command.
Access Method
Default: 0h
normalintrsts_enableregbit15
0h
15 (normalintrsts_enableregbit15): The HD shall control error
RO
Interrupts using the Error Interrupt Signal Enable register.
normalintrsts_enableregbit14
0h
14 (normalintrsts_enableregbit14): Boot Terminate Interrupt
RW
Signal Enable
0h normalintrsts_enableregbit13
13
RW (normalintrsts_enableregbit13): Boot ack rcv Signal Enable
0h normalintrsts_enableregbit12
12
RW (normalintrsts_enableregbit12): Re-Tuning Event Signal Enable
0h normalintrsts_enableregbit11
11
RW (normalintrsts_enableregbit11): INT_C Signal Enable
0h normalintrsts_enableregbit10
10
RW (normalintrsts_enableregbit10): INT_B Signal Enable
0h normalintrsts_enableregbit9
9
RW (normalintrsts_enableregbit9): INT_A Signal Enable
0h sdhcregset_cardintstsena (sdhcregset_cardintstsena): Card
8
RW Interrupt Signal Enable
0h sdhcregset_cardremstsena (sdhcregset_cardremstsena):
7
RW Card Removal Signal Enable
0h sdhcregset_cardinsstsena (sdhcregset_cardinsstsena): Card
6
RW Insertion Signal Enable
normalintrsts_enableregbit5
0h
5 (normalintrsts_enableregbit5): Buffer Read Ready Signal
RW
Enable
normalintrsts_enableregbit4
0h
4 (normalintrsts_enableregbit4): Buffer Write Ready Signal
RW
Enable
0h normalintrsts_enableregbit3
3
RW (normalintrsts_enableregbit3): DMA Interrupt Signal Enable
0h normalintrsts_enableregbit2
2
RW (normalintrsts_enableregbit2): Block Gap Event Signal Enable
normalintrsts_enableregbit1
0h
1 (normalintrsts_enableregbit1): Transfer Complete Signal
RW
Enable
normalintrsts_enableregbit0
0h
0 (normalintrsts_enableregbit0): Command Complete Signal
RW
Enable
Access Method
Default: 0h
0h
15:13 Reserved.
RO
0h errorintrsig_enableregbit12 (errorintrsig_enableregbit12):
12
RO Target Response Error Signal Enable
0h
11 Reserved.
RO
0h errorintrsig_enableregbit10 (errorintrsig_enableregbit10):
10
RW Tuning Error Signal Enable
0h errorintrsig_enableregbit9 (errorintrsig_enableregbit9):
9
RW ADMA Error Signal Enable
0h errorintrsig_enableregbit8 (errorintrsig_enableregbit8):
8
RW Auto CMD Error Signal Enable
0h errorintrsig_enableregbit7 (errorintrsig_enableregbit7):
7
RW Current Limit Error Signal Enable
0h errorintrsig_enableregbit6 (errorintrsig_enableregbit6):
6
RW Data End Bit Error Signal Enable
0h errorintrsig_enableregbit5 (errorintrsig_enableregbit5):
5
RW Data CRC Error Signal Enable
0h errorintrsig_enableregbit4 (errorintrsig_enableregbit4):
4
RW Data Timeout Error Signal Enable
0h errorintrsig_enableregbit3 (errorintrsig_enableregbit3):
3
RW Command Index Error Signal Enable
0h errorintrsig_enableregbit2 (errorintrsig_enableregbit2):
2
RW Command End Bit Error Signal Enable
0h errorintrsig_enableregbit1 (errorintrsig_enableregbit1):
1
RW Command CRC Error Signal Enable
0h errorintrsig_enableregbit0 (errorintrsig_enableregbit0):
0
RW Command Timeout Error Signal Enable
Access Method
Default: 0h
0h
15:8 Reserved.
RO
autocmderrsts_nexterror (autocmderrsts_nexterror):
0h Setting this bit to 1 means CMD_wo_DAT is not executed due to an
7
RO Auto CMD12 error(D04- D01) in this register. This bit is set to 0
when Auto CMD Error is generated by Auto CMD23
0h
6:5 Reserved.
RO
autocmderrsts_indexerror (autocmderrsts_indexerror):
0h
4 Occurs if the Command Index error occurs in response to a
RO
command.
0h autocmderrsts_endbiterror (autocmderrsts_endbiterror):
3
RO Occurs when detecting that the end bit of command response is 0.
0h autocmderrsts_crcerror (autocmderrsts_crcerror): Occurs
2
RO when detecting a CRC error in the command response.
autocmderrsts_timeouterror (autocmderrsts_timeouterror):
0h
1 Occurs if the no response is returned within 64 SDCLK cycles from
RO
the end bit of the command.
autocmderrsts_notexecerror
0h (autocmderrsts_notexecerror): Setting this bit to 1 means the
0
RO HC cannot issue Auto CMD12 to stop memory multiple block
transfer due to some error.
Access Method
Default: 0h
0h hostctrl2_presetvalueenable (hostctrl2_presetvalueenable):
15
RW This bit enables the functions defined in the Preset Value registers.
hostctrl2_asynchintrenable (hostctrl2_asynchintrenable):
0h This bit can be set to 1 if a card support asynchronous interrupt and
14
RW Asynchronous Interrupt Support is set to 1 in the Capabilities
register.
0h
13:10 Reserved.
RO
hostctrl2_driverstrength_bit2
0h
9 (hostctrl2_driverstrength_bit2): This is the programmed Drive
RW
STrength output and Bit[2] of the sdhccore_drivestrength value.
0h
8 Reserved.
RO
0h hostctrl2_samplingclkselect (hostctrl2_samplingclkselect):
7
RW This bit is set by tuning procedure when Execute Tuning is cleared.
hostctrl2_executetuning (hostctrl2_executetuning): This bit
0h
6 is set to 1 to start tuning procedure and automatically cleared when
RW
tuning procedure is completed.
0h hostctrl2_driverstrength (hostctrl2_driverstrength): Host
5:4
RW Controller output driver in 1.8V signaling is selected by this bit.
0h hostctrl2_1p8vsignallingena (hostctrl2_1p8vsignallingena):
3
RW This bit controls voltage regulator for I/O cell.
hostctrl2_uhsmodeselect (hostctrl2_uhsmodeselect): This
0h
2:0 field is used to select one of UHS-I modes and effective when 1.8V
RW
Signaling Enable is set to 1.
Access Method
Default: 0h
corecfg_highspeedsupport (corecfg_highspeedsupport):
0h
21 This bit indicates whether the HC and the Host System support High
RO
Speed mode.
0h
20 Reserved.
RO
Access Method
Default: 0h
0h
63:24 Reserved.
RO
0h corecfg_maxcurrent1p8v (corecfg_maxcurrent1p8v):
23:16
RO Maximum Current for 1.8V
0h corecfg_maxcurrent3p0v (corecfg_maxcurrent3p0v):
15:8
RO Maximum Current for 3.0V
0h corecfg_maxcurrent3p3v (corecfg_maxcurrent3p3v):
7:0
RO Maximum Current for 3.3V
Access Method
Default: 0h
0h
15:8 Reserved.
RO
forcecmdnotissuedbyautocmd12err
0h
7 (forcecmdnotissuedbyautocmd12err): Force Event for
RO
Command Not Issued by AUTO CMD12 Error
0h
6:5 Reserved.
RO
Access Method
Default: 0h
0h
15:11 Reserved.
RO
10
0h forcetuningerr (forcetuningerr): Force Event for Tuning Error
RO
5
0h forcedatcrcerr (forcedatcrcerr): Force Event for Data CRC Error
RO
Access Method
Default: 0h
0h
7:3 Reserved.
RO
admaerrsts_admalenmismatcherr
0h
2 (admaerrsts_admalenmismatcherr): ADMA Length Mismatch
RO
Error
admaerrsts_admaerrorstate (admaerrsts_admaerrorstate):
0h
1:0 This field indicates the state of ADMA when error is occurred during
RO
ADMA data transfer.
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 0h
Access Method
Default: 4h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
4h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 4h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
4h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 2h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
2h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 4h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
4h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 2h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
2h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 1h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
1h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 0h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
0h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 2h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
2h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 0h
Access Method
Default: 0h
0h DriverStrengthSelectValue (DriverStrengthSelectValue):
15:14
RO Driver Strength Select Value
0h
13:11 Reserved.
RO
ClockGeneratorSelectValue (ClockGeneratorSelectValue):
0h
10 This bit is effective when Host Controller supports programmable
RO
clock
SDCLKFrequencySelectValue (SDCLKFrequencySelectValue):
0h
9:0 10-bit preset value to set SDCLK Frequency Select in the Clock
RO
Control Register is described by a host system.
Access Method
Default: 0h
15:1
0h RSVD (Reserved_15_1): Reserved_15_1
RO
Access Method
Default: 0h
0h
15:8 Reserved.
RO
Access Method
Default: 1002h
Access Method
Default: 510h
31:12
0h RSVD (Reserved_51): Reserved_51
RO
Access Method
Default: 30C0h
31:16
0h RSVD (Reserved_52): Reserved_52
RO
11:10
0h RSVD (Reserved_53): Reserved_53
RO
Access Method
Default: 0h
31:13
0h RSVD (Reserved_54): Reserved_54
RO
11:9
0h RSVD (Reserved_11_9): Reserved_11_9
RO
7:1
0h RSVD (Reserved_7_1): Reserved_7_1
RO
Access Method
Default: 0h
31:9
0h RSVD (Reserved_57): Reserved_57
RO
7:1
0h RSVD (Reserved_58): Reserved_58
RO
Halt (Halt): Host software shall write 1 to the bit when it wants to
0h
0 acquire software control over the eMMC bus and disable CQE from
RW
issuing commands on the bus.
Access Method
Default: 0h
31:4
0h RSVD (Reserved_59): Reserved_59
RO
Response_Error_Detected_Interrupt
0h (Response_Error_Detected_Interrupt): This status bit is
2
RW/1C asserted (if CQISTE.RED=1) when a response is received with an
error bit set in the device status field.
Task_Complete_Interrupt (Task_Complete_Interrupt): This
status bit is asserted (if CQISTE.TCC=1) when at least one of the
0h
1 following two conditions are met: (1) A task is completed and the
RW/1C
INT bit is set in its Task Descriptor (2) Interrupt caused by Interrupt
Coalescing logic
Halt_Complete_Interrupt (Halt_Complete_Interrupt): This
0h status bit is asserted (if CQISTE.HAC=1) when halt bit in CQCTL
0
RW/1C register transitions from 0 to 1 indicating that host controller has
completed its current ongoing task and has entered halt state.
Access Method
Default: 0h
31:4
0h RSVD (Reserved_60): Reserved_60
RO
Task_Cleared_Status_Enable
0h
3 (Task_Cleared_Status_Enable): 1 = CQIS.TCL will be set when
RW
its interrupt condition is active 0 = CQIS.TCL is disabled
Response_Error_Detected_Status_Enable
0h (Response_Error_Detected_Status_Enable): 1 = CQIS.RED
2
RW will be set when its interrupt condition is active 0 = CQIS.RED is
disabled
Task_Complete_Status_Enable
0h
1 (Task_Complete_Status_Enable): 1 = CQIS.TCC will be set
RW
when its interrupt condition is active 0 = CQIS.TCC is disabled
Halt_Complete_Status_Enable
0h
0 (Halt_Complete_Status_Enable): 1 = CQIS.HAC will be set
RW
when its interrupt condition is active 0 = CQIS.HAC is disabled
Access Method
Default: 0h
31:4
0h Reserved (Reserved_61): Reserved_61
RO
Task_Cleared_Signal_Enable
0h
3 (Task_Cleared_Signal_Enable): When set and CQIS.TCL is
RW
asserted, the CQE shall generate an interrupt
Response_Error_Detected_Signal_Enable
0h
2 (Response_Error_Detected_Signal_Enable): When set and
RW
CQIS.RED is asserted, the CQE shall generate an interrupt
Task_Complete_Signal_Enable
0h
1 (Task_Complete_Signal_Enable): When set and CQIS.TCC is
RW
asserted, the CQE shall generate an interrupt
Halt_Complete_Signal_Enable
0h
0 (Halt_Complete_Signal_Enable): When set and CQIS.HAC is
RW
asserted, the CQE shall generate an interrupt
Access Method
Default: 0h
30:21
0h Reserved (Reserved_62): Reserved_62
RO
19:17
0h Reserved (Reserved_63): Reserved_63
RO
14:13
0h Reserved (Reserved_64): Reserved_64
RO
Access Method
Default: 0h
cmdquetaskdesclistbaseaddrreg_tdlba
0h (cmdquetaskdesclistbaseaddrreg_tdlba): This register stores
31:0
RW the LSB bits (bits 31:0) of the byte address of the head of the Task
Descriptor List in system memory.
Access Method
Default: 0h
cmdquetaskdesclistbaseadduprreg_tdlba
0h (cmdquetaskdesclistbaseadduprreg_tdlba): This register
31:0
RW stores the MSB bits (bits 63:32) of the byte address of the head of
the Task Descriptor List in system memory.
Access Method
Default: 0h
Access Method
Default: 0h
cmdquetaskdoorbellnotifyreg_ntf
(cmdquetaskdoorbellnotifyreg_ntf): When receiving interrupt
0h
31:0 for task completion, software may read this register to know which
RW
tasks have finished. After reading this register, software may clear
the relevant bit fields by writing 1 to the corresponding bits.
Access Method
Default: 0h
Access Method
Default: 0h
cmdquedevpendtaskreg_pend
0h (cmdquedevpendtaskreg_pend): CQE shall set this bit after
31:0
RO receiving a successful response for CMD45. CQE shall clear this bit
after the task has completed execution.
Access Method
Default: 0h
cmdquequetaskclrreg_clr (cmdquequetaskclrreg_clr):
0h
31:0 Writing 1 to bit n of this register orders CQE to clear a task which
RW
software has previously issued.
Access Method
Default: 11000h
31:20
0h Reserved (Reserved_65): Reserved_65
RO
sendststmrconfig1reg_blkcnt
1h (sendststmrconfig1reg_blkcnt): This field indicates to CQE
19:16
RW when to send SEND_QUEUE_STATUS (CMD13) command to inquire
the status of the device's task queue.
sendststmrconfig1reg_idltmr
1000h (sendststmrconfig1reg_idltmr): This field indicates to CQE the
15:0
RW polling period to use when using periodic SEND_QUEUE_STATUS
(CMD13) polling.
Access Method
Default: 0h
31:16
0h Reserved (Reserved_66): Reserved_66
RO
Access Method
Default: 0h
cmdrespfordirectcmndtaskreg_lstresp
0h (cmdrespfordirectcmndtaskreg_lstresp): This register contains
31:0
RO the response of the command generated by the last direct-
command (DCMD) task which was sent.
Access Method
Default: FDF9A080h
resmodeerrmaskreg_errmask
FDF9A080h (resmodeerrmaskreg_errmask): This bit is used as in interrupt
31:0
RW mask on the device status filed which is received in R1/R1b
responses.
Access Method
Default: 0h
30:29
0h Reserved (Reserved_67): Reserved_67
RO
23:22
0h Reserved (Reserved_68): Reserved_68
RO
14:13
0h Reserved (Reserved_69): Reserved_69
RO
cqtaskerrinforreg_resmodeerrtaskID
0h (cqtaskerrinforreg_resmodeerrtaskID): This field indicates the
12:8
RO ID of the task which was executed on the command line when an
error occurred.
7:6
0h Reserved (Reserved_70): Reserved_70
RO
cqtaskerrinforreg_resmoderrcmdindex
0h (cqtaskerrinforreg_resmoderrcmdindex): This field indicates
5:0
RO the index of the command which was executed on the command
line when an error occurred.
Access Method
Default: 0h
31:6
0h Reserved (Reserved_71): Reserved_71
RO
cmdrespindexreg_lstcmdresindex
0h (cmdrespindexreg_lstcmdresindex): This field stores the index
5:0
RO of the last received command response. CQE shall update the value
every time a command response is received.
Access Method
Default: 0h
cmdrespargument_lstcmdresarg
0h (cmdrespargument_lstcmdresarg): This field stores the
31:0
RO argument of the last received command. CQE shall update the
value every time a command response is received.
§§
14 LPIO Registers
This chapter documents the registers of the LPIO controller devices. The processor
contains multiple LPIO controller devices:
NOTE: Register default values are taken from device LPIO0 only. Refer Vol1 for Device
IDs
AACh
31:16 DEVICEID: Device ID identifies the particular PCI device
RO
8086h VENDORID: Vendor ID is a unique ID provided by the PCI SIG, which identifies the
15:0
RO manufacturer of the device
0h
31:30 RESERVED0: Reserved
RO
0h
29 RMA: Received Master Abort
RW/1C
0h
28 RTA: Received Target Abort
RW/1C
0h
27:21 RESERVED1: Reserved
RO
1h CAPLIST: Capabilities List: Indicates that the controller contains a capabilities pointer
20
RO list
0h
19 INTR_STATUS: Interrupt Status: This bit reflects state of interrupt in the device
RO
0h
18:16 RESERVED2: Reserved
RO
0h
15:11 RESERVED3: Reserved
RO
0h
10 INTR_DISABLE: Interrupt Disable
RW
0h
9 RESERVED4: Reserved
RO
0h
8 SERR_ENABLE: SERR Enable , Not implemented
RW
0h
7:3 RESERVED5: Reserved
RO
0h
2 BME: Bus Master Enable
RW
0h
1 MSE: Memory Space Enable
RW
0h
0 RESERVED6: Reserved
RO
118000h CLASS_CODES: Class Code register is read-only and is used to identify the generic
31:8 function of the device, and in some cases, a specific register-level programming
RO interface
0h
7:0 RID: Revision ID identifies the revision of particular PCI device.
RO
0h
31:24 RESERVED0: Reserved
RO
1h
23 MULFNDEV: Multi-Function Device
RO
0h
22:16 HEADERTYPE: Header Type: Implements Type 0 Configuration header
RO
0h
15:8 LATTIMER: Latency Timer:. This register is implemented as R/W with default as 0
RO
0h
7:0 CACHELINE_SIZE: Cacheline Size
RW
0h BASEADDR: Base Address Register Low, Base address of the OCP fabric memory
31:12
RW space. Taken from Strap values as ones
0h
3 PREFETCHABLE: Prefetchable: Indicates that this BAR is not prefetchable
RO
0h
31:0 BASEADDR_HIGH: Base Address high - MSB
RW
0h BASEADDR1: Base Address1 This field is present if BAR1 is enabled through private
31:12
RW configuration space.
0h
11:4 SIZEINDICATOR1: Always is 0 as minimum size is 4K
RO
0h
3 PREFETCHABLE1: Prefetchable: Indicates that this BAR is not prefetchable.
RO
0h BASEADDR1_HIGH: Base Address: Base address of the OCP fabric memory space.
31:0
RW Taken from Strap values as ones
0h
SUBSYSTEMID: Subsystem ID: This register is implemented for any function that can
31:16
be instantiated more than once in a given system.
RW/O
0h
31:8 RESERVED0: Reserved
RO
80h
7:0 CAPPTR_POWER: Capabilities Pointer: Indicates what the next capability is.
RO
0h MAX_LAT: Value of 0 indicates device has no major requirements for the settings of
31:24
RO latency timers
0h MIN_GNT: Value of 0 indicates device has no major requirements for the settings of
23:16
RO latency timers
0h
15:12 RESERVED0: Reserved
RO
1h INTPIN: Interrupt Pin: Value in this register is reflected from the IPIN value in the
11:8
RO private configuration space.
0h PMESUPPORT: This 5-bit field indicates the power states in which the function can
31:27
RO assert the PME#
0h
26:19 RESERVED0: Reserved
RO
3h VERSION: Indicates support for Revision 1.2 of the PCI Power Management
18:16
RO Specification
90h
15:8 NXTCAP: Next Capability: Points to the next capability structure.
RO
0h
31:16 RESERVED0: Reserved
RO
0h
14:9 RESERVED1: Reserved
RO
0h
8 PMEENABLE: PME Enable
RW
0h
7:4 RESERVED2: Reserved
RO
0h
2 RESERVED3: Reserved
RO
0h POWERSTATE: Power State: This field is used both to determine the current power
1:0
RW state and to set a new power state
Fh
31:28 VEND_CAP: Vendor Specific Capability ID
RO
0h
27:24 REVID: Revision ID of capability structure
RO
14h
23:16 CAP_LENGTH: Vendor Specific Capability Length
RO
0h
15:8 NEXT_CAP: Next Capability
RO
9h
7:0 CAPID: Capability ID
RO
14h
31:20 VSEC_LENGTH: Vendor Specific Extended Capability Length
RO
0h
19:16 VSEC_REV: Vendor specific Extended Capability revision
RO
10h
15:0 VSECID: Vendor Specific Extended Capability ID
RO
210h
31:4 SW_LAT_DWORD_OFFSET: SW LTR Update MMIO Offset Location (SWLTRLOC)
RO
1h
0 SW_LAT_VALID: This value is reflected from the SW LTR valid strap at the top level
RO
24Ch DWORD_OFFSET: contains the location pointer to the SW LTR register in MMIO
31:4
RO space, as an offset from the specified BAR
0h
3:1 BAR_NUM: Bar num: Indicates that the D0i3 MMIO location is always at BAR0
RO
1h
0 VALID: Valid: This value is reflected from the D0i3 valid strap at the top level.
RO
0h
31:22 RESERVED0: Reserved
RO
0h
21 HAE: Hardware Autonomous Enable - LPSS has RO instead of RW
RO
0h
20 RESERVED1: Reserved
RO
1h
19 SLEEP_EN: Sleep Enable
RW
1h PGE: DEVIDLE Enable (DEVIDLEN): If ?1?, then the function will power gate when idle
18
RW and the DevIdle register (DevIdleC[2] = ?1?) is set.
1h I3_ENABLE: D3-Hot Enable (D3HEN): If ?1?, then function will power gate when idle
17
RW and the PMCSR[1:0] register in the function =?11? (D3).
1h
16 PMCRE: PMCRE: PMC Request Enable
RW
0h
15:13 RESERVED2: Reserved
RO
2h
12:10 POW_LAT_SCALE: Power On Latency Scale
RW/O
0h
9:0 POW_LAT_VALUE: Power On Latency value
RW/O
0h GEN_REG_RW1: General Purpose PCI Register: This register value is brought out as
31:0
RW oob_gen_pci_reg1 Out of Band signal
0h GEN_REG_RW2: General Purpose PCI Register: This register value is brought out as
31:0
RW oob_gen_pci_reg2 Out of Band signal
0h GEN_REG_RW3: General Purpose PCI Register: This register value is brought out as
31:0
RW oob_gen_pci_reg3 Out of Band signal
0h GEN_REG_RW4: General Purpose PCI Register: This register value is brought out as
31:0
RW oob_gen_pci_reg4 Out of Band signal
0h
31:0 MANID: Manufacturer ID: Default value comes from straps.
RO
§§
NOTE: Register default values are taken from device LPIO0 only. Refer Vol1 for Device
IDs
0h
31:9 Reserved (RESERVED_31_9): Reserved
NA
0h
8 TX_EMPTY_CTRL:
RW
0h
7 RESERVED_7: Reserved
NA
1h
6 IC_SLAVE_DISABLE:
RW
1h
5 IC_RESTART_EN:
RW
1h
4 IC_10BITADDR_MASTER (IC_10BITADDR_MASTER_RD_ONLY):
RO
0h
3 RESERVED_3: Reserved
NA
3h
2:1 SPEED:
RW
1h
0 MASTER_MODE:
RW
0h
31:13 RESERVED_13_31: Reserved
NA
1h
12 IC_10BITADDR_MASTER:
RW
0h
11 SPECIAL:
RW
0h
10 GC_OR_START:
RW
55h
9:0 IC_TAR:
RW
0h
31:10 RESERVED_10_31: Reserved
NA
55h
9:0 IC_SAR:
RW
0h
31:3 RESERVED_3_31: Reserved
NA
1h
2:0 IC_HS_MAR:
RW
0h
31:11 RESERVED_11_31: Reserved
NA
0h
10 RESTART:
RW
0h
9 STOP:
RW
0h
8 CMD:
RW
0h
7:0 DAT:
RW
0h
31:16 RESERVED_16_31: Reserved
NA
1F4h
15:0 IC_SS_SCL_HCNT:
RW
0h
31:16 RESERVED_16_31: Reserved
NA
24Ch
15:0 IC_SS_SCL_LCNT:
RW
0h
31:16 RESERVED_16_31: Reserved
NA
4Bh
15:0 IC_FS_SCL_HCNT:
RW
0h
31:16 RESERVED_16_31: Reserved
NA
A3h
15:0 IC_FS_SCL_LCNT:
RW
0h
31:16 RESERVED_16_31: Reserved
NA
8h
15:0 IC_HS_SCL_HCNT:
RW
0h
31:16 RESERVED_16_31: Reserved
NA
14h
15:0 IC_HS_SCL_LCNT:
RW
0h
31:14 RESERVED_14_31: Reserved
NA
0h
13 R_MST_ON_HOLD:
RO
0h
12 R_RESTART_DET:
RO
0h
11 R_GEN_CALL:
RO
0h
10 R_START_DET:
RO
0h
9 R_STOP_DET:
RO
0h
8 R_ACTIVITY:
RO
0h
7 R_RX_DONE:
RO
0h
6 R_TX_ABRT:
RO
0h
5 R_RD_REQ:
RO
0h
4 R_TX_EMPTY:
RO
0h
3 R_TX_OVER:
RO
0h
2 R_RX_FULL:
RO
0h
1 R_RX_OVER:
RO
0h
0 R_RX_UNDER:
RO
0h
31:14 RESERVED_31_14: Reserved
NA
0h
13 M_MST_ON_HOLD:
RW
0h
12 M_RESTART_DET:
RO
1h
11 M_GEN_CALL:
RW
0h
10 M_START_DET:
RW
0h
9 M_STOP_DET:
RW
0h
8 M_ACTIVITY:
RW
1h
7 M_RX_DONE:
RW
1h
6 M_TX_ABRT:
RW
1h
5 M_RD_REQ:
RW
1h
4 M_TX_EMPTY:
RW
1h
3 M_TX_OVER:
RW
1h
2 M_RX_FULL:
RW
1h
1 M_RX_OVER:
RW
1h
0 M_RX_UNDER:
RW
0h
31:14 RESERVED_14_31: Reserved
NA
0h
13 MST_ON_HOLD: Same as in reg_IC_INTR_STAT
RO
0h
12 RESTART_DET: Same as in reg_IC_INTR_STAT
RO
0h
11 GEN_CALL: Same as in reg_IC_INTR_STAT
RO
0h
10 START_DET: Same as in reg_IC_INTR_STAT
RO
0h
9 STOP_DET: Same as in reg_IC_INTR_STAT
RO
0h
8 ACTIVITY: Same as in reg_IC_INTR_STAT
RO
0h
7 RX_DONE: Same as in reg_IC_INTR_STAT
RO
0h
6 TX_ABRT: Same as in reg_IC_INTR_STAT
RO
0h
5 RD_REQ: Same as in reg_IC_INTR_STAT
RO
0h
4 TX_EMPTY: Same as in reg_IC_INTR_STAT
RO
0h
3 TX_OVER: Same as in reg_IC_INTR_STAT
RO
0h
2 RX_FULL: Same as in reg_IC_INTR_STAT
RO
0h
1 RX_OVER: Same as in reg_IC_INTR_STAT
RO
0h
0 RX_UNDER: Same as in reg_IC_INTR_STAT
RO
0h
31:8 RESERVED_8_31: Reserved
RO
0h
7:0 RX_TL:
RW
0h
31:8 RESERVED_8_31: Reserved
NA
0h
7:0 TX_TL:
RW
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_INTR:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_RX_UNDER:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_RX_OVER:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h CLR_TX_OVER: Read this register to clear the TX_OVER interrupt (bit 3) of the
0
RO IC_RAW_INTR_STAT register.
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_RD_REQ:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_TX_ABRT:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_RX_DONE:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_ACTIVITY:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_STOP_DET:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_START_DET:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 CLR_GEN_CALL:
RO
0h
31:2 RESERVED_2_31: Reserved
NA
0h
1 ABORT:
RW
0h
0 ENABLE:
RW
0h
31:7 RESERVED_7_31: Reserved
NA
0h
6 SLV_ACTIVITY:
RO
0h
5 MST_ACTIVITY:
RO
0h
4 RFF:
RO
0h
3 RFNE:
RO
1h
2 TFE:
RO
1h
1 TFNF:
RO
0h
0 ACTIVITY: I2C Activity Status
RO
0h
31:9 RESERVED_9_31: Reserved
NA
0h
8:0 TXFLR:
RO
0h
31:9 RESERVED_9_31: Reserved
NA
0h
8:0 RXFLR:
RO
0h
31:16 RESERVED_16_31: Reserved
NA
1h
15:0 IC_SDA_HOLD: Sets the required SDA hold time in units of ic_clk period.
RW
0h
31:24 TX_FLUSH_CNT:
RO
0h
23:17 RESERVED_23_17: Reserved
NA
0h
16 ABRT_USER_ABRT:
RO
0h
15 ABRT_SLVRD_INTX:
RO
0h
14 ABRT_SLV_ARBLOST:
RO
0h
13 ABRT_SLVFLUSH_TXFIFO:
RO
0h
12 ARB_LOST:
RO
0h
11 ABRT_MASTER_DIS:
RO
0h
10 ABRT_10B_RD_NORSTRT:
RO
0h
9 ABRT_SBYTE_NORSTRT:
RO
0h
8 ABRT_HS_NORSTRT:
RO
0h
7 ABRT_SBYTE_ACKDET:
RO
0h
6 ABRT_HS_ACKDET:
RO
0h
5 ABRT_GCALL_READ:
RO
0h
4 ABRT_GCALL_NOACK:
RO
0h
3 ABRT_TXDATA_NOACK:
RO
0h
2 ABRT_10ADDR2_NOACK:
RO
0h
1 ABRT_10ADDR1_NOACK:
RO
0h
0 ABRT_7B_ADDR_NOACK:
RO
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 NACK:
RW
0h
31:2 RESERVED_2_31: Reserved
NA
0h
1 TDMAE:
RW
0h
0 RDMAE:
RW
0h
31:8 RESERVED_8_31: Reserved
NA
0h
7:0 DMATDL:
RW
0h
31:8 RESERVED_8_31: Reserved
NA
0h
7:0 DMARDL:
RW
0h
31:8 RESERVED_8_31: Reserved
NA
64h
7:0 SDA_SETUP:
RW
0h
31:1 RESERVED_1_31: Reserved
NA
1h
0 ACK_GEN_CALL:
RW
0h
31:3 RESERVED_3_31: Reserved
NA
0h
2 SLV_RX_DATA_LOST:
RO
0h
1 SLV_DISABLED_WHILE_BUSY:
RO
0h
0 IC_EN:
RO
0h
31:8 RESERVED_8_31: Reserved
NA
7h
7:0 IC_FS_SPKLEN:
RW
0h
31:8 RESERVED_8_31: Reserved
NA
2h
7:0 IC_HS_SPKLEN:
RW
0h
31:1 RESERVED_1_31: Reserved
NA
0h
0 IC_CLR_RESTART_DET:
RO
0h
31:24 RESERVED_24_31: Reserved
NA
3Fh
23:16 TX_BUFFER_DEPTH:
RO
1h
7 ADD_ENCODED_PARAMS:
RO
1h
6 HAS_DMA:
RO
1h
5 INTR_IO:
RO
0h
4 HC_COUNT_VALUES:
RO
3h
3:2 MAX_SPEED_MODE:
RO
2h
1:0 APB_DATA_WIDTH:
RO
3132312Ah
31:0 IC_COMP_VERSION
RO
44570140h
31:0 IC_COMP_TYPE:
RO
0h
31:0 I2C_RESERVED0_REG: i2c reserved0 register
NA
0h
31:3 RESERVED: Reserved
NA
0h
2 RESET_DMA: DMA sw reset
RW
0h
1:0 RESET_IP: i2c functional (serial) reset
RW
0h
31 SDA_MUX_SEL: sda_mux_sel
RW
0h
30 SDA_SIGNAL_STATE: sda_signal_state
RW
0h
29 SCL_MUX_SEL: scl_mux_sel
RW
0h
28 SCL_SIGNAL_STATE: scl_signal_state
RW
0h
27 I2C_SDA_RD_PRE_DRIVE: i2c_sda_rd_pre_drive
RO
1h
26 I2C_SDA_RD_POST_DRIVE: i2c_sda_rd_post_drive
RO
0h
25 I2C_SCL_RD_PRE_DRIVE: i2c_scl_rd_pre_drive
RO
1h
24 I2C_SCL_RD_POST_DRIVE: i2c_scl_rd_post_drive
RO
0h
23:5 reserved (I2C_GENERAL_REG_23_5): reserved bits in i2c GEENRAL reg
NA
0h TX_LASTBYTE_FLAG: tx last byte (tx transaction completed) flag bit in i2c GENERAL
4
RW reg
0h
3 IO_VOLTAGE_SELECT: io voltage select bit in i2c GENERAL reg
RW
0h
2:0 reserved1 (I2C_GENERAL_REG_0): i2c GENERAL reg reserved bit 0
NA
0h
30:29 RESERVED_HIGH: Reserved
NA
0h
25:16 NON_SNOOP_VALUE: 10-bit latency value
RO
SNOOP_REQUIRMENT: If the Requirement (bit 15) is clear, that indicates that the
0h device has no LTR requirement for this type of traffic (i.e. it can wait for service
15
RW indefinitely). If the 10-bit latency value is zero it indicates that the device cannot
tolerate any delay and needs the best possible service/response time.
0h
14:13 RESERVED_LOW: Reserved
NA
0h
9:0 SNOOP_VALUE: 10-bit latency value
RW
0h
30:29 RESERVED_HIGH: Reserved
NA
0h
25:16 NON_SNOOP_VALUE: 10-bit latency value
RO
SNOOP_REQUIRMENT: If the Requirement (bit 15) is clear, that indicates that the
0h device has no LTR requirement for this type of traffic (i.e. it can wait for service
15
RW indefinitely). If the 10-bit latency value is zero it indicates that the device cannot
tolerate any delay and needs the best possible service/response time.
0h
14:13 RESERVED_LOW: Reserved
NA
2h SNOOP_LATENCY_SCALE: Support for codes 010 (1us) or 011 (32us) for Snoop
12:10 Latency Scale(1us -> 32ms total span) only. Writes to this CSR which dont match
RW those values will be dropped completely, next read will return previous value.
0h
9:0 SNOOP_VALUE: 10-bit latency value
RW
0h
31 tx_count_overflow (TX_ACK_COUNT_OVERFLOW): count overflow indication
RO
0h
30:24 RESERVED: Reserved
NA
0h
23:0 TX_ACK_COUNT: Count ACK seen on Write commands
RO
0h
30:24 RESERVED: Reserved
NA
0h
23:0 RX_ACK_COUNT: Counts ACK seen on Read commands
RO
0h
31:2 RESERVED: Reserved
NA
0h
31:1 RESERVED: Reserved
NA
0h
31:0 SW_SCRATCH_0: sw scratch reg 0
RW
0h
31:0 i2c_sw_scratch_1_reg (SW_SCRATCH_1): sw scratch reg 1
RW
0h
31:0 i2c_sw_scratch_2_reg (SW_SCRATCH_2): sw scratch reg 2
RW
0h
31:0 i2c_sw_scratch_3_reg (SW_SCRATCH_3): sw scratch reg 3
RW
0h
31:4 RESERVED: Reserved
NA
0h SW_DMA_CLK_CTL: dma clock gate cntrol bits, 00-hw clk en,01-rsv, 10-force off,
3:2
RW 11-force on
0h SW_IP_CLK_CTL: ip clock gate cntrol bits, 00-hw clk en,01-rsv, 10-force off, 11-
1:0
RW force on
0h
31:0 i2c_reserved1_reg (RESERVED1): Reserved
NA
0h
31:0 I2C_REMAP_ADDR_LO_REG: i2c remap addr lo reg
RW
0h
31:0 I2C_REMAP_ADDR_HI: i2c remap addr hi reg
RW
0h
31:0 i2c_reserved2_reg (RESERVED2): Reserved
NA
0h
31:5 RESERVED: Reserved
NA
0h
4 INTR_REQ_CAPABLE: intr_req_capable
RO
1h
3 RESTORE_REQUIRED: restore_required
RW/1C
0h
2 DEVIDLE: devidle
RW
0h
1 INTR_REQ: intr_req
RO
0h
0 CMD_IN_PROGRESS: cmd_in_progress
RO
0h
31:11 RESERVED: Reserved
NA
1h
10 VTOUCH_CAP: vtouch_cap
NA
1h
9 SERIAL_CLK_FREQ: 1-133 Mhz
RO
0h
8 IDMA_PRESENT: 0= DMA present 1= DMA not present
RO
0h
7:4 INSTANCE_TYPE: I2C, SPI or UART
RO
0h
3:0 INSTANCE_NUMBER: i2c0 - 000 i2c1 - 001 .. i2c5- 101
RO
SAR_LO: Current Source Address of DMA transfer. Updated after each source transfer.
The SINC field in the CTL_LO[n]: Control Register determines whether the address
increments or is left unchanged on every source transfer throughout the block transfer.
When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the
updated source transfer addresses. However, when the channel is disabled, the original
programmed value will be reflected when reading this register. It's important to notice
the following: 1. Once the block transfer is in progress (i.e. when channel is enabled),
the read-back value correlates with the OCP Read Address that one would see in an
0h OCP tracker. 2. If the read to this register comes during a block transfer, the LAST DMA
31:0 Read address sent on the OCP before the register read is what's reflected in the read-
RW back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-
back value reflects the first address of the burst read since this is what gets sent on the
OCP fabric. 4. If the read to the register occurred after the whole block got transferred,
then the channel gets disabled and the returned value would be the original
programmed value. 5. Since the read-back value is OCP based, only DW aligned
addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6.
Based on the above remarks, this value should be used as pseudo DMA read progress
indicator when the channel is enabled and not an absolute one. Decrementing
addresses are not supported
SAR_HI: Current Source Address of DMA transfer. Updated after each source transfer.
The SINC field in the CTL_LO[n]: Control Register determines whether the address
increments or is left unchanged on every source transfer throughout the block transfer.
When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the
updated source transfer addresses. However, when the channel is disabled, the original
programmed value will be reflected when reading this register. It's important to notice
the following: 1. Once the block transfer is in progress (i.e. when channel is enabled),
the read-back value correlates with the OCP Read Address that one would see in an
0h OCP tracker. 2. If the read to this register comes during a block transfer, the LAST DMA
31:0 Read address sent on the OCP before the register read is what's reflected in the read-
RW back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-
back value reflects the first address of the burst read since this is what gets sent on the
OCP fabric. 4. If the read to the register occurred after the whole block got transferred,
then the channel gets disabled and the returned value would be the original
programmed value. 5. Since the read-back value is OCP based, only DW aligned
addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6.
Based on the above remarks, this value should be used as pseudo DMA read progress
indicator when the channel is enabled and not an absolute one. Decrementing
addresses are not supported
DAR_HI: Current Destination Address of DMA transfer. Updated after each destination
transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the
address increments or is left unchanged on every destination transfer throughout the
block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will
reflect the updated destination transfer addresses. However, when the channel is
disabled, the original programmed value will be reflected when reading this register.
It's important to notice the following: 1. Once the block transfer is in progress (i.e.
when channel is enabled), the read-back value correlates with the OCP Write Address
0h that one would see in an OCP tracker. 2. If the read to this register comes during a
31:0 block transfer, the LAST DMA Write address sent on the OCP before the register read is
RW what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e.
burst length > 1), the read-back value reflects the first address of the burst write since
this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the
whole block got transferred, then the channel gets disabled and the returned value
would be the original programmed value. 5. Since the read-back value is OCP based,
only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be
reflected) 6. Based on the above remarks, this value should be used as pseudo DMA
write progress indicator when the channel is enabled and not an absolute one.
Decrementing addresses are not supported
linked lists are not enabled. This register must be programmed prior to enabling the
channel in order to set up the transfer type. LLP.LOC != 0 contains the pointer to the
next LLI for block chaining using linked lists, The LLPx register can also point to the
address where write-back of the control and source/destination status information
occur after block completion.
LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that
0h the two LSBs of the starting address are not stored because the address is assumed to
31:2
RW be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be
changed or programmed to anything other than 32-bit.
0h
1:0 RSVD2: Reserved
NA
LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that
0h the two LSBs of the starting address are not stored because the address is assumed to
31:2
RW be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be
changed or programmed to anything other than 32-bit.
0h
1:0 RSVD2: Reserved
NA
0h
31:29 RSVD: Reserved
NA
0h LLP_SRC_EN: Block chaining is enabled on the source side only if the LLP_SRC_EN
28
RW field is high and LLPn.LOC is non-zero and (LLP_EN == 1)
0h
26:22 RSVD1: Reserved
RO
0h TT_FC: Transfer Type and Flow Control. The following transfer types are supported.
21:20 Memory to Memory (00) Memory to Peripheral (01) Peripheral to Memory (10)
RW Peripheral to Peripheral (11) Flow Control is always assigned to the DMA.
0h
19 RSVD2: Reserved
NA
0h SRC_MSIZE: Source Burst Transaction Length. Number of data items, each of width
16:14
RW CTL_LOn.SRC_TR_WIDTH, to be read from the source.
0h
9 RSVD3: Reserved
NA
0h
7 RSVD4: Reserved
NA
0h INT_EN: Interrupt Enable Bit. If set, then all interrupt-generating sources are
0
RW enabled.
DONE: If status write-back is enabled, the upper word of the control register,
CTL_HIn, is written to the control register location of the Linked List Item (LLI) in
0h system memory at the end of the block transfer with the done bit set. Software can poll
17 the LLI CTL_HI.DONE bit to see when a block transfer is complete. The LLI
RW CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to
enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is
not cleared.
BLOCK_TS: Block Transfer Size (in Bytes). Since the DMA is always the flow
controller, the user needs to write this field before the channel is enabled in order to
indicate the block size. The number programmed into BLOCK_TS indicates the total
0h number of bytes to transfer for every block transfer. Once the transfer starts (i.e.
16:0 channel is enabled), the read-back value is the total number of bytes for which Read
RW Commands have already been sent to the source. It doesnt mean Bytes that are
already in the FIFO. However, when the channel is disabled, the original programmed
value will be reflected when reading this register. Theoretical Byte Size range is from 0
to (2^17 -1) = (128 KB - 1).
SSTAT: Source status information retrieved by hardware from the address pointed to
by the contents of the Source Status Address Register. This register is a temporary
0h placeholder for the source status information on its way to the SSTATn register location
31:0
RW of the LLI. The source status information should be retrieved by software from the
SSTATn register location of the LLI, and not by a read of this register over the DMA
slave interface.
0h SSTATAR_LO: Pointer from where hardware can fetch the source status information,
31:0 which is registered in the SSTATn register and written out to the SSTATn register
RW location of the LLI before the start of the next block.
0h SSTATAR_HI: Pointer from where hardware can fetch the source status information,
31:0 which is registered in the SSTATn register and written out to the SSTATn register
RW location of the LLI before the start of the next block.
0h DSTATAR_LO: Pointer from where hardware can fetch the destination status
31:0 information, which is registered in the DSTATn register and written out to the DSTATn
RW register location of the LLI before the start of the next block.
0h DSTATAR_HI: Pointer from where hardware can fetch the destination status
31:0 information, which is registered in the DSTATn register and written out to the DSTATn
RW register location of the LLI before the start of the next block.
0h
29:22 RESERVED_29_22: Reserved
NA
0h SRC_OPT_BL: Optimize Source Burst Length : 0 = Writes will use only BL=1 or
21 BL=(2 ^ SRC_MSIZE) 1 = Writes will use (1 <= BL <= (2 ^ SRC_MSIZE)) ***
RW This bit should be set to (0) if Source HW-Handshake is enabled
0h DST_OPT_BL: Optimize Destination Burst Length : 0 = Writes will use only BL=1 or
20 BL=(2 ^ DST_MSIZE) 1 = Writes will use (1 <= BL <= (2 ^ DST_MSIZE)) ***
RW This bit should be set to (0) if Destination HW-Handshake is enabled
0h
19 SRC_HS_POL: Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
RW
0h
17:11 RESERVED_17_11: Reserved
NA
0h CH_DRAIN: Forces channel FIFO to drain while in suspension. This bit has effect only
10
RW when CH_SUSPEND ia asserted
1h FIFO_EMPTY: Indicates if there is data left in the channel FIFO. Can be used in
9 conjunction with CFGx.CH_SUSP to cleanly disable a channel. 1 = Channel FIFO empty
RO 0 = Channel FIFO not empty
CH_SUSP: Channel Suspend. Suspends all DMA data transfers from the source until
0h this bit is cleared. There is no guarantee that the current transaction will complete. Can
8
RW also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without
losing any data. 0 = Not suspended. 1 = Suspend DMA transfer from the source.
SS_UPD_EN: Source Status Update Enable. Source status information is fetched only
0h from the location pointed to by the SSTATARn register, stored in the SSTATn register
7
RW and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is
ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)
0h CTL_HI_UPD_EN: CTL_HI Update Enable. If set, the CTL_HI register is written out
5 to the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN
RW == 0)
0h
4 RSVD_4_4: Reserved
NA
0h ALL_NP_WR: 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port 0x0 : Non-
2 Posted Writes will only be used at end of block transfers and in HW-Handshake (if
RW HW_NP_WR=1); for all other cases, Posted Writes will be used.
1h SRC_BURST_ALIGN: 0x1 : SRC Burst Transfers are broken at a Burst Length aligned
1
RW boundary 0x0 : SRC Burst Transfers are not broken at a Burst Length aligned boundary
1h DST_BURST_ALIGN: 0x1 : DST Burst Transfers are broken at a Burst Length aligned
0
RW boundary 0x0 : DST Burst Transfers are not broken at a Burst Length aligned boundary
0h
31:28 RESERVED_31_28: Reserved
NA
0h WR_ISSUE_THD: Write Issue Threshold. Used to relax the issue criterion for Writes.
27:18 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write burst
RW size = (2 ^ DST_MSIZE)*TW.
0h RD_ISSUE_THD: Read Issue Threshold. Used to relax the issue criterion for Reads.
17:8 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst
RW size = (2 ^ SRC_MSIZE)*TW.
0h SGC: Source gather count. Source contiguous transfer count between successive
31:20
RW gather boundaries.
0h
19:0 SGI: Source gather interval.
RW
0h
19:0 DSI: Destination scatter interval.
RW
SAR_LO: Current Source Address of DMA transfer. Updated after each source transfer.
The SINC field in the CTL_LO[n]: Control Register determines whether the address
increments or is left unchanged on every source transfer throughout the block transfer.
When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the
updated source transfer addresses. However, when the channel is disabled, the original
programmed value will be reflected when reading this register. It's important to notice
the following: 1. Once the block transfer is in progress (i.e. when channel is enabled),
the read-back value correlates with the OCP Read Address that one would see in an
0h OCP tracker. 2. If the read to this register comes during a block transfer, the LAST DMA
31:0 Read address sent on the OCP before the register read is what's reflected in the read-
RW back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-
back value reflects the first address of the burst read since this is what gets sent on the
OCP fabric. 4. If the read to the register occurred after the whole block got transferred,
then the channel gets disabled and the returned value would be the original
programmed value. 5. Since the read-back value is OCP based, only DW aligned
addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6.
Based on the above remarks, this value should be used as pseudo DMA read progress
indicator when the channel is enabled and not an absolute one. Decrementing
addresses are not supported
SAR_HI: Current Source Address of DMA transfer. Updated after each source transfer.
The SINC field in the CTL_LO[n]: Control Register determines whether the address
increments or is left unchanged on every source transfer throughout the block transfer.
When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the
updated source transfer addresses. However, when the channel is disabled, the original
programmed value will be reflected when reading this register. It's important to notice
the following: 1. Once the block transfer is in progress (i.e. when channel is enabled),
the read-back value correlates with the OCP Read Address that one would see in an
0h OCP tracker. 2. If the read to this register comes during a block transfer, the LAST DMA
31:0 Read address sent on the OCP before the register read is what's reflected in the read-
RW back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-
back value reflects the first address of the burst read since this is what gets sent on the
OCP fabric. 4. If the read to the register occurred after the whole block got transferred,
then the channel gets disabled and the returned value would be the original
programmed value. 5. Since the read-back value is OCP based, only DW aligned
addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6.
Based on the above remarks, this value should be used as pseudo DMA read progress
indicator when the channel is enabled and not an absolute one. Decrementing
addresses are not supported
DAR_HI: Current Destination Address of DMA transfer. Updated after each destination
transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the
address increments or is left unchanged on every destination transfer throughout the
block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will
reflect the updated destination transfer addresses. However, when the channel is
disabled, the original programmed value will be reflected when reading this register.
It's important to notice the following: 1. Once the block transfer is in progress (i.e.
when channel is enabled), the read-back value correlates with the OCP Write Address
0h that one would see in an OCP tracker. 2. If the read to this register comes during a
31:0 block transfer, the LAST DMA Write address sent on the OCP before the register read is
RW what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e.
burst length > 1), the read-back value reflects the first address of the burst write since
this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the
whole block got transferred, then the channel gets disabled and the returned value
would be the original programmed value. 5. Since the read-back value is OCP based,
only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be
reflected) 6. Based on the above remarks, this value should be used as pseudo DMA
write progress indicator when the channel is enabled and not an absolute one.
Decrementing addresses are not supported
LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that
0h the two LSBs of the starting address are not stored because the address is assumed to
31:2
RW be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be
changed or programmed to anything other than 32-bit.
0h
1:0 RSVD2: Reserved
NA
LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that
0h the two LSBs of the starting address are not stored because the address is assumed to
31:2
RW be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be
changed or programmed to anything other than 32-bit.
0h
1:0 RSVD2: Reserved
NA
0h
31:29 RSVD: Reserved
NA
0h LLP_SRC_EN: Block chaining is enabled on the source side only if the LLP_SRC_EN
28
RW field is high and LLPn.LOC is non-zero and (LLP_EN == 1)
0h
26:22 RSVD1: Reserved
RO
0h TT_FC: Transfer Type and Flow Control. The following transfer types are supported.
21:20 Memory to Memory (00) Memory to Peripheral (01) Peripheral to Memory (10)
RW Peripheral to Peripheral (11) Flow Control is always assigned to the DMA.
0h
19 RSVD2: Reserved
NA
0h SRC_MSIZE: Source Burst Transaction Length. Number of data items, each of width
16:14
RW CTL_LOn.SRC_TR_WIDTH, to be read from the source.
0h
9 RSVD3: Reserved
NA
0h
7 RSVD4: Reserved
NA
0h INT_EN: Interrupt Enable Bit. If set, then all interrupt-generating sources are
0
RW enabled.
DONE: If status write-back is enabled, the upper word of the control register,
CTL_HIn, is written to the control register location of the Linked List Item (LLI) in
0h system memory at the end of the block transfer with the done bit set. Software can poll
17 the LLI CTL_HI.DONE bit to see when a block transfer is complete. The LLI
RW CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to
enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is
not cleared.
BLOCK_TS: Block Transfer Size (in Bytes). Since the DMA is always the flow
controller, the user needs to write this field before the channel is enabled in order to
indicate the block size. The number programmed into BLOCK_TS indicates the total
0h number of bytes to transfer for every block transfer. Once the transfer starts (i.e.
16:0 channel is enabled), the read-back value is the total number of bytes for which Read
RW Commands have already been sent to the source. It doesnt mean Bytes that are
already in the FIFO. However, when the channel is disabled, the original programmed
value will be reflected when reading this register. Theoretical Byte Size range is from 0
to (2^17 -1) = (128 KB - 1).
SSTAT: Source status information retrieved by hardware from the address pointed to
by the contents of the Source Status Address Register. This register is a temporary
0h placeholder for the source status information on its way to the SSTATn register location
31:0
RW of the LLI. The source status information should be retrieved by software from the
SSTATn register location of the LLI, and not by a read of this register over the DMA
slave interface.
0h SSTATAR_LO: Pointer from where hardware can fetch the source status information,
31:0 which is registered in the SSTATn register and written out to the SSTATn register
RW location of the LLI before the start of the next block.
0h SSTATAR_HI: Pointer from where hardware can fetch the source status information,
31:0 which is registered in the SSTATn register and written out to the SSTATn register
RW location of the LLI before the start of the next block.
0h DSTATAR_LO: Pointer from where hardware can fetch the destination status
31:0 information, which is registered in the DSTATn register and written out to the DSTATn
RW register location of the LLI before the start of the next block.
0h DSTATAR_HI: Pointer from where hardware can fetch the destination status
31:0 information, which is registered in the DSTATn register and written out to the DSTATn
RW register location of the LLI before the start of the next block.
0h
29:22 RESERVED_29_22: Reserved
NA
0h SRC_OPT_BL: Optimize Source Burst Length : 0 = Writes will use only BL=1 or
21 BL=(2 ^ SRC_MSIZE) 1 = Writes will use (1 <= BL <= (2 ^ SRC_MSIZE)) ***
RW This bit should be set to (0) if Source HW-Handshake is enabled
0h DST_OPT_BL: Optimize Destination Burst Length : 0 = Writes will use only BL=1 or
20 BL=(2 ^ DST_MSIZE) 1 = Writes will use (1 <= BL <= (2 ^ DST_MSIZE)) ***
RW This bit should be set to (0) if Destination HW-Handshake is enabled
0h
19 SRC_HS_POL: Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
RW
0h
17:11 RESERVED_17_11: Reserved
NA
0h CH_DRAIN: Forces channel FIFO to drain while in suspension. This bit has effect only
10
RW when CH_SUSPEND ia asserted
1h FIFO_EMPTY: Indicates if there is data left in the channel FIFO. Can be used in
9 conjunction with CFGx.CH_SUSP to cleanly disable a channel. 1 = Channel FIFO empty
RO 0 = Channel FIFO not empty
CH_SUSP: Channel Suspend. Suspends all DMA data transfers from the source until
0h this bit is cleared. There is no guarantee that the current transaction will complete. Can
8
RW also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without
losing any data. 0 = Not suspended. 1 = Suspend DMA transfer from the source.
SS_UPD_EN: Source Status Update Enable. Source status information is fetched only
0h from the location pointed to by the SSTATARn register, stored in the SSTATn register
7
RW and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is
ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)
0h CTL_HI_UPD_EN: CTL_HI Update Enable. If set, the CTL_HI register is written out to
5 the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN
RW == 0)
0h
4 RSVD_4_4: Reserved
NA
0h ALL_NP_WR: 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port 0x0 : Non-
2 Posted Writes will only be used at end of block transfers and in HW-Handshake (if
RW HW_NP_WR=1); for all other cases, Posted Writes will be used.
1h SRC_BURST_ALIGN: 0x1 : SRC Burst Transfers are broken at a Burst Length aligned
1
RW boundary 0x0 : SRC Burst Transfers are not broken at a Burst Length aligned boundary
1h DST_BURST_ALIGN: 0x1 : DST Burst Transfers are broken at a Burst Length aligned
0
RW boundary 0x0 : DST Burst Transfers are not broken at a Burst Length aligned boundary
0h
31:28 RESERVED_31_28: Reserved
NA
0h WR_ISSUE_THD: Write Issue Threshold. Used to relax the issue criterion for Writes.
27:18 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write burst
RW size = (2 ^ DST_MSIZE)*TW.
0h RD_ISSUE_THD: Read Issue Threshold. Used to relax the issue criterion for Reads.
17:8 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst
RW size = (2 ^ SRC_MSIZE)*TW.
0h SGC: Source gather count. Source contiguous transfer count between successive
31:20
RW gather boundaries.
0h
19:0 SGI: Source gather interval.
RW
0h
19:0 DSI: Destination scatter interval.
RW
0h
31:2 RSVD: Reserved
NA
0h
1:0 RAW: Raw interrupt status
RO
0h
31:2 RSVD: Reserved
NA
0h
1:0 RAW: Raw interrupt status
RO
0h
31:2 RSVD: Reserved
NA
0h
1:0 RAW: Raw interrupt status
RO
0h
31:2 RSVD: Reserved
NA
0h
1:0 RAW: Raw interrupt status
RO
0h
31:2 RSVD: Reserved
NA
0h
1:0 RAW: Raw interrupt status
RO
0h
31:2 RSVD: Reserved
NA
0h
1:0 STATUS: Interrupt status
RO
0h
31:2 RSVD: Reserved
NA