ELL201 L5 23aug21 1629569698387

Please note all course content is exclusively for registered IIT-D ELL-201 students in current
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contents/materials takes place.
ELL 201: Digital Electronics
Lecture 5
Prof. Manan Suri (EE)

manansuri@ee.iitd.ac.in
http://web.iitd.ac.in/~manansuri/
M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Logic States & Truth Tables
• Any logical function or logical expression that takes in certain inputs and gives a
certain output (maps a rule or function from input → output)
F (inputs) → Output
• Truth table is a mathematical table or an empirical way of listing the function

outputs corresponding to all combinations of input cases
• Always has 1 column to represent each input variable
• Always has 1 column to denote the final output state
• Thus for ‘n-input’ logical expression a truth table will have at least n+1 coloumns
• Number of rows in truth table = 2N for an N-input variable system (in boolean
algebra)

Recap: Logic Gates – NOT Gate (’)
• Simplest Logic Gate – also known as the complement or the invertor
Truth Table
Symbol Truth Table
X Y=X’
Y = NOT X
X Y=X’ 0 1
1 0
Single Input Gate

Recap: Logic Gates – OR Gate (+)
Symbol Truth Table
X R = X+Y
Y X Y R = X+Y
R = X OR Y
0 0 0
0 1 1
1 0 1
1 1 1
2-Input OR Gate

Recap: Logic Gates – AND Gate (*)
Symbol Truth Table
X R = X*Y
Y X Y R=X*Y
R = X AND Y
0 0 0
0 1 0
1 0 0
1 1 1
2-Input AND Gate

Recap: Boolean Algebra
1 is identity element for AND (*): x*1=x
0 is identity element for OR (+): x+0=x
DeMorgan’s Rule: (A*B)’ = A’ + B’

(A+B)’ = A’*B’

Recap: Universal Logic Gates – NAND & NOR
Symbol
Not-AND
Truth Table
R = (X*Y)’
X X Y R = X NAND Y
Y 0 0 1
0 1 1
Symbol 1 0 1
Not-OR 1 1 0
X R = (X+Y)’ X Y R = X NOR Y
Y 0 0 1
0 1 0
1 0 0
1 1 0
Recap: Prove that NAND is a Universal Gate!
Build a NOT Gate using NAND ?
Output = X’
R = (X*X)’
X
X Y=X’
X
Build AND Gate using NAND ? 1 NAND Gate to build NOT

Output → X*Y
R = (X*Y)’ R1 = (R*R)’
X
Y R1 = ((XY)’)’= XY
2 NAND Gates to build AND
Build OR Gate using NAND ?
Output → X+Y
X X’ R = (X’*Y’)’
= (X+Y)
Y Y’
3 NAND Gates to build OR
Recap: Prove that NOR is a Universal Gate!
Build a NOT Gate using NAND ?
Output = X’
R = (X+X)’
X
X Y=X’
X
Build OR Gate using NOR ? 1 NOR Gate to build NOT

Output → X+Y
R = (X+Y)’ R1 = (R+R)’
X
Y R1 = ((R)’)’= X+Y
2 NOR Gates to build OR
Build AND Gate using NOR ?
Output → X*Y
Try on you own

a b F
Recap: Boolean Functions 0 0 – 1 Different Representations
tations of Boolean Functions
F
0 1 1 : (i) English (ii) Truth Table (iii) Eqn. (iv)
F outputs 1 when a is 0 and b is 01 or0when
0, Circuits
0 a is 0 and b is 1
1.
(c)
English 2:
1: 1F outputs 1 when 1a is10, regardless
Circuit 0 of b’s value
Equation 1: Fa(a,b) = a’ Truth table Circuit 1:
a F (d) a b F
’ + a’b
Representations of Boolean Functions
Circuit 2b
F
a
0 0 1
F=a’
English 1: F outputs 1 when a is 0 and 0 b1 is 0 1 or when a is 0 and b is 1

0, 1.
F English 2: F outputs 11 when 0 0a is 0, regardless of b’s value
(a) (c)
epresentations of Boolean Functions
n different ways Circuit 1 a 1 1 0
a b F
ns of the same functions F(a,b), using
English 1: F outputs 1 when a is 0 andb b is 0
2: Truth table
0, or when a is 0 and b is 1 1.
quation, Circuit, and Truth
a Table F 0 0 1
Equation 2: English 2:
Equation 1: F(a,b) = a’b’ + a’b a’b
F outputs 1 when
Circuit 2: a is 0, (d)
regardless ofFb’s value
(a) 0 1 1
Equation 2: F(a,b) = a a’Circuit
a 2
1 0 0
(b) 7 representations
(c) a b F of
Circuit the 1 same function 1 1 0
function F b 0 0 1 !!
n 1: F(a,b) = a’b’ + a’b F Truth table
0 1 1
en represented
2: F(a,b) = a a’ in different ways a F (d)
1 0 0
ven representations of the same functions
M. Suri, ELL201, F(a,b), using
Circuit
(copyright IITD)
2
"Intended for
(c)
methods: English, Equation, Circuit, and Truth
CircuitTable 1 1 1 0
Recap: Standard Form or Canonical Form
• Truth tables can become impractical for high number of inputs
• Standard Equations can handle large number of inputs
- Sum of Products (SOP)

- Product of Sums (POS)

Recap: Minterms
Minterms of 3 variables
mi = ith minterm
X Y Z Product Symbol m0 m1 m2 m3 m4 m5 m6 m7
Term
0 0 0 X’Y’Z’ m0 1 0 0 0 0 0 0 0
0 0 1 X’Y’Z m1 0 1 0 0 0 0 0 0
0 1 0 X’YZ’ m2 0 0 1 0 0 0 0 0
0 1 1 X’YZ m3 0 0 0 1 0 0 0 0
1 0 0 XY’Z’ m4 0 0 0 0 1 0 0 0
1 0 1 XY’Z m5 0 0 0 0 0 1 0 0
1 1 0 XYZ’ m6 0 0 0 0 0 0 1 0
1 1 1 XYZ m7 0 0 0 0 0 0 0 1
0-complemented mi = 1 only for 1 unique combination of variables

1-uncomplemented i indicates the binary combination for which it is 1

Recap: Maxterms
MAXTERMS of 3 variables
Mi = ith maxterm
X Y Z Sum Symbol M0 M1 M2 M3 M4 M5 M6 M7
Term
0 0 0 X+Y+Z M0 0 1 1 1 1 1 1 1
0 0 1 X+Y+Z’ M1 1 0 1 1 1 1 1 1
0 1 0 X+Y’+Z M2 1 1 0 1 1 1 1 1
0 1 1 X+Y’+Z’ M3 1 1 1 0 1 1 1 1
1 0 0 X’+Y+Z M4 1 1 1 1 0 1 1 1
1 0 1 X’+Y+Z’ M5 1 1 1 1 1 0 1 1
1 1 0 X’+Y’+Z M6 1 1 1 1 1 1 0 1
1 1 1 X’+Y’+Z’ M7 1 1 1 1 1 1 1 0
0-UNcomplemented Mi = 0 only for 1 unique combination of variables

1-complemented i indicates the binary combination for which it is 0

Tentative Timeline
(Note: timeline may change during the semester without any prior notice → details are only of indicative nature)
Lec. No Content
1 Intro + Logistics + Course Policy + Motivation etc
2 Why digital, Number Systems + Conversions etc.
3 Fractional, Complements, Addn, Subtraction
4 Logic Gates, Boolean Algebra, Minterm, Maxterm, SOP, POS
5
KMaps, Minimization, XoR Gate
6
7 XOR Gate, Adders (half/full) + Parity bit circuits + 4-bit adder + subtraction +
8 overflow detection + BCD adder, Ripple Carry, CLA, 4-bit, 16-bit, 64-bit, Timing
9 Analysis, etc.
10
Mux + Decoder + Encoder-1
11
12 PB Set/Assignment or as per need
Minor week
13
14
Sequential Logic - Latches. Flip flops, varieties, counters, registers, digital CMOS,
15
Verilog intro
16
17
18 PB Set/Assignment or as per need
Mid Sem Break
19
20 FSM intro, Moore, Mealy, Examples, Conversions etc.
21
22
Memory, Advanced topics, etc.
23
24 Extra/Buffer/Cover-up class/As per need
Major Exam Week
• Any Boolean function can be expressed as a Sum of Minterms or (Sum
of products) using its Truth Table
• Rule: Take the sum of all those minterms in the Truth Table that have
output as 1
Example:

output as 1
Example:

output as 1
Example:

output as 1
Example:

output as 1
Example:

• Any Boolean function can be expressed as a Product of Maxterms or
(Product of Sums) using its Truth Table
• Rule: Take the Product of all those Maxterms in the Truth Table that
have output as 0
Example:

have output as 0
Example:

have output as 0
Example:

have output as 0
Example:

have output as 0
Example:
Find F’

have output as 0
Example:
Find F’

have output as 0
Example:
Find F’

have output as 0
Example:
Find F’

have output as 0
Example:
Find F’

have output as 0
Example:
Find F’
Minterms and Maxterms are complements! (mi)’ = Mi

Minterms →Maxterms
Example:
POS
Notice that indices are complementary

when moving from
POS → SOP
SOP

Each additional level → increases the length of datapath → increases the
propagation delays !!

Karnaugh Maps

Gray Code
• Binary Numeral system where successive values
differ in only 1 bit

Adjacency
Truth
Truth Table
Table Adjacencies
Adjacencies
Why look at Grey Codes? – concept of ADJACENCY
AA B B FF the selected boolean terms differ by just 1 literal

-Adjacency:
00 0-Adjacency
0 11 HelpsThese in simplification – when expressed in standard form
These adjacent
areadjacent
are inaagray
in graycode
codesense
sense
-Truth table based examples –
00 1 11
1Ex.1 -- they
theydiffer
differby
by11bit
bit
Tocan
We find the
canapply expression
apply XY++XY’ – express
XY’ ==XX in SOP form (minterms)
11 0A0 B00 F We XY
A’B’
A BB ++A’B
A’B’
A AA’B
ABB==A A’(B’+B)
A (B +B)
+B)==A
A’(B’+B)
(B A’(1)
A (1)==A
A’(1)
(1) A’
A
A’
11 101 000 1
AA B B F F
0 1 1
00 1 00 0 00 0 Sameidea:
Same idea:A
A
A’BB++AB
BEx.2
A’B AB==BB
A B F A’B+AB=B
00 1 11 1 11 0
11 00 00 0 0 0
11 11 11 0 1 1
Physical Adjacency in TT
dea:
ea: 1Problem:
0
Problem: 0
not same as gray code
Physical
y adjacency
j
1 y 1 adjacency
Physical 1j y in truth
y in truth adjacency
code adjacencyallows
ode adjacency allowsuse
useof
of tabledoes
table doesnot notindicate
indicategray gray
fication theorems
ication theorems code
code adjacency
adjacency
Karnaugh Maps
• A K-Map exploits adjacency or in other words its at truth table with
physical adjacency
2 Variable Karnaugh Map
• K-Map for a N-variable system will have 2N cells, just like outputs of truth-
table
A B F
0 0
2 – variable K-map A In Minterms
0 1
y
1B
0 1 y
1 0x 0 0 1
x
1 1 0
0 x’y’ x’y 0 A=1,
m0 B=0
m1
A=0 B=0
A=0, 1
1 xy’ xy 1 m2 m3
A=1, B=1
A=0, B=1
A different way to draw a truth table: by folding it

Karnaugh Maps
physical adjacency
table
A B F
0 0
0 1
y B 0 1 y
1 0x 0 1
x
1 1 0
0 A=1,
m0 B=0
m1
A=0 B=0
A=0, 1
1 m2 m3
A=1, B=1
A=0, B=1

Karnaugh Maps
physical adjacency
table
A B F
0 0
0 1
y
1B
0 1 y
1 0x 0 0 1
x
1 1 0
0 0 A=1,
m0 B=0
m1
A=0 B=0
A=0, 1
1 1 m2 m3
A=1, B=1
A=0, B=1

Karnaugh Maps
physical adjacency
table
A B F
0 0
0 1
y
1B
0 1 y
1 0x 0 0 1
x
1 1 0
0 x’y’ x’y 0 A=1,
m0 B=0
m1
A=0 B=0
A=0, 1
1 xy’ xy 1 m2 m3
A=1, B=1
A=0, B=1

Karnaugh Maps
physical adjacency
table
A B F
0 0
0 1
y
1B
0 1 y
1 0x 0 0 1
x
1 1 0
0 x’y’ x’y 0 A=1, B=0
A=0 B=0
A=0, 1
1 xy’ xy 1
A=1, B=1
A=0, B=1

Karnaugh Maps
physical adjacency
table
A B F
0 0
0 1
y
1B
0 1 y
1 0x 0 0 1
x
1 1 0
0 x’y’ x’y 0 A=1,
m0 B=0
m1
A=0 B=0
A=0, 1
1 xy’ xy 1 m2 m3
A=1, B=1
A=0, B=1
A different
Basically way
you are to draw
folding a truth
the truth tabletable: byrepresenting
and then folding it it

Karnaugh Maps
Steps to use a K-Map for simplification –
1.Using the given truth table or boolean expression fill out the corresponding
minterm cells with 1s (maxterm cells with 0s)
2.Make groups of adjacent minterm cells containing 1s (0s in case of

maxterm)
(note: number of cells in each group can only be a power of 2: 1,2,4...)
3.Each group in the K-map will give you a reduced/simplified literal

(from inspection, remove those literals that change across the group, and
retain only those that remain the same)
4. The final simplified expression can be expressed as a sum (or product) of

all reduced literals
Always try to make largest possible groups

Karnaugh Maps

maxterm)



Karnaugh Maps

maxterm)



Karnaugh Maps

maxterm)



Karnaugh Maps

maxterm)



Karnaugh Maps
Example 1

Karnaugh Maps
Example 2

Karnaugh Maps
Example 3

Thank you


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Please note all course content is exclusively for registered IIT-D ELL-201 students in current

semester. It is your responsibility to ensure no unauthorized circulation of the course

ELL 201: Digital Electronics

Prof. Manan Suri (EE)

M. Suri, ELL201, (copyright IITD) "Intended for

• Truth table is a mathematical table or an empirical way of listing the function

• Always has 1 column to represent each input variable

• Always has 1 column to denote the final output state

M. Suri, ELL201, (copyright IITD) "Intended for

Symbol Truth Table

Single Input Gate

M. Suri, ELL201, (copyright IITD) "Intended for

Symbol Truth Table

M. Suri, ELL201, (copyright IITD) "Intended for

Symbol Truth Table

2-Input AND Gate

M. Suri, ELL201, (copyright IITD) "Intended for

DeMorgan’s Rule: (A*B)’ = A’ + B’

M. Suri, ELL201, (copyright IITD) "Intended for

Build AND Gate using NAND ? 1 NAND Gate to build NOT

Build OR Gate using NOR ? 1 NOR Gate to build NOT

Try on you own

M. Suri, ELL201, (copyright IITD) "Intended for

English 1: F outputs 1 when a is 0 and 0 b1 is 0 1 or when a is 0 and b is 1

- Sum of Products (SOP)

M. Suri, ELL201, (copyright IITD) "Intended for

0-complemented mi = 1 only for 1 unique combination of variables

M. Suri, ELL201, (copyright IITD) "Intended for

0-UNcomplemented Mi = 0 only for 1 unique combination of variables

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

Minterms and Maxterms are complements! (mi)’ = Mi

Notice that indices are complementary

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

AA B B FF the selected boolean terms differ by just 1 literal

A different way to draw a truth table: by folding it

M. Suri, ELL201, (copyright IITD) "Intended for

A different way to draw a truth table: by folding it

M. Suri, ELL201, (copyright IITD) "Intended for

A different way to draw a truth table: by folding it

M. Suri, ELL201, (copyright IITD) "Intended for

A different way to draw a truth table: by folding it

M. Suri, ELL201, (copyright IITD) "Intended for

A different way to draw a truth table: by folding it

M. Suri, ELL201, (copyright IITD) "Intended for

M. Suri, ELL201, (copyright IITD) "Intended for

2.Make groups of adjacent minterm cells containing 1s (0s in case of