COMPUTER ARCHETECTURE & ORGANIZATION 1

SY COMPUTER SCIENCE & ENGINEERING

1. What was the name of of government funded computer used in World War II to compute firing
tables?
A) VAX Computer
B) IBM Computer
C) Colossus Computer
D) ENIAC Computer

2. The fundamental conceptual unit in in a computer is

A) CPU
B) Hard Drive
C) Operating system
D) Transister

3. First electronic computer was

A) EDVAC
B) ENIAC
C) IAS
D) None of these

4. ENIAC Means….
A) Electronic Numerical Integrator and Computation
B) Electrical Numerical Integrator and computing
C) Electronic Numerical integration and computer
D) Electronic Numerical integrator and computing

5. EDVAC Means…..
A) Electronic discrete variable and computer
B) Electronic discrete variable and computing
C) Electronic discrete variable and computer
D) Electronic discrete variable and computation

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 2
SY COMPUTER SCIENCE & ENGINEERING

6. ENIAC was a…………… machine.

A) Binary
B) Decimal
C) Hexadecimal
D) Octal
7. …..used stored program concept.
A) EDVAC
B) ENIAC
C) Ins
D) None of these

8. ENIAC data memory consisted of………. Accumulators and capable of storing …….digits decimal
number
A) 10 and 20
B) 20 and 10
C) 20 and 20
D) 10 and 10

9. IN EDVAC programs and their data were located in the………memory.

A) External
B) Separate
C) Additional
D) Same

10. …..invented an influential mechanical calculator

A) Elkert and mauchly
B) Blaise
C) Von Neumann
D) Charles Babbage
11. Floating points representation is used to store
A) Boolean valves
B) Whole number
C) Real number
D) Integer

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 3
SY COMPUTER SCIENCE & ENGINEERING

12. … designed the first mecinacial computer that can perform multistep operations automatically
A) Charge Babbage’s
B) Von Neumann
C) Blaise Pascal
D) Harvard

13. Calculator invented by pascal could do…… operations on decimal numbers

A) Multiply and add
B) Subtract and multiply
C) Compare and add
D) Add and subtract

14. First generation used….

A) Transistor
B) Integrated circuits
C) Vacuum tube
D) VLSI

15. Second generation had remarkable feature of used of….

A) Vaccum tubes
B) Transistors
C) Stored program
D) Integrated circuits

16. Integrated circuits were the feature of used of …

A) First
B) Second
C) Third
D) Fourth

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 4
SY COMPUTER SCIENCE & ENGINEERING

17. VLSI technology used in …… generation

A) First
B) Second
C) Third
D) Fourth

18. …was introduced of first minicomputer

A) IBM system 1360
B) POP 8
C) POP 6
D) IBM system 1340

19. …….introduction bus structure

A) IBM system 1360
B) POP 8
C) POP 6
D) IBM system 1340

20. First computer family was

A) IBM system 1360
B) Pop 8
C) Pop 6
D) IBM system 1340

21. …… and ….. invented IAS( Institute for advanced studies)

A) Von Neumann and gold Stine
B) Von Neumann and Pascal
C) Von Neumann and charge Babbage
D) Eckert and Maucly

22. In original IAS machine storage location was referred to as

A) Byte
B) Word
C) Digit
D) Number
DBATU B.Tech CSE 2nd Year(MH)
https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 5
SY COMPUTER SCIENCE & ENGINEERING

23. In IAS computer……..fetches and interprets the instructions in memory and causes them to be
executed.
A) ALU
B) Control unit
C) Accumulator
D) Program counter

24. Von Neumann architecture is

A) SISD
B) SIMD
C) MIMD
D) MISD

25. In Original Von Neumann machine memory unit consists of …… storage location of……….bits
each
A) 2048, 16
B) 4096, 20
C) 4096, 60
D) 4096, 40

26. In Von Neumann machine ………feature was responsible for performance bottleneck
A. Stored program
B. Separate memory for data and wide
C. I/o access
D. None of these

27. Which of the following operation are involved in an instruction cycles

A) Opcode decoding
B) Instruction execution
C) Instruction fetching
D) All of these.

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 6
SY COMPUTER SCIENCE & ENGINEERING

28. …… stores address of next instruction to be executed

A) AR
B) AC
C) PC
D) IR

29. AR in IAS is …. Wide

A) 12 bit
B) 14 bit
C) 16 bit
D) 48 bit

30. Data register in IAS is……..wide

A) 16 bit
B) 20 bit
C) 40 bit
D) 48 bit

31. Accumulator and MQ (Multiplier Quotient) register in IAS is…….wide.

A) 16 bit
B) 20 bit
C) 40bit
D) 48 bit

32. …..used to store an operand during the execution of instruction

A) AR
B) DR
C) IR
D) IBR

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 7
SY COMPUTER SCIENCE & ENGINEERING

33. Program control unit of IAS fetches………instructions simultaneously

A) Two
B) Three
C) Four
D) Six

34. IR stores……instruction
A) Immediately Executable
B) Later executable
C) Currently executing
D) Aborted type

35. IBR stores……instruction.

A) Immediately executable
B) Later executable
C) Currently executing
D) Aborted type

36. Data transfer instruction…..transfer content register MQ to the accumulator AC

A) ACMQ
B) ACAC+MQ
C) AC →MQ
D) MQAC

37. ….architecture shows separate memory banks for data and program
A) Princeton
B) Harved
C) Von Neumann
D) Rockwell

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 8
SY COMPUTER SCIENCE & ENGINEERING

38. Harvard architecture shows feature of executing instructions in …… instruction cycles than von
Neumann
A) More
B) Double
C) Reduced.
D) Exactly half

39. …. Is the example of Harvard architecture

A) Microprocessor
B) Microcontroller
C) Complier
D) Assemblers

40. ….is the example of Von Neumann architecture

A) Microprocessor
B) Microcontroller
C) Complier
D) Assembler

41. ……..architecture used both RISC and CISC architecture.

A) Von Neumann
B) Harvard
C) Babbage
D) None of these

42. ….architecture used only RISE architecture

A) Von Neumann
B) Harvard
C) Babbage
D) None of these

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 9
SY COMPUTER SCIENCE & ENGINEERING

43. ….bus is unidirectional

A) Data
B) Address
C) Control
D) None of these

44. Use of …..isolates CPU from frequent accesses to main memory

A) Local I/o controller
B) Expansion bus interface.
C) Cache structure
D) System bus
45. In Harvard machine instruction are executed in instruction cycles than von Neumann machine.
A) Fever
B) More
C) Two
D) none of these

46. In Harvard machine greater amount of instruction parallelism is achieved due to separate ......
A) processing units
B) execution units
C) memory banks
D) none of these

47. The instruction suffer register stores

A) Data
B) Address
C) Instruction
D) Operand

48. The first generation computer was designated and constructed by.......
A) Von Neumann
B) Blaise Pascal
C) Charles Babbage
D) Eckert and Mauchly

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 10
SY COMPUTER SCIENCE & ENGINEERING

49. The first generation computer was a…..machine

A) Decimal
B) Binary
C) Octal
D) Hexadecimal

50. Timing involves a clock line. ......

A) Synchronous
B) Asynehronous
C) symmetric
D) None of these
51. . ..... more data between system modules
A) Data bus
B) Address bus
C) Control bus
D) None of these

52. …….designed source or destination of data of the data bus.

A) Data bus.
B) Address bus
C) Control bus
D) None of these

53. ……control access to and use of the data and address lines.
A) Dat bus
B) Address bus
C) Control bus
D) None of these

54. ….timing takes advantage of mixture of slow and fast device sharing the same bus
A) Synchronous
B) Asynchronous
C) Asymmetric
D) None of these

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 11
SY COMPUTER SCIENCE & ENGINEERING

55. Second generation computes can handle operation

A) Fixed point
B) Floating point
C) Both (a) And (b)
D) None of these

56. The opcode fetched from memory is placed in ….. of process

A) Accumulator
B) instruction register
C) instruction decoder
D) data register
57. ......bus is used to connect major computer components.
A) Address
B) Data
C) Control
D) System

58. Data bus is......

A) Unidirectional
B) Bidirectional
C) Unidirectional or Bidirectional
D) none of these

59. .......bus width decides the number of bits transformed at one time.
A) Data
B) Address
C) Control
D) System

60. .....bus width decides the range of locations that can be accessed.
A) Data
B) Address
C) Control
D) System

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO
 COMPUTER ARCHETECTURE & ORGANIZATION 12
SY COMPUTER SCIENCE & ENGINEERING

61. Assembly language

A) uses alphabetic codes in place of binary numbers used in machine language
B) is the earliest language to write programs
C) need not be translated into machine language
D) none of these

62. Any computer must at least consist of

A) Data bus
B) Address bus
C) control bus
D) all of the above
63. A binary digit is called a
A) Bit
B) Byte
C) Number
D) Character

64. In third generation magnetic cone memories were replace by ….. memories
A) Magnetic tape
B) Optical
C) Ic
D) Magnetic disk

DBATU B.Tech CSE 2nd Year(MH)

https://chat.whatsapp.com/ClbWqtrM61t4NrqEgLqjVO