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Adharsh Feee Lab
Adharsh Feee Lab
Adharsh Feee Lab
2021-2022
VERIFICATION OF 3-6
1.
ALL LOGIC
GATES
SUBTRACTOR 16-18
5.
TITLE: Verification of Logic gates & its Truth table.
• OBJECT: To verify Logic gates & its Truth table.
• THEORY:
• AND GATE:
A Boolean operator which gives the value one if and only if all the operands
are one, and otherwise has a value of zero.
A circuit which produces an output signal only when signals are received
simultaneously through all input connections.
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
• OR GATE:
A logical operation which gives the value one if at least one operand has the
value one, and otherwise gives a value of input output zero.
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
• NOT GATE:
A Boolean operator with only one variable that has the value one when the
variable is zero and vice versa.
A circuit which produces an output signal only when there is not a signal on its
input.
A Ā
0 1
1 0
A Boolean operator which gives the value zero if and only if all the operands
have a value of one, and otherwise has a value of one (equivalent to NOT
AND).
A B
0 0 1
0 1 0
1 0 0
1 1 0
• NOR GATE:
A Boolean operator which gives the value one if and only if all operands have a
value of zero and otherwise has a value of zero.
A B
0 0 1
0 1 1
1 0 1
1 1 0
Circuit diagram and truth table
• EXCLUSIVE OR GATE (XOR GATE):
XOR Gate is a digital logic gate that gives a true output when the number of
true inputs is odd. An XOR Gate implements an exclusive or; that is, a true
output result of one, and only one, of the inputs to the gate is true.
A B
0 0 0
0 1 1
1 0 1
1 1 0
An XNOR Gate is a digital logic gate with two or more inputs and one output
that performs logical equality. The output of an XNOR gate is true when all of
its inputs are true or when all of its inputs are false.
A B
0 0 1
0 1 0
1 0 0
1 1 1
• CONCLUSION: The truth table of the logic gates are verified and ok.
• TITLE: Universal Logic Gate
• OBJECT: NAND & NOR as a universal gate & its truth table
• APPARATUS: [i] Digital trainer board.
[ii] Connecting wire.
• NAND TO NOT:
• TRUTH TABLE:
A Y=
A̅
0 1
1 0
• NAND TO OR:
• TRUTH TABLE:
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
• NAND TO AND:
• TRUTH TABLE:
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
NOR GATE AS A UNIVERSAL GATE
• NOR TO OR GATE:
• TRUTH TABLE:
A B 𝐴+𝐵 Y=A+B
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
1 0
• TRUTH TABLE:
A A̅ B B̅ Y=A.B
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1
• TITLE: Verification of De-morgan’s theorem with logic gates.
• OBJECTIVE: To verify De-morgan’s theorem with logic gates and there
truth table.
• DEMORGAN’S THEORY:
DeMorgan’s Theorems are basically two sets of rules or laws developed from
the Boolean expressions for AND, OR and NOT using two input variables, A
and B. These two rules or theorems allow the input variables to be negated and
converted from one form of a Boolean function into an opposite form.
We can also show that 𝐴̅+̅𝐵̅=𝐴̅.𝐵̅ using the following logic gates example
The top logic gate arrangement of: 𝐴̅+̅𝐵̅ can be implemented using a standard
NOR gate function using inputs A and B. The lower logic gate arrangement first
inverts the two inputs, thus producing 𝐴̅ and 𝐵̅. Thus then become the inputs to
the AND gate. Therefore the output from the AND gate becomes: 𝐴̅.𝐵̅
Then we can see that a standard AND gate function with inverters (NOT gates)
on each of its inputs produces an equivalent output condition to a standard NOR
gate function, and an individual NOR gate can be represented in this way as the
equivalency of a NOR gate is a negative-AND.
We can also show that 𝐴̅. ̅𝐵̅ = 𝐴̅+𝐵̅ using logic gates as shown.
The top logic gate arrangement of: 𝐴.̅ 𝐵 ̅ ̅ can be implemented using a
standard NAND gate with inputs A and B. The lower logic gate arrangement
first inverts the two inputs producing 𝐴̅ and 𝐵̅. These then become the inputs to
the OR gate. Therefore the output from the OR gate becomes: 𝐴̅+𝐵̅.
Then we can see here that a standard OR gate function with inverters (NOT
gates) on each of its inputs is equivalent to a NAND gate function. So an
individual NAND gate can be represented in this way as the equivalency of a
NAND gate is a negative-OR.
• CONCLUTION: The original value and practical value are same. The
truth tables are verified and ok.
TITLE: Study of half adder full adder
half subtractor and full subtractor.
• OBJECTIVE: To realize half adder and full adder using logic gates.
• HALF-ADDER:
From Truth table, the logic expression of the sum output can be written as a
Sum of Product expression by summing up the input combination for which the
sum is equal to l.
In the truth table, the sum output is 1 when AB = 01 and AB = 10. Therefore,
the expression for sum is,
The logic symbol of the full adder is shown in the diagrams. It consists of three
inputs and two outputs. The two input variables denoted by A (Augend bit) and
B (Addend bit) represent the two significant bits to be added. The third input C
in represents the carry from the previous lower significant position. The outputs
are designated by the symbols 5 (for sum) and C out (for carry).
The truth table for the full-adder circuit is shown above. The binary variable S
gives the value of the LSB of the sum, and the binary variable C out gives the
output carry. A full-adder can be formed using two half-adder circuits and an
OR gate as shown in the previous page.
TITLE: Study of half subtractor and
full subtractor.
• OBJECTIVE: To realise half subtractor and full subtractor using logic gates.
• APPARATUS: i) Digital trainer board.
ii) Connecting wire.
• HALF-SUBTRACTOR:
The half-subtractor is a combinational circuit which is used to perform
subtraction of two bites. It has two inputs, X (minued) and Y (subtrahend) and
two outputs D (difference) and Bout (borrow out). The logic symbol for a half-
subtractor is shown. The truth table for half subtractor is shown in Table-1.
From the truth table, it is clear that the different output is O if X=Y and 1 if
X=Y; the borrow output Bout is 1 whenever X<Y. If X is less than Y, then
subtraction is done by borrowing 1 from the next higher order it.
From the above equation, the half-subtractor can be implemented using an EX-
OR gate, a NOT gate and a AND gate as show Fig-1.
• FULL-SUBTRACTOR:
A full-subtractor is a combinational circuit that performs subtraction involving
three bits, namely minued bit, subtrahend bit and the borrow from the previous
stage. The logic symbol for full-subtractor is shown in Fig-2.
• CONCLUSION: The original value and practical value are same. The truth
tables are verified and ok.