1 Objective

To design and implement Half and Full Adders.

2 Purpose
Having completed this experiment you will be able to:
• How to construct the basic binary adder, i.e. Half-Adder circuit by using discrete
components as well as on MATLAB
• How to use to Half-Adders to construct a Full-Adder circuit by using discrete
components as well as on MATLAB
• How to construct parallel binary adder in MATLAB

3 Apparatus
• Logic Trainer
• Components (ICs)
– 74LS08
– 74LS86
– 74LS32
• Connecting wires
• MATLAB

4 Theory
4.1 Binary Addition
To build a binary adder of any size it is sufficient to build a unit, which can add two
single bits. Such a circuit is not very complex as there are only three calculations that needs
to be performed, i.e.
0+0=0
0+1=1
1 + 1 = 10
In the third case we encounter a slight complication: A single bit of output does not suffice to
represent the sum of 1 and 1, and we must ”carry” a 1 to the next place. A 1-bit adder,
therefore, must accept two bits of input (the bits to be added) and generate two bits of
output. These two bits can be designated the SUM bit and the CARRY OUT bit.

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4.1.1 Half Adder Circuit
Half Adder is a combinational logic circuit that generates the sum of two single-bit
binary numbers. The logic circuit has two inputs A and B and two outputs i.e. Sum and
Carry abbreviated as SHA and CHA respectively. The functionality of this truth table can
be described by the following two Boolean equations for Sum and Carry as shown below:

S = −−−−−−−−−−−−−
C = −−−−−−−−−−−−−
The implementation of half adder boolean functions is shown in Fig. 1. Although the
Half-Adder circuit is very basic and simple, but it is the first stage in the design of any
n-bit adder circuit.

4.1.2 Full Adder Circuit

As can be seen from the operation of Half-Adder, even the addition of two single-bit
numbers may generate a carry. This implies that the circuit, which is going to perform
addition on the next higher bits, must take into account the carry from the previous stage.
Thus in order to built n-bit adders, we require a modification in the Half-Adder circuit that
can accept three inputs rather than two, i.e. two bits to be added and the carry from the
previous stage. Such a circuit is called a Full-Adder. In this table, x and y represent the
two bits to be added and z is the carry from the previous stage. The Boolean expressions
for the two outputs, after algebraic simplification, are given below.

S = −−−−−−−−−−−−−−−
C = −−−−−−−−−−−−−−−
Figure 2 shows an implementation of full adder boolean functions. Especially note that how
two Half-Adders are used to implement a Full-Adder.

4.1.3 Procedure
• Connect the Logic Trainer to 220V AC power supply.
• Turn On the trainer and verify its DC voltage, it should be +5 volts exactly.
• Install the IC 7408 and 7486 on the trainers breadboard.
• Connect the +VCC (pin 14) and Ground (pin 7) pins of the IC to +5V and Ground
supply of the trainer board.
• Make the appropriate circuit connections as shown in Fig. 1. Use the trainers logic
switches to provide 0 and 1 at the input and use the trainers LEDs to display the
outputs. Note that there are more than one gates in each IC chip, so you can use any
one of these gates to make your connections for the pin numbers corresponding to
each gate in that particular chip.
• Apply inputs to the circuit and record corresponding values of outputs in Table 1.
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 • Now without disconnecting the previous circuit, make another half-adder circuit and
•
connect the two half adders to implement the functionality of a full-adder as shown
in Fig. 2.
• Record your observations in Table 2.

4.2 Experimental Results

4.2.1 Truth Table for Half Adder
Table 1: Truth Table for Half Adder
Inputs Outputs
X Y Cout

0 0
0 1
1 0
1 1

4.2.2 Truth Table for full Adder

Table 2: Truth Table for full Adder
Inputs Outputs
X Y Z Cout

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

5 Exercise: 1
• Design Half Adder in MATLAB and attach results.

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6 Exercise: 2
•• Construct the circuit for binary adder by using full adder circuit in MATLAB and
attach the result.

7 Conclusion:
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