Chapter 11 Frequency Response

EE105 - Spring 2007 ƒ 11.1 General Considerations

Microelectronic Devices and ƒ 11.2 High-Frequency Models of Transistors
Circuits ƒ 11.3 Frequency Response of CS Stages
ƒ 11.4 Frequency Response of CG Stages
ƒ 11.5 Frequency Response of Followers
Lecture 9
Frequency Response ƒ 11.6 Frequency Response of Cascode Stage
ƒ 11.7 Frequency Response of Differential Pairs

High Frequency Roll-off of Amplifier Gain Roll-off Thru CL

⎛ 1 ⎞
− g mVin ⎜ RD || ⎟ = Vout
⎝ CL s ⎠

ƒ The capacitive load, CL, is the culprit for gain roll-off

ƒ As frequency of operation increases, the gain of since at high frequency, it will “steal” away some signal
amplifier decreases. This chapter analyzes this current and shunt it to ground.
problem.
3 4
 Frequency Response of the CS Stage Example: Figure of Merit

Vout g m RD 1
= F .O.M . =
Vin RD2 CL2ω 2 + 1 VT VCC CL

ƒ This metric quantifies a circuit’s gain, bandwidth, and

ƒ At low frequency, the capacitor is effectively open and the gain is
flat. As frequency increases, the capacitor tends to a short and power dissipation. In the bipolar case, low temperature,
the gain starts to decrease. A special frequency is ω=1/(RDCL), supply, and load capacitance mark a superior figure of
where the gain drops by 3dB. merit.
5 6

Bode Plot Example: Bode Plot

⎛ s ⎞⎛ s ⎞
⎜1 + ⎟ ⎜1 + ⎟L
ω ω
H ( s ) = A0 ⎝ z1 ⎠ ⎝ z2 ⎠

⎛ s ⎞⎛ s ⎞
⎜⎜1 + ⎟⎟ ⎜⎜ 1 + ⎟⎟L
⎝ ω p1 ⎠⎝ ω p 2 ⎠

1
ƒ When we hit a zero, ωzj, the Bode magnitude rises with ω p1 =
a slope of +20dB/dec. RD CL
ƒ When we hit a pole, ωpj, the Bode magnitude falls with a ƒ The circuit only has one pole (no zero) at 1/(RDCL), so
slope of -20dB/dec the slope drops from 0 to -20dB/dec as we pass ωp1.
7 8
 Pole Identification Example I Pole Identification Example II

1
1 1 ω p1 = 1
ω p1 = ωp2 = ⎛ 1 ⎞ ω p2 =
RS Cin RD CL ⎜ RS || ⎟ Cin RD CL
⎝ g m ⎠

9 10

Circuit with Floating Capacitor Miller’s Theorem

ZF ZF
ƒ The pole of a circuit is computed by finding the effective Z1 = Z2 =
resistance and capacitance from a node to GROUND. 1 − Av 1 − 1/ Av
ƒ The circuit above creates a problem since neither ƒ If Av is the gain from node 1 to 2, then a floating
terminal of CF is grounded. impedance ZF can be converted to two grounded
impedances Z1 and Z2.
11 12
 Miller Multiplication Example: Miller Theorem

1 1
ƒ With Miller’s theorem, we can separate the floating ωin = ωout =
capacitor. However, the input capacitor is larger than RS (1 + g m RD ) CF ⎛ 1 ⎞
RD ⎜1 + ⎟ CF
the original floating capacitor. We call this Miller ⎝ g m RD ⎠
multiplication.
13 14

MOS Intrinsic Capacitances Gate Oxide Capacitance Partition and Full Model

ƒ The gate oxide capacitance is often partitioned between

ƒ For a MOS, there exist oxide capacitance from gate to
source and drain. In saturation, C2 ~ Cgate, and C1 ~ 0.
channel, junction capacitances from source/drain to
They are in parallel with the overlap capacitance to form
substrate, and overlap capacitance from gate to
CGS and CGD.
source/drain.
15 16
Example: Capacitance Identification Transit Frequency

gm gm
2π fT = 2π fT =
Cπ CGS
ƒ Transit frequency, fT, is defined as the frequency where
the current gain from input to output drops to 1.
17 18

Unified Model for CE and CS Stages Unified Model Using Miller’s Theorem

19 20
 Direct Analysis of CE and CS Stages Example: CE and CS Direct Analysis

gm
| ω z |=
C XY
1
| ω p1 |=
(1 + g m RL ) C XY RThev + RThevCin + RL ( C XY + Cout )
| ω p 2 |=
(1 + g m RL ) C XY RThev + RThevCin + RL ( C XY + Cout ) 1
RThev RL ( CinC XY + Cout C XY + CinCout ) ω p1 ≈
⎡⎣1 + g m1 ( rO1 || rO 2 ) ⎤⎦ C XY RS + RS Cin + ( rO1 || rO 2 ) (C XY + Cout )

⎡1 + g m1 ( rO1 || rO 2 ) ⎤⎦ C XY RS + RS Cin + ( rO1 || rO 2 ) (C XY + Cout )

ƒ Direct analysis yields different pole locations and an ωp2 ≈ ⎣
RS ( rO1 || rO 2 )( CinC XY +Cout C XY + CinCout )
extra zero.
21 22

Input Impedance of CE and CS Stages Frequency Response of CG Stage

1
ω p, X =
⎛ 1 ⎞
⎜ S
R || ⎟ CX
⎝ gm ⎠
C X = CGS + CSB

1
ω p ,Y =
RDCY
rO = ∞ CY = CGD + CDB
1 1
Zin ≈ || rπ Zin ≈
⎡⎣Cπ + (1+ gmRC ) Cμ ⎤⎦ s ⎡⎣CGS + (1+ gmRD ) CGD ⎤⎦ s ƒ Similar to a CB stage, the input pole is on the order of
fT, so rarely a speed bottleneck.
23 24
 Example: CG Stage Pole Identification Emitter and Source Followers

1 1
ƒ The following will discuss the frequency response of
ω p, X = ω p ,Y = emitter and source followers using direct analysis.
⎛ 1 ⎞ 1
( CDB1 + CGD1 + CGS 2 + CDB 2 )
⎜ RS || ⎟ ( CSB1 + CGS 1 )
⎝ g m1 ⎠ gm2 ƒ Emitter follower is treated first and source follower is
derived easily by allowing rπ to go to infinity.
25 26

Direct Analysis of Source Follower Stage Example: Source Follower

C GS
1+ s
Vout gm
= 2
Vin as + bs + 1

RS
CGS
1+s a= ( CGDCGS + CGDCSB + CGS CSB ) a=
RS
[C GD1C GS 1 + (C GD1 + C GS 1 )(C SB1 + C GD 2 + C DB 2 ) ]
Vout gm gm g m1
= C + CSB C + C SB 1 + C GD 2 + C DB 2
Vin as 2 + bs + 1 b = RS CGD + GD b = R S C GD 1 + GD 1
g m1
gm
27 28
 Input Capacitance of Emitter/Source Follower Example: Source Follower Input Capacitance

rO = ∞

Cπ CGS 1
Cin = Cμ + Cin = CGD + Cin = CGD1 + CGS 1
1 + g m RL 1 + g m RL 1 + g m1 ( rO1 || rO 2 )

29 30

Output Impedance of Source Follower Active Inductor

VX RS CGS s + 1 ƒ The plot above shows the output impedance of emitter and
= source followers. Since a follower’s primary duty is to lower the
I X CGS s + g m driving impedance (RS>1/gm), the “active inductor” characteristic
on the right is usually observed.
31 32
 Example: Output Impedance Frequency Response of Cascode Stage

rO = ∞

− g m1
VX ( rO1 || rO 2 ) CGS 3 s + 1 Av , XY = ≈ −1 C x ≈ 2C XY
= gm2
IX CGS 3 s + g m 3 ƒ For cascode stages, there are three poles and Miller
multiplication is smaller than in the CE/CS stage.
33 34

Poles of MOS Cascode MOS Cascode Example

1
ω p,X = 1 ω p,X =
1
1
⎡ ⎛ g ⎞ ⎤ ω p , out = ⎡ ⎛ ⎞ ⎤ ω p , out =
R L ( C DB 2 + C GD 2 ) R L ( C DB 2 + C GD 2 )
g
R S ⎢ C GS 1 + ⎜ 1 + m 1 ⎟ C GD 1 ⎥ R S ⎢ C GS 1 + ⎜ 1 + m1 ⎟ C GD 1 ⎥
⎣ ⎝ g m2 ⎠ ⎦ ⎣ ⎝ g m2 ⎠ ⎦

1
ω p ,Y =
1 ⎡ ⎛ gm2 ⎞ ⎤ 1
⎢ C DB1 + C GS 2 + ⎜ 1 + ⎟ C GD1 ⎥ ω p ,Y =
gm2 ⎣ ⎝ g m1 ⎠ ⎦ 1 ⎡ ⎛ gm2 ⎞ ⎤
⎢ C DB1 + C GS 2 + ⎜ 1 + ⎟ C GD1 + C GD 3 + C DB 3 ⎥
gm2 ⎣ ⎝ g m1 ⎠ ⎦
35 36
 I/O Impedance of MOS Cascode MOS Differential Pair Frequency Response

1
Z in = Z out = RL ||
1
⎡ ⎛ g m1 ⎞ ⎤ ( CGD 2 + CDB 2 ) s ƒ Since MOS differential pair can be analyzed using half-
⎢CGS 1 + ⎜1 + ⎟ CGD1 ⎥ s
⎣ ⎝ gm2 ⎠ ⎦ circuit, its transfer function, I/O impedances, locations
of poles/zeros are the same as that of the half circuit’s.
37 38

Example: MOS Differential Pair

1
ω p, X =
RS [CGS 1 + (1 + g m1 / g m 3 )CGD1 ]
1
ω p ,Y =
1 ⎡ ⎛ g m3 ⎞ ⎤
⎢ C DB1 + CGS 3 + ⎜ 1 + ⎟ CGD1 ⎥
gm3 ⎣ ⎝ g m1 ⎠ ⎦
1
ω p ,out =
RL ( C DB 3 + CGD 3 )

39