UNIT-1

1.Convert the following

a) (248.67)10 = ()8
b) (11011.1101)2 = ()10
c) (ADEB.FC)16 = ()8

2. Subtract the following using r-1 ‘s complement

a) (2548.52)10 – (241)10

b) (11010.10)2 – ( 110)2

3.Implement Basic gates and EX-OR gate using NAND gate only
4. Generate Hamming code for the binary message 110010100 using even parity

5. Explain about Binary codes

Classify the codes into five groups:

(i) Weighted Binary codes

(ii) Non-weighted codes

(iii) Error–detecting codes

(iv) Error–correcting codes

(v) Alphanumeric codes.

Weighted Binary Codes

In weighted binary codes, each position of a number represents a specific weight. The bits are multiplied by
the weights indicated; and the sum of these weighted bits gives the equivalent decimal digit.

Non-Weighted Codes

These codes are not positionally weighted. This means that each position within a binary number is not
assigned a fixed value.
Excess-3 codes and Gray codes are examples of non weighted codes.

Gray code (Unit Distance code or Reflective code)

There are applications in which it is desirable to represent numerical as well as other information with a
code that changes in only one bit position from one code word to the next adjacent word. This class of code
is called a unit distance code (UDC). These are sometimes also called as ‘cyclic’, ‘reflective’ or ‘gray’ code.

Error Detecting Codes

For a single bit error detection, the most common way to achieve error detection is by means of a parity bit.

A parity bit is an extra bit (redundant bit) included with a message to make the total number of 1’s
transmitted either odd or even.

ERROR DETECTING AND CORRECTING CODES

1. PARITY CHECKING

2. HAMMING CODE
6. Define IC and draw the pin diagram for the following IC’s 7404,7408,7432
UNIT-2

1. Find the complement of the AB’C+A’BC+ABC

2. Simplify ∑m(0,1,5,7,8,9,10,11,13,15,18,20,21,23,26,28,29,31) Using K-Map

3. Simplify ∑m(0,1,3,7,8,9,11,15) Using Quine McCluskey Method

4. Explain about BCD ADDER circuit in detail

A BCD adder is used to perform the addition of BCD numbers. A BCD digit can have any of the ten
possible four-bit binary representations, that is, 0000, 0001, , 1001, the equivalent of decimal numbers
0, 1, , 9. When we set out to add two BCD digits and we assume that there is an input carry too, the
highest binary number that we can get is the equivalent of decimal number 19 (9 + 9 + 1).
The result 1101 is correct in natural binary number but it is incorrect in 8421 code. Its answer should
have been 00010011 (13). However, to get the correct answer 6 (0110) is added to the incorrect sum, as
it avoids the illegal number 1010 through 1111 of the 8421 code. So when 0110 is added to the
incorrect answer 1101, the correct answer is obtained as follows:
5. Design Full Adder circuit and implement Full Adder using two half adders
Full adder is a combinational circuit that performs the addition of three binary digits.
1. It has three inputs A, B and C and two outputs S and Co produced by addition of three input bits.
Carry output is designated Co just to avoid confusion between with i/p variable C.

Truth Table : The eight possible combinations of three input variables with their respective
outputs is shown. We observe that when all the three inputs are 1, the sum and carry both
outputs,
are 1.
A ‘Full Adder’ can also be implemented using two half adders and an ‘OR’ Gate
6.Explain about Carry Look Ahead Adder Circuit in detail

Let us define two new binary variables:

Pi called CARRY PROPAGATE and

Gi called CARRY GENERATE.

Binary variable Gi is so called as it generates a carry whenever Ai and Bi are ‘1’.

Binary variable Pi is called CARRY PROPAGATE as it is instrumental in propagation of Ci to Ci+1.

CARRY, SUM, CARRY GENERATE and CARRY PROPAGATE parameters are given by the
following expressions:
UNIT-3

1. Design 8X1 MUX logic diagram. Implement ∑m(0,1,3,7,8,9,11,15) using 8X1 MUX
8x1 Multiplexer

Let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We know that 4x1
Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1 Multiplexer has 8 data
inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4x1
Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the
outputs of first stage as inputs and to produce the final output.
We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above
Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.
Implement ∑m(0,1,3,7,8,9,11,15) using 8X1 MUX
Implement of 8:1 mux
Multiplexer (8:1mux)

2. Implement Full Subtractor Using Decoder

Implement a full subtractor circuit with a 3 to 8 line decoder and two OR gates.

Solution: The Boolean expressions for Difference D and Borrow B bits of full subtractor
 3. Design 2-bit digital comparator circuit

A 2-bit digital comparator will compare A1, A0 bits of input A with B1, B0 bits of input B resp. to design this
comparator will use a 4:16 decoder to produce the required output. The truth table for designing the comparator
is as below: