`timescale 1ns / 1ps

`define S0 2'd0
`define S1 2'd1
`define S2 2'd2
`define S3 2'd3

module sublab2(mclk, btn, sw, an, seg);

parameter n = 12500; // 4ms
input mclk; // clock, rst_b
input [0:0] btn; // rst
input [9:0] sw;
output reg [3:0] an;
output [0:6] seg;

reg [1:0] state, n_state;

assign seg = (sw[0] == 1) ? 7'b0000001 :

(sw[1] == 1) ? 7'b1001111 :
(sw[2] == 1) ? 7'b0010010 :
(sw[3] == 1) ? 7'b0000110 :
(sw[4] == 1) ? 7'b1001100 :
(sw[5] == 1) ? 7'b0100100 :
(sw[6] == 1) ? 7'b1100000 :
(sw[7] == 1) ? 7'b0001111 :
(sw[8] == 1) ? 7'b0000000 :
(sw[9] == 1) ? 7'b0000100 :
7'b0000001;

reg [31:0] clock_count;

reg change;

always@(posedge mclk) // generate change signal

begin
if (btn[0])
begin
clock_count <= 32'd0;
change <= 1'b0;
end
else if (clock_count != n)
begin
clock_count <= clock_count + 1'b1;
change <= 1'b0;
end
else
begin
clock_count <= 32'd0;
change <= 1'b1;
end
end

always@(posedge mclk) // sequential part

begin
if (btn[0])
state <= `S0;
else
state <= n_state;
end

always@(state or change) // combinational part

 begin
if (change == 1'b1)
begin
case(state)
`S0: n_state <= `S1;
`S1: n_state <= `S2;
`S2: n_state <= `S3;
`S3: n_state <= `S0;
default: n_state <= `S0;
endcase
end
else
begin
case(state)
`S0: n_state <= `S0;
`S1: n_state <= `S1;
`S2: n_state <= `S2;
`S3: n_state <= `S3;
default: n_state <= `S0;
endcase
end
end

always@(state) // output part

begin
case(state)
`S0: an <= 4'b1110;
`S1: an <= 4'b1101;
`S2: an <= 4'b1011;
`S3: an <= 4'b0111;
default: an <= 4'b1111;

endcase
end

endmodule