13-Mar-21

VLSI I: Lecture #5

Tristate &
Sequential Logics

Outline
 Strong ‘0’ & ‘1’
 Pass Transistors and Transmission Gates
 Non-inverting Buffer
 Tristate
 Restoring and non-restoring Circuit
 Multiplexer (MUX)
 XOR & XNOR
 CMOS Latches & Flip-Flops

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Strong ‘0’ & ‘1’

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Non inverting buffer

Tristates

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Nonrestoring Tristate and circuit

 Transmission gate acts as tristate buffer and
it is a nonrestoring circuit; since, it does not
have VDD and GRD of its own. Hence, if input
is a noisy or otherwise degraded, the output
EN
will receive the same noise.
A Y
 Noise on A is passed on to Y (after several
stages, the noise may degrade the signal
beyond recognition) EN

Tristate Inverter

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Restoring and non Restoring Circuits

 Tristate inverter produces restored output and it is a

restoring circuit since output is actively driven from VDD
and GND.
 Note however that the Tristate buffer
 ignores the conduction complement rule because we want a Z
output

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3 input XOR
For 3 input XOR gates, we can have the HIGH output when odd numbers of inputs
are at HIGH level. So the 3-input OR gate is called as “Odd functioned OR gate”.

3 input XNOR

XNOR operation with more than two inputs is like that. When there are odd
numbers of inputs in high or logical 1 condition, the output will be 0; otherwise, the
output will be 1.

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D Latch
 When CLK = 1, latch is transparent
 Q follows D (a buffer with a Delay)

 When CLK = 0, the latch is opaque

 Q holds its last value independent of D

 a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q

D Latch Design
 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

Old Q
CLK

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D Latch Operation

D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
CLK
CLK
D
Flop

D Q
Q

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D Flip-flop Design
 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

A “negative level-sensitive” latch A “positive level-sensitive” latch

D Flip-flop Operation
Inverted version of D

QM Q
D

CLK = 0

Holds the last value of NOT(D)

QM
D Q

Q -> NOT(NOT(QM))
CLK = 1

CLK

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D Flip-flop Operation Contd.

Race Condition
 Back-to-back flops can
malfunction from clock skew
 Second flip-flop fires Early
 Sees first flip-flop change
and captures its result
 Called hold-time failure or
race condition

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Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
 As long as nonoverlap exceeds clock skew
 Good for safe design
 Industry manages skew more carefully instead

2 1
QM
D Q

2 2 1 1

2 1

1

2

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