Journal of Semiconductors

SEMICONDUCTOR INTEGRATED CIRCUITS You may also like

- An 11-bit ENOB, accuracy-programmable,
A single-channel 10-bit 160 MS/s SAR ADC in 65 and non-calibrating time-mode SAR ADC
Hua Fan, , Xue Han et al.
nm CMOS - High-speed, high-resolution, radiation-
tolerant SAR ADCs for particle physics
experiments
To cite this article: Lu Yuxiao et al 2014 J. Semicond. 35 045009 H. Xu, Y. Zhou, Y. Chiu et al.

- A single channel, 6-bit 230-MS/s

asynchronous SAR ADC based on 2
bits/stage
Xue Han, , Qi Wei et al.
View the article online for updates and enhancements.

This content was downloaded from IP address 223.100.197.29 on 18/04/2023 at 04:50

Vol. 35, No. 4 Journal of Semiconductors April 2014

A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS

Lu Yuxiao(卢宇潇)Ž , Sun Lu(孙麓), Li Zhe(李哲), and Zhou Jianjun(周健军)
Centre for Analog/Radio Frequency Integrated Circuits (CARFIC), Shanghai Jiao Tong University, Shanghai 200240, China

Abstract: This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR)
analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed,
a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay,
and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset
and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track
and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion
ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power
consumption is 9.5 mW and a core die area of 250  200 m2 is occupied.

Key words: SAR ADC; asynchronous clock; SAR logic; Bootstrapped switch
DOI: 10.1088/1674-4926/35/4/045009 EEACC: 2570

1. Introduction ments (sub-arrays) to prevent the rapid exponential increment

SAR ADC has attracted wide attention in moderate speed
and medium resolution applications due to its low power and
minimal-analog features. In recent years, several high speed
techniques have been reported, such as the asynchronous clock
(self-timing)Œ1 3 , redundant bit correction (over-range, sub-
radix)Œ4 6 , 2-bit per cycleŒ2; 7; 8 and the split-capacitor ar-
rayŒ9; 10 .
The asynchronous clock is considered as the foremost sys-
tematic solution for high speed SAR ADC. A traditional N
bit SAR ADC with a sampling frequency fs needs an exter-
nal clock of (N C1)fs , which severely limits its speed; instead,
the asynchronous SAR ADC just needs a clock as slow as fs .
Although the external clock is much slower, the internal con-
version still retains the multifold speed of fs , controlled and
triggered by a self-timed clock. Fortunately, as the process ad-
vances, an internal high speed clock becomes easier to achieve.
Redundant bit correction resembles the idea of a 1.5 bit of
pipelined ADC to make each bit weigh smaller than the sum of
its subsequent bit weights, and the weight difference as redun-
dancy can be used to tolerate error decision, meta-stability, in-
complete DAC settling and power/ground dynamic noiseŒ4; 5 .
However, the tolerance range should be traded off with a maxi-
mum quantization range (full swing input). Besides, the redun-
dant bits need more cycles to finish and require an extra digital
circuit to perform the shift summation.
A 2-bit-per-cycle solution combines the features of flash
and SAR, which uses three parallel comparators to produce 2
bits in one cycle, so the conversion time is spared by almost
half, which is popular for high speed and low resolution archi-
tecture. However, the mismatch between DACs and compara-
tors, and the signal-dependent noises, such as kickback noise
and offset, make it difficult to realize a resolution higher than
8 bitŒ2 .
In order to reduce the DAC settling time, the binary
weighted capacitive array can be split into two or more seg-
of the capacitance. It is not only fast in settling, but also has low
power and is area-efficient. The issue of the split-capacitor ar-
ray is that the segments require a proper-value bridge capacitor
to connect each other. The mismatches between each segment
are mainly caused by the parasitic capacitors and routing of
the bridge capacitor, which turns out to be the nonlinearity of
the entire ADC outputs. The more segments the DAC is sepa-
rated into, the greater the nonlinearity tends to become. For the
extreme case, the C–2C array has a dramatically limited linear-
ity performance, which is difficult for resolutions higher than
7 bŒ10 and demands calibration. The typical split-capacitor ar-
ray has two segments and can achieve 10 b after some fore-
ground calibration and careful layout.
In 2009, a method to reduce the logic delay was introduced,
see Ref. [11]. The comparator results are almost directly fed
to DAC via a MUX, achieving a bit cycle of totally 400 ps.
Unfortunately, the method is not suitable for a generic SAR
ADC as it is designed for a 2-bit-per-cycle structure with 6-bit
resolution. In 2012, a new way to reduce the logic delay was
reportedŒ7 . It is a domino-cell based dynamic register, which
can replace the shift register and DFF to mitigate the loading of
the clock, but the structure is also limited in 2-bit-per-cycle and
low resolution. In this paper, another domino-based (so-called
“window-opening” in this paper) SAR logic is proposed, which
is compatible to arbitrary-resolution with just one third DFFs
compared with the traditional structure, minimizing the clock
load and achieving only a very small latency that the logic has
to add.
In this paper, a single-channel asynchronous 10-bit 160
MS/s SAR ADC is presented in 65 nm CMOS technology with
a 1.2 V VDD also as Vref . A new bootstrapped switch with
a pre-charge phase is utilized to increase the sampling speed
and reduce the bootstrap capacitance. A partial set-and-down
scheme combined with binary-redundancy is employed to keep
the DAC settling speed while maintaining adequate accuracy.
This paper also introduces a new window-opening SAR logic

† Corresponding author. Email: iamluyuxiao@gmail.com

Received 9 September 2013, revised manuscript received 9 October 2013 © 2014 Chinese Institute of Electronics

045009-1
J. Semicond. 2014, 35(4)
Fig. 1. Proposed 10 bit asynchronous SAR ADC architecture.
to minimize the delay from comparator to DAC, which signif-
icantly shortens the bit cycling time.
2. ADC architecture
The architecture of the 10-bit SAR ADC is shown in
Fig. 1. It is made up of a bootstrapped switch with a pre-
charge phase, a split-capacitor DAC, a dynamic comparator, a
window-opening asynchronous SAR logic, a digital error cor-
rection block, an on-chip comparator offset calibration block
and output buffers.
As SAR ADC quantizes a sample through several bit cy-
cles, it is necessary to optimize all the time consumers in one
bit cycle. In order to speed up sampling, a new bootstrapped
switch with pre-charge phase is presented. During the pre-
charge phase between the sample and track phase, the gate of
the bootstrapped switch is tied high to the VDD, which can
boost the opening speed of the switch and save on bootstrap
capacitor area.
The DAC structure is based on a “split-capacitor”, which
increases the DAC settling speed, reduces the input sampling
capacitance, the total area and the switching power. However,
the structure does not adopt the “5MSBsC5LSBs”, but the
“6MSBsC4LSBs” to keep sufficient input capacitance to sup-
press clock feedthrough and maintain acceptable matching. To
quicken DAC settling, a “set-and-down” algorithm as well as
binary-redundancy is adopted. “Set-and-down” is fast, power
efficient and can spare half the capacitance compared to the
traditional typeŒ6 . However, it suffers from the dynamic off-
set variation from the comparator due to the common mode
step-down each cycle. To alleviate the offset problem, this pa-
per proposes a partial set-and-down method, which is able to
set the common mode at an arbitrary appropriate level. Redun-
dancy is also an effective measure for high speed SAR. Since
the ADC is reference free, the VDD and GND serving as ref-
045009-2
Lu Yuxiao et al.
erences will cause each DAC to charge and discharge through
bonding wire thus slow down the settling. The DAC parasitic
resistance and capacitance from routing also brings about extra
delay. What is more, the comparator may make error decisions
due to the thermal noise for small inputs and has to force a
“0” result to deal with the meta-stability. All the above error
sources can be handled by a redundancy scheme, as long as the
error is within the compensation range.
The dynamic comparator is a p-type input folded structure,
which can output detectable results with post-simulated 100 ps
delay for 1 LSB input. To minimize the systematic offset of the
comparator, an on-chip offset calibration is included.
The window-opening SAR logic is introduced to decrease
the logic delay. It is very simple and can effectively eliminate
the unnecessary waiting and cut the logic delay by over two
thirds (from 260 to 80 ps, tested under the same condition)
compared to the traditional prototype.
The digital error correction is used to sum the 12 b coarse
codes to obtain the 10 b output codes.
3. Circuit implementation
3.1. Bootstrapped switch with pre-charge phase
Compared to the traditional bootstrapped switch, the one
with a pre-charge phase in Fig. 2Œ12 can greatly reduce the
bootstrap capacitance while enhancing the operating speed.
Figure 2(b) illustrates the principle. The sample and track phase
are the same as those in the traditional bootstrapped switch, but
the pre-charge phase between hold and track helps tie the gate
of the bootstrap switch to the VDD faster. We know that the
bootstrap voltage drops when the Csw (see Fig. 2(b)) is con-
nected to the bootstrap switch due to the charge redistribution.
Now the parasitic capacitor at the switch gate is pre-charged to
the VDD before the track, the charge redistribution is limited,
J. Semicond. 2014, 35(4)
Fig. 2. (a) Schematic of the new bootstrapped switch with pre-charge
phase and (b) its mechanism diagram.
which results in a much smaller bootstrap capacitor Csw . For
sampling the capacitance of 1.2 pF, the Csw can be 100 fF.
The pre-charge technique in Ref. [12] cannot handle a large
swing because the bootstrap capacitor discharging occurs when
the input signal approaches the VDD. This design proposes an
improved full-swing signal range with no trade-off of area and
speed.
The operation of the proposed bootstrapped switch can be
divided into three phases. As shown in Fig. 2(a), when PreCh
D 1 in the pre-charge phase, node G1 is pre-charged directly
to the VDD via M7 and M8. Meanwhile, M4 and M5 are off
to preserve the charge in CB (stored in the last hold phase and
VCB D VDD). Moreover, the gates of M2 and M3 are tied
high to block X from connecting G1. During the track phase
(Trk D 1), the capacitor CB bootstraps G1 through M2 and the
transmission gates TG1. In the hold phase, G1 is pulled down
to ground via M11 and M12. Simultaneously, M4 and M5 are
on to charge CB to the VDD again.
In contrast to the topology in Ref. [12], the input voltage
swing for the proposed one can reach rail-to-rail without any
charge leakage. This is realized by preventing M5 and M7 from
being inversely turned on. In terms of M5, X and G1 are tied
together (so VGS D 0) by turning on M2 in the track phase. To
045009-3
Lu Yuxiao et al.
Fig. 3. Monte Carlo simulation of the MoM capacitor of 19.7 fF in
200 runs.
keep M2 fully on during tracking, VGS, M2 is designed to stay
VDD through the path of TG2 and CB. As for M7, the methods
are all the same with M5, not to mention again for simplicity.
3.2. Sub-DAC
The split-capacitance sub-DAC adopts the partial set-and-
down algorithm with two redundant bits, which is depicted in
Fig. 1. As mentioned in Section 2, the sub-DAC is separated
into two uneven segments, the 6 bit MSB array and the 4 bit
LSB array. Since the DAC does not consist of a calibration cir-
cuit for simplicity, decreasing the bit number of the LSB array
is necessary to maintain the DAC linearity. To maintain enough
matching accuracy for the 10 bit, the unit capacitance is de-
signed to be 19.7 fF, which is the MoM-type capacitor. Accord-
ing to the Monte Carlo simulation in 200 runs, the variation of
capacitor value C =C is 0.379 LSB in Fig. 3. The value can be
conservative to meet the matching requirements regarding the
routing parasitic capacitance. Furthermore, a larger unit capac-
itance can mitigate the detrimental effect caused by the clock
feedthrough and charge injection when the switch is off to hold
the sample. In terms of process variation, the capacitance pro-
cess corner mainly affects the settling speed; the matching fac-
tor and linearity are not serious problems.
Both of the two sub arrays have one redundancy bit, which
are B5C and B1C, with the bit weights of 32 LSBs and 2 LSBs
respectively. The bit weights of the 12 b redundancy code are
512, 256, 128, 64, 32, 32, 16, 8, 4, 2, 2, 1, and the digital out-
put equals to .16 C 1/ C B9  512 C


C B5  32 C
B5C  32 C


C B1  2 C B1C  2. So the digital code has
an offset of 17 LSB and the DAC output range is “00


0”–
“11


1”, namely, –17 to 1040 LSBs. However, the number of
redundancy bits cannot be large at will. More redundancy also
means more bit cycles within one period, which may cause
meta-stability. Besides, more compensation range should be
traded off with quantization range. For example, the total DAC
output range is 1057 LSBs, but the ADC output codes will
overflow (saturate) if the coarse codes are greater than 1024
LSBs or less than 0, so the effective input signal range is re-
duced to 0 1024/1057Vref D 0 0:969Vref . In this design,
two redundancy bits B1C and B5C are added, and an aggre-
gate error within –17 to 16 LSB can be compensated, which
is a compromise in terms of speed and accuracy. Note that the
compensation effect depends on not only the total bits weights
of the redundancies, but also where they locate. Explicitly, they
can only correct the errors before them; for example, B5C can
J. Semicond. 2014, 35(4)
Fig. 4. The “partial set and down” transient waveforms of the DAC
outputs.
Fig. 6. The comparator clock generator.
compensate the errors that originate from B9 to B5 within the
16 LSB range, and B1C from B9 to B1 within the 2 LSB range.
The high-weight bit is capable of providing a large correction
range while the low-weight bit retains some immunity from er-
rors due to the comparator thermal noise with small inputs. So
both high- and low-weight bits should be included.
The bridge capacitor is supposed to be 16/15C; however,
the actual value is a little larger due to the extra parasitic ca-
pacitance at the LSB array side.
Now, the DAC operation is discussed below. After the in-
put signals are sampled onto the top plates of the two capacitor
arrays, the comparator performs the first comparison. The volt-
age difference of the two DACs will add or subtract Vref /2, de-
pending on the results. Then the second comparison begins and
the logic feeds back the results to the DAC to add or subtract
Vref /4 and so on and so forth. When all the coarse bits are con-
verted, the digital error correction (DEC) logic does the shift
summation to output inerrant codes. The DEC logic is mainly
made up of simple MUXs and full adders, which can perform
the real-time correction at 160 MHz with no difficulty.
As shown in Fig. 1, the B8 of the DAC is passed through a
buffer instead of an inverter. This implementation is called par-
tial set-and-down. Set-and-down requires all the DAC bottom
plates to be set to VDD during sampling. Then the SAR logic
045009-4
Lu Yuxiao et al.
Fig. 5. Dynamic comparator in sub-ADC.
will output “1” to the corresponding inverter to pull down the
voltage to “0” at the bottom plates. Thus the changing direc-
tion of the DAC voltages is all the way down, and the falling
common mode causes a dynamic comparator offset error. The
partial set-and-down method just picks some bits to change
the DAC voltage direction to upward. In this design, the B8
is the chosen for the common mode to finally settle to 300
mV and the variation range is thereby cut by half, as shown
in Fig. 4.
3.3. Dynamic comparator
The dynamic comparator is a single-stage folded structure
with a p-type input, as shown in Fig. 5. When CLK is low, the
inner latch outputs tn and tp are tied high and comparator out-
puts CMP_OP and CMP_ON are low. When CLK rises up, the
latch begins to regenerate. To reduce the time of regeneration,
the input pair is designed to be large enough, while the PMOS
of the latch is small and the NMOS of the latch is big to accel-
erate the discharge. As the comparator has no preamplifier, the
kickback noise could be serious, so a neutralization technique
is used.
The comparator clock generator is a self-reset topology.
Its schematic and timing diagram are shown in Fig. 6. When
SAMP is high, the switch MN3 ties the clock CMP_CLK
J. Semicond. 2014, 35(4) Lu Yuxiao et al.

Fig. 7. Schematic of the traditional SAR logic.

Fig. 8. Schematic of the proposed SAR logic.

low, resetting the comparator. As long as SAMP falls, the
switch MP1 is on to pull CMP_CLK high and enables the com-
parator. After the regeneration, either CMP_OP or CMP_ON
rises up, pulling down CMP_CLK on its own. The compara-
tor is thereby reset and gets ready for the next bit earlier. Note
that MP1 should be off after CMP_CLK rises up and before
CMP_OP or CMP_ON goes high to avoid short circuiting, so
CMP_CLK_DEL0 as a short delay of CMP_CLK is to make
it and guarantee CMP_CLK to be fully pulled to the VDD be-
fore MP1 shuts down itself. When the comparator finishes re-
generation, CMP_CLK becomes low, resetting the comparator.
Then, after a variable delay, which comprises the logic propa-
gation and the DAC settling, CMP_CLK_DEL1 begins to fall
to turn on MP1 again, restarting the second comparison.
To reduce the systematic offset mainly caused by the para-
sitic capacitive mismatch, an auxiliary differential pair OSN
and OSP is added for offset calibration. The size of the pair is
1/8th of the main input pair to increase the accuracy and the im-
munity of the kickback noise. Since the input voltage range can
be almost full-scale, the calibration range can achieve 100 mV,
and the step can be 1/6 LSB. The OSN and OSP input is pro-
vided by an 8 bit auxiliary DAC. When the offset calibration
begins, EN_Cali D 1, the bootstrapped switch is off and both
the main DAC outputs are connected to VCM . Then the com-
parator detects the offset and quantizes it like normal SAR
ADC with the auxiliary logic and DAC. Note that the quan-
tization results for the offset should be updated in each sample
phase before the next conversion.

045009-5
J. Semicond. 2014, 35(4) Lu Yuxiao et al.

Fig. 10. Comparison of the (a) logic delay between traditional SAR
ADC and (b) the proposed SAR ADC.

Fig. 9. Timing diagram of the principle of the window-opening con-

cept.

3.4. Window-opening SAR logic

The traditional SAR logic consists of a shift register and a
DAC register (seen in Fig. 7). The DAC register serves to set
the comparator results to DAC one-bit-a-cycle clocked by the
shift register. The shift register is triggered by the ready flag,
CMP_RDY from the comparator. The traditional logic delay is

Tlogic;trad D TCMP_RDY C TDFF;SHIFT C TDFF;DAC C Tbuf ; (1)

where TCMP_RDY is the OR gate delay from the CMP_RDY gen-

eration, TDFF;SHIFT and TDFF;DAC are delays from the shift re-
gister and the DAC register respectively, and Tbuf is the delay
caused by the driving buffers for the DAC.
Unlike the structure of the traditional logic, the proposed Fig. 11. The schematics of the window generator and the latch output
SAR logic circuit consists of N window generators and N latch block.
blocks, as shown in Fig. 8. Figure 9 illustrate the whole opera-
tion. The bit cycling begins immediately after sampling. When
The main advantages of the window-opening concept
the inverted sample clock, SAMP_B, is input to the first win-
are as follows. Firstly, it effectively reduces the load of
dow generator, the MSB window opens and the MSB latch
CMP_RDY. CMP_RDY has a capacitive load of N DFFs
block is enabled to wait for the comparator result. On the arrival
in the traditional approach, while in the proposed method,
of the result, the latch block passes it to DAC through a tiny-
CMP_RDY sees just one DFF and N 1 cut-off switches.
delay latch block. Once the comparison is finished, CMP_RDY
The load reduction helps decrease the OR delay and dynamic
falls down and its negative edge is detected to close the MSB
power consumption. Secondly, as soon as the comparator re-
window and open the MSB-1 window simultaneously. Then
sult arrives, the latch block passes it to DAC with no delays
the MSB latch block is locked and stores the results until
from the OR gate, the shift register or the DAC register. To put
the next sample phase. Meanwhile, the MSB-1 latch block is
it another way, the OR gate and the DFFs are placed aside from
opened to receive the second comparator results. In such a way,
the critical path. Thirdly, a small latch block is placed to sub-
N bit cycling completes serially. In other words, a shifting win-
stitute two fast DAC DFFs in the traditional structure, saving
dow here substitutes the shifting clock edge in traditional SAR
power and area. The total area of SAR logic is 35  70 m2 .
logic to conduct the successive approximation process. There-
fore, the proposed SAR logic delay is:
4. Experimental results
Tlogic;prop D Tlatch C Tbuf ; (2)
The proposed 10-bit ADC is fabricated in a 1P6M 65 nm
where Tlatch is the delay from the latch output block and Tbuf is CMOS process with a 1.2 V supply. The die micrograph is
the same as in Eq. (1). demonstrated in Fig. 12. Each block is enclosed by the white
The comparison of the logic delay is depicted in Fig. 10; frames. The measured SFDR is 65 dB and SNDR is 52.9
the schematics of the window generator and the latch output dB when a 30.1 MHz input signal is sampled at 160 MS/s,
block are depicted in Fig. 11. as shown in Fig. 13. Sweeps of the inputs at frequencies of

045009-6
J. Semicond. 2014, 35(4) Lu Yuxiao et al.

Fig. 12. Die micrograph.

Fig. 15. Measured DNL and INL with 30.1 MHz input clocked at 30
MHz (1.28  105 points).

Table 1. Performance summary.

Parameter Value
Process 65 nm 1P6M CMOS
Power supply 1.2 V
Sampling rate 160 MS/s
Resolution 10 bit
ENOB 8.5
Full scale input 2 Vp p
Fig. 13. Measured 1.28  105 points FFT sampling a 30.1 MHz input DNL 0:47/C1.66 LSB
at 160 MS/s. INL 1:06/C1.18 LSB
SFDR (fin D 30.1 MHz) 65 dB
SNDR (fin D 30.1 MHz) 52.9 dB
Core die area 225  200 m2
Power consumption 9.5 mW

Fig. 14. Measured SFDR and SNDR at 160 MS/s versus input fre-
quency.
30.1 MHz, 50.1 MHz and 100.1 MHz, and the SFDRs and
SNDRs, are shown in Fig. 14, which reveals that the SNDR
and SFDR are larger than 50 dB and 55 dB respectively when
the input signal is up to 100 MHz. The DNL is 0:47/C1.66
LSB and the INL is 1:06/C1.18 LSB, according to Fig. 15.
The static linearity results are not very good, mainly because
the layout of the DAC has mismatches between the total bit
weights of the LSB array and the LSB of the MSB array, and
no DAC calibration is included. Chip performance is summa-
rized in Table 1. Table 2 compares this work with three 10-bit
SAR based ADCs and an 8-bit SAR ADC prototype.
5. Conclusions
A 10-bit 160 MS/s single-channel asynchronous SAR
ADC in 65 nm CMOS is presented. A partial set-and-down
DAC with a two redundant bits structure helps the DAC settle
fast and relieves the comparator offset problem. The compara-
tor clock generator is a self-reset topology, which can reset the
comparator as soon as the regeneration completes, increasing
the high speed ability. The window-opening SAR logic, adopt-
ing the domino-cell idea, is able to pass the results within just
one latch delay, which is also very power- and area-efficient.
The results of the experiment indicate that the ADC achieves
the SNDR of 52.9 dB and SFDR of 65 dB while consuming
9.5 mW power. The chip area is 250  200 m2 .
References
[1] Kull L, Toifl T, Schmatz M, et al. A 3.1 mW 8 b 1.2 GS/s
single-channel asynchronous SAR ADC with alternate compara-
tors for enhanced speed in 32 nm digital SOI CMOS. IEEE In-
ternational Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2013: 468
[2] Lien Y C. A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous sub-
ranged SAR ADC in 28-nm CMOS technology. Symposium on
VLSI Circuits (VLSIC), 2012: 88

045009-7
J. Semicond. 2014, 35(4) Lu Yuxiao et al.

Table 2. Performance comparison.

Parameter ISSCC07’Œ13 CICC10’Œ14 JSSC12’Œ15 ISSCC13’Œ1 JOS13’Œ16 This work
Process (nm) 90 65 65 32(SOI) 65 65
Architecture Subrange Pipelined SAR Pipelined SAR Single-channel Single-channel Single-channel
SAR SAR SAR
Supply voltage (V) 1 1 1.1 1.1 1.0 1.2
Sampling rate (MS/s) 160 204 160 1300 80 160
Resolution (bit) 10 10 10 8 10 10
ENOB (bit) 9.15 8.87 8.91 6.24 7.73 8.5
DNL/INL (LSB) N/A 0.74/0.9 0.46/1.7 0.91/0.79 1.3/2.2 1.66/1.18
SFDR/SNDR (dB) 75/57 @ 63.5/55.2 @ 61.3/55.4 @ 49.83/39.3 @ 64.6/48.3 @ 65/52 @
10 MHz input 2.4 MHz input 1.5 MHz input 477 MHz input 10 MH input 30 MHz input
Power (mW) 84 9.15 2.72 4.2 1.6 9.5
FOM (fJ/conv-step) 956 120 50 43 94.8 164
Area (m2 / 1000  420 850  260 500  420 70  22 0.13 mm2 225  200

[3] Tao J, Wing L, Zhong F Y, et al. A single-channel, 1.25-GS/s,
6-bit, 6.08-mW asynchronous successive-approximation ADC
with improved feedback delay in 40-nm CMOS. IEEE J Solid-
State Circuits, 2012, 47(10): 2444
[4] Liu C C, Chang S J, Huang G Y, et al. A 10 b 100 MS/s 1.13 mW
SAR ADC with binary-scaled error compensation. IEEE Interna-
tional Solid-State Circuits Conference Digest of Technical Papers
(ISSCC), 2010: 386
[5] Kuttner F. A 1.2 V 10 b 20 MSample/s non-binary successive ap-
proximation ADC in 0.13 m CMOS. IEEE International Solid-
State Circuits Conference (ISSCC), 2002, 1: 176
[6] Liu W, Huang P, Chiu Y. A 12 b 22.5/45 MS/s 3.0 mW 0.059
mm2 CMOS SAR ADC achieving over 90 dB SFDR. IEEE In-
ternational Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2010: 380
[7] Hong H K, Kim W, Park S J, et al. A 7 b 1 GS/s 7.2 mW nonbinary
2 b/cycle SAR ADC with register-to-DAC direct control. IEEE
Custom Integrated Circuits Conference (CICC), 2012: 1
[8] Wei H, Chan C H, Chio U F, et al. An 8-b 400-MS/s 2-b-per-
cycle SAR ADC with resistive DAC. IEEE J Solid-State Circuits,
2012, 47(11): 2763
[9] Saberi M, Lotfi R. Segmented architecture for successive ap-
proximation analog-to-digital converters. IEEE Trans Very Large
Scale Integration (VLSI) Systems, 2013, PP(99): 1
[10] Alpman E, Lakdawala H, Carley L R, et al. A 1.1 V 50 mW 2.5
GS/s 7 b time-interleaved C-2C SAR ADC in 45 nm LP digital
CMOS. IEEE International Solid-State Circuits Conference Di-
gest of Technical Papers, 2009: 76, 77a
[11] Cao Z, Yan S, Li Y. A 32 mW 1.25 GS/s 6 b 2 b/step SAR ADC
in 0.13 m CMOS. IEEE International Solid-State Circuits Con-
ference Digest of Technical Papers, 2008: 542.
[12] Doris K, Janssen E, Nani C, et al. A 480 mW 2.6 GS/s 10 b time-
interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm
CMOS. IEEE J Solid-State Circuits, 2011, 46(12): 2821
[13] Huber D J, Chandler R J, Abidi A A. A 10 b 160 MS/s 84 mW 1
V subranging ADC in 90 nm CMOS. IEEE International Solid-
State Circuits Conference Digest of Technical Papers (ISSCC),
2007: 454
[14] Jeon Y D, Cho Y K, Nam J W, et al. A 9.15 mW 0.22 mm2 10 b
204 MS/s pipelined SAR ADC in 65 nm CMOS. IEEE Custom
Integrated Circuits Conference (CICC), 2010: 1
[15] Zhu Y, Chan C H, Sin S W, et al. A 50-fJ 10-b 160-MS/s
pipelined-SAR ADC decoupled flip-around MDAC and self-
embedded offset cancellation. IEEE J Solid-State Circuits, 2012,
47(11): 2614
[16] Ma Jun, Guo Yawei, Wu Yue, et al. A 1-V 10-bit 80-MS/s 1.6-
mW SAR ADC in 65-nm GP CMOS. Journal of Semiconductors,
2013, 34(8): 085014

045009-8