Ncvlog KPNS

Cadence® NC-Verilog® Simulator Known
Problems and Solutions

Product Version 8.2
November 2008
Updated June 2009

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NC-Verilog Simulator Known Problems and Solutions
Contents
Cadence NC-Verilog Simulator Known Problems and
Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Product: NC-SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Product Level 2: DOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CCR 98155: Makefile.nc does not support .C extension for C++ on IBM . . . . . . 10
Product Level 2: IP_PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CCR 434611: Block and Generate access not supported with portview type IP author
privilege . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CCR 230561: Internal error when Verilog system function call is called with protected
arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CCR 84543: ncsim internals with SDI and protected code . . . . . . . . . . . . . . . . . 11
CCR 82101: VHDL attributes may reveal protected information . . . . . . . . . . . . . 11
CCR 80102: $display system task displays protected instances . . . . . . . . . . . . 11
CCR 79122: Report statement inside protected IP may reveal protected information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Product Level 2: IRUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CCR 543309: Under irun the SPECMAN_PRE_COMMANDS are only seen by
Specman at simulation time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Product Level 2: NCELAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CCR 263256: Changing the timestamp of a file regenerates intermediate files (ASTs
and VSTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CCR 182523: Generated configuration files in hierarchical mode with cyclic
dependency fails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CCR 178499: Generation of configuration file fails for multiple library mapping of same
physical library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CCR 102260: Unable to elaborate large designs on the AIX platform . . . . . . . . . 14
Product Level 2: NCSIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CCR 562592: IUS with Specman may hang on Linux EE5 when the IUS profiler is on
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CCR 485610: NCelab binds with wrong module when multiple choices exist . . . 15
CCR 308902: Built-in function IEEE.std_logic_arith does not report error for integer
overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
June 2009 3 Product Version 8.2

CCR 228237: Incorrect timing and toggle information in the library backward SAIF file
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CCR 209971: Contention time and inertial and transport glitch counts are not
supported for SAIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CCR 58274: EVCD does not dump the initial value information for signals . . . . 16
CCR 57855: Incorrect testbench generated if EVCD is dumped for vector
subelements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CCR 53180: Some objects are not shown in the waveform viewer during interactive
simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CCR 43086: Waveform editing through Tcl on signal objects may result in incorrect
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Product Level 2: NCUPDATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CCR 253768: Updates to cds.lib are ignored if elaboration is performed with -update
switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Product Level 2: OTHER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CCR 485515: 64-bit NC tools fail with snapshots > 2GB on AIX 32-bit kernel . . 18
CCR 235387: Multiple logical names mapping to a physical library errors out when
decompiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CCR 222103: Goto - Cause does not work with dynamic counter-example waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CCR 217136: ncdc does not reproduce cds.lib with IEEE_pure path when required
20
CCR 41339: ncls errors out when different units have the same name in mixed-
language design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Product Level 2: PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CCR 522880: VHDL Event Synchronization with CPF behavior . . . . . . . . . . . . . 21
CCR 406975: Incorrect logging of signals in SimVision data file . . . . . . . . . . . . . 21
Product Level 2: SYSTEMVERILOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CCR 261760: Dynamic arrays are not supported in structs . . . . . . . . . . . . . . . . . 22
Product Level 2: TCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CCR 43502: Difference in behavior with VCD and EVCD dump while using save and
restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CCR 31538: The NC-Sim Tcl expr command behaves differently on an array . . 22
CCR 27140: Line breakpoints deleted erratically when simulation is reset . . . . 23
Product Level 2: VCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CCR 184556: EVCD incorrect for VHDL ports of type OUT, when drivers exist inside
SMART model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Product Level 2: VPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

CCR 485572: ncsim crashes when opening an external process . . . . . . . . . . . . 24

CCR 207862: Restart callback routines cannot be static on Linux . . . . . . . . . . . 24
Product: NC-VERILOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Product Level 2: IP_PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CCR 83680: Out-of-module-references may not work with protected design units
25
CCR 82567: The use of Verilog-2001 features in a protected cell may leak protected
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Product Level 2: NCELAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CCR 485577: 32-bit version of the tool is returning a 64-bit integer . . . . . . . . . . 25
CCR 32763: ncelab errors out if dumpvars including scope is declared within @*
27
CCR 20299: UDP does not get compiled via Design Prep if it is missing instance
name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CCR 8910: Design can elaborate via bindings but via config it fails . . . . . . . . . 27
Product Level 2: NCPREP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CCR 15486: ncprep +redirect+ causes cds.lib to point to incorrect work library
location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Product Level 2: NCSIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CCR 491222: Use of function call in bit-select or indexed part-select of an assign
statement or output port expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CCR 486178: ncverilog shows different strength on a subset of a signal . . . . . . 29
CCR 485711: Default timescale for Verilog-XL and NC-Verilog are different when
recording to database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CCR 485690: NCSIM fails when P-Threads are linked on the Linux platform . . . 30
CCR 485481: $sformat task does not return a value . . . . . . . . . . . . . . . . . . . . . . 30
CCR 186558: $ftell() does not function correctly on Linux . . . . . . . . . . . . . . . . . . 31
CCR 29523: reset/restart commands disable statement trace writing . . . . . . . . 31
CCR 29122: Edge to source may not work with non-blocking assignments . . . . 31
Product Level 2: NCSIM_SHM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CCR 35452: wrapsize option with recordfile does not work with NC-Verilog . . . 32
CCR 30875: Database opened without the -statement option does not have variable
declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Product Level 2: NCSIM_TCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CCR 286582: Tcl force command does not extend 'x' or 'z' values beyond 32 bits .
32
CCR 126155: Describe and driver Tcl commands give value(s) of entire multi-
dimensional array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Product Level 2: NCVLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CCR 201861: Same named file in a new working directory does not force Verilog
recompilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CCR 35056: Verilog-XL and NC-Verilog produce different $dumpports results . 34
Product Level 2: NCXLMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CCR 211760: cds.lib in -y directory causes ncverilog to fail during elaboration . 35
Product Level 2: OTHER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CCR 95733: ncdc will not decompile protected code . . . . . . . . . . . . . . . . . . . . . 35
CCR 17001: pak files do not get updated if you copy an existing library to a new name
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Product Level 2: OVM_LIB_CDNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CCR 620104: XBUS example does not work with -svpp switch . . . . . . . . . . . . . . 36
Product Level 2: PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CCR 257583: Fork/Join style testbench runs very slowly . . . . . . . . . . . . . . . . . . 36
CCR 20740: Slow vpiDriver access in vpi_iterate when const connected to a vector
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Product Level 2: PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CCR 607903: Automatic coverage model not generated on AIX 64-bit platform . 37
CCR 554371: Isolation between power domains not added to SystemVerilog interface
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CCR 418860: Verilog netlist simulation with CPF fails . . . . . . . . . . . . . . . . . . . . . 38
Product Level 2: RANDOMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CCR 484538: Function calls within an inline constraint expression cannot have a
prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CCR 437516: LRM restrictions on functions that are called in constraint expressions
are not fully enforced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Product Level 2: SVPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CCR 454583: svpp does not support parameterized types and specializations in
different scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Product Level 2: SYSTEMVERILOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CCR 341632: Named event probes are inaccurate after SystemVerilog event
assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CCR 270608: Cannot have a member of a struct with bit overflow . . . . . . . . . . . 40
CCR 230533: Scope randomize calls cannot be made from protected Verilog code.
41
CCR 217696: AMS cannot make reference to SystemVerilog constructs or data types.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CCR 190036: The always_comb construct produces unexpected results. . . . . 41

CCR 156103: Interface references are not probed with $shm_probe() . . . . . . . . 42

Product Level 2: TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CCR 183443: Wrong file name may be given for SDF interconnect warning . . . 42
CCR 28372: Multi-source interconnect delay with continuous assign takes the
interconnect path when multiple paths enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CCR 3175: XL/NC difference on register use in timing checks . . . . . . . . . . . . . 43
Product Level 2: URM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CCR 593287: ovm_component constructor must have name and parent arguments in
correct order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Product Level 2: VPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CCR 485672: vpiProtected Boolean property always returns false . . . . . . . . . . . 44
CCR 146114: Stopping and resuming of SHM database in NC-Verilog . . . . . . . 45
CCR 80823: Port information is visible through VPI even if protected . . . . . . . . 45
CCR 50068: The vpi_get_value routine does not return a value for a continuous
assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CCR 28838: Using C++ functions does not create the correct simulator executables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CCR 5826: Restart does not work with SWIFT models . . . . . . . . . . . . . . . . . . . 46
CCR 5825: Reset does not work after a finish command has been processed . 46


Cadence NC-Verilog Simulator Known

Problems and Solutions
Product Version 8.2

November 2008
Updated June 2009
This Known Problems and Solutions document describes important Product Change
Requests (CCRs) for the NC-Verilog simulator and tells you how to solve or work around
these problems.
CCRs that have been filed against another product, such as Verilog-XL or NC-VHDL, may be
included in this document because they also apply to NC-Verilog.
Note: The operating system information included for each CCR usually indicates the platform
on which the problem was first identified. In many cases, the problem is not platform-specific
unless explicitly noted.
Note: The Planned Release information that is included for the CCRs listed in this document
reflects the Cadence estimate, at the time of publishing, of when the resolution will be
incorporated in the product. Communication of this Planned Release information is for
informational purposes only and should not be considered a warranty of any kind. Cadence
reserves the right to alter the planned release at any time without notice.
Updated Known Problems and Solutions documents are published at regular intervals.
Customers can view on SourceLink the most up-to-date information about the status of their
CCRs.

June 2009
Product: NC-SIM
Product Level 2: DOC
CCR 98155: Makefile.nc does not support .C extension for C++ on IBM
OS: AIX Version: 5.1
Description: Makefile.nc in the installation hierarchy does not support the .C extension for
C++ files on IBM even though xlC recommends that this extension be used for C++ files on
IBM.
Solution: Change the file extension from .C to .cc or redefine the CC_EXTENSION macro
to C.
Planned Release: Not currently planned.
Product Level 2: IP_PROTECT
CCR 434611: Block and Generate access not supported with portview
type IP author privilege
OS: ALL Version: ALL
Description: If the design consists of block and generate statements, the portview IP
author privilege may not enable access to objects declared in these blocks.
Solution: The IP should be encrypted using:

■ The pragma to enable/disable the privilege
■ The debugall privilege
CCR 230561: Internal error when Verilog system function call is called
with protected arguments
OS: ALL_UNIX Version: ALL

June 2009
Description: An internal error is generated when a Verilog system function call is called with
protected arguments.
Solution: Do not use Verilog system tasks with ncprotect.
CCR 84543: ncsim internals with SDI and protected code

Description: Running ncsim on a protected module that contains SDI/HDL content crashes
ncsim. The behavior of SDI/HDL system tasks, and other Verilog system tasks, with IP
protection is being defined. The use of system tasks in protected design units may cause
erroneous behavior.
Solution: Avoid using system tasks with protected design units.
CCR 82101: VHDL attributes may reveal protected information

Description: If VHDL attributes, especially predefined VHDL attributes, have been used in
a protected design, these attributes may reveal protected information. For example, the
path_name attribute will reveal the component and instance names of the design units.
Solution: Avoid using predefined attributes in the designs to be protected.
CCR 80102: $display system task displays protected instances

Description: The use of system tasks inside a design that is to be protected may reveal
some of the protected information.
Solution: Avoid using system tasks inside the design to be protected, especially those
system tasks that dump design information, such as $display and $monitor.

June 2009
CCR 79122: Report statement inside protected IP may reveal protected

information
OS: SOLARIS Version: 8
Description: If an IP author has used a report statement in the design and has protected
it using ncprotect, the simulator may reveal some information about the protected objects
through the report statement.
Solution: Avoid using the report statement from the protected IP. If using the report
statement is essential, try not to report objects through the statement.
Product Level 2: IRUN
CCR 543309: Under irun the SPECMAN_PRE_COMMANDS are only seen

by Specman at simulation time
OS: LINUX Version: ALL
Description: The different stages of Specman compilation cannot rely on the

SPECMAN_PRE_COMMANDS evironment variable. If something must be defined during
Specman compilation, the user must use the -snset options instead.
Solution: Because of the different Specman stages that can be invoked under irun,
presetting the env SPECMAN_PRE_COMMANDS has been restricted to passing the
contents of the environment to the simulation stage. You cannot use this environment
variable to affect comilation or the loading of Specman e code. For this you should use the
-snset or -sncompargs options:
irun -snset "config gen -default_generator=IntelliGen" test.e

June 2009
Product Level 2: NCELAB
CCR 263256: Changing the timestamp of a file regenerates intermediate

files (ASTs and VSTs)
Description: AST(s)/VST(s) are redumped for both VHDL and Verilog when the timestamps
are modified. However, COD/SIG files are retained for both languages across different hotfix
releases. The ASTs/VSTs should be regenerated only if the checksum differs (that is, if the
content of the source file has changed). In case of timestamp change, ASTs should be
retained.
Solution: Avoid operations like copy and move of any unmodified files to avoid regeneration
of ASTs and VSTs.
CCR 182523: Generated configuration files in hierarchical mode with

cyclic dependency fails
Description: Using the -confhier option to generate hierarchical configuration files may
result in a situation in which the generated configuration files cannot be compiled. This
happens if there is a cyclic dependency in the files.
For example, suppose that you have a design that contains three entities: top, mid, and
bottom, such that top instantiates mid, and mid instantiates bottom. Let there be two
libraries in the design into which these entities get compiled: lib1 and lib2. Entities top
and bottom are compiled into lib1, and middle is compiled into lib2.
If you then use the -confhier option to generate configuration files for this design, the
generated files, lib1_conf.vhd and lib2_conf.vhd will not compile.
The reason is that lib1_conf.vhd must be compiled in lib1, and lib2_conf.vhd must
be compiled in lib2. Moreover, to compile the generated configuration for entity mid
(cfg_mid_arch), the configuration for bottom (cfg_bottom_arch) must already have
been compiled. But, cfg_bottom_arch is in file lib1_conf.vhd, which needs to be
compiled in lib1, but cannot be compiled because it is dependent on mid, which is in turn
dependent on bottom. Hence, neither of the generated files will compile.

June 2009
Solution: To avoid this circular dependency problem, use the -confflat option to
generate a flat configuration file.
CCR 178499: Generation of configuration file fails for multiple library

mapping of same physical library
Description: The configuration file generator (invoked with ncelab -conffile)

generates errors when multiple logical libraries are mapped to the same physical library.
Solution: None.
CCR 102260: Unable to elaborate large designs on the AIX platform

OS: AIX Version: ALL
Description: On the AIX platform, it may not be possible to elaborate large designs using
the 32-bit version of the tools. This can happen when the elaborator needs more than
2Gbytes of available User Data memory. The maximum size that the NC tools can use on this
platform is 2Gbytes.
Solution: Cadence is aware of the issue and the solution suggested by IBM (involving the
use of shared memory) will require significant changes in our memory
allocation/management code. As an alternative, the IUS 5.3 and later versions of the tools
can be run in 64-bit mode, which does not have the 2Gbyte limit.
Product Level 2: NCSIM
CCR 562592: IUS with Specman may hang on Linux EE5 when the IUS
profiler is on
OS: LINUX Version: RHEL5.0_64

June 2009
Description: If a design is simulated along with the Specman environment, and the IUS
profiler is on (that is, the -profile option is used), then the simulation may hang on the RHEL
5.0, 5.1, and 5.2 platforms.
Solution: Simulate the design without the IUS profiler on RHEL 5.0, 5.1 ,and 5.2 platforms.
If a profile is required for the design under simulation, please use RHEL4, or RHEL5.3.
Planned Release: IUS8.1-S
CCR 485610: NCelab binds with wrong module when multiple choices
exist
OS: LINUX Version: REDHAT7.2
Description: In some circumstances where multiple libraries contain modules that have the
same name, the elaborator may bind to the module that you do not want it to bind to.
Solution: Rename the modules so that they have unique names.
In addition, please report the problem to Cadence along with a test case.
CCR 308902: Built-in function IEEE.std_logic_arith does not report error

for integer overflow
Description: The function std_logic_arith in IEEE package, does not work correctly for
integer overflow. A warning is generated instead of an error. If you compile with the ncvhdl
-nobuiltin command-line option, the error is correctly reported during simulation.
However, the behavior of the function should not differ when compiled with or without the
-nobuiltin switch.
Solution: Use the -nobuiltin option during compilation.

June 2009
CCR 228237: Incorrect timing and toggle information in the library

backward SAIF file
Description: The library backward SAIF file shows incorrect dump for timing and toggle
attributes for certain conditions.
Solution: None.
CCR 209971: Contention time and inertial and transport glitch counts are
not supported for SAIF
Description: Contention time TB and inertial and transport glitch counts (TG, IG, and IK)
are currently not supported for SAIF.
Solution: None.
CCR 58274: EVCD does not dump the initial value information for signals
Description: The EVCD standard does not include the dumping of initial values of the
signals being probed. The format defines the dumping of the changed values from the default
initial values.
Solution: If it is critical to have the initial values recorded (for example, if you are using the
ncgentb utility to generate a testbench), use assignments at time #0 to create initial values.
CCR 57855: Incorrect testbench generated if EVCD is dumped for vector

subelements

June 2009
Description: If you dump EVCD for subelements of a vector port, and then generate a
testbench using the ncgentb utility, the generated testbench fails to combine these
subelements into a single vector. This results in incorrect testbench generation.
Solution: Do not generate EVCD files for subelements of a vector port. When EVCD for an
array has to be created, dump the complete vector.
CCR 53180: Some objects are not shown in the waveform viewer during
interactive simulation
Description: In some instances, adding vector objects to the waveform viewer during an
interactive simulation results in a "???" being displayed rather than the value of the object.
This is a problem involving the use of hexadecimal notation in bit-string assignments.
Solution: The problem can be resolved by elaborating the design using the ncelab
-expand command-line option.
CCR 43086: Waveform editing through Tcl on signal objects may result
in incorrect output
Description: This problem occurs when the signal in question satisfies the following
conditions:
■ The signal is assigned an expression with zero delay in VHDL, and has a waveform
deposited through Tcl.
■ The expression is another signal name which has a waveform in a different process.
The problem happens because the zero delay assignment in VHDL does not take into
consideration waveform editing due to waveforms deposited through Tcl. This problem exists
in both vectorized and non-vectorized cases.
This is not a very common scenario and the behavior is correct in all other situations.
Solution: None.

June 2009
Product Level 2: NCUPDATE
CCR 253768: Updates to cds.lib are ignored if elaboration is performed

with -update switch
Description: The elaborator does not detect changes to the cds.lib file. For example, if
you change the physical mapping for a work library and then reinvoke the elaborator with
ncelab -update, the elaborator cannot detect and take into account these changes.
Moreover, if the argument passed to the -cdslib switch is changed, the elaborator
regenerates the snapshot, but does not reflect the latest changes.
Solution: The only workaround is to recompile the design if the cds.lib file has been
modified.
Product Level 2: OTHER
CCR 485515: 64-bit NC tools fail with snapshots > 2GB on AIX 32-bit
kernel
OS: AIX Version: 5.1
Description: 64-bit NC tools (ncelab/ncsim) fail when reading/writing large snapshots

(greater than 2GB) on 32-bit kernel AIX machine. This happens even on systems that have
large file support (LFS) enabled (that is, the file system supports file sizes beyond 2GB).
ncelab fails with the following message when writing snapshots that are greater than 2GB:
ncelab: *E,DLWRTF: Write of intermediate file for snapshot worklib.test:behave
(SSS) failed (Invalid argument).
ncsim fails with the following message when reading snapshots that are greater than 2GB:
ncsim: *E,DLREAD: Intermediate file for snapshot worklib.monster_eprom_test_conf
ig:configuration (SSS) is corrupt (truncated?).

June 2009
Solution: The AIX 32-bit kernel architecture does not support file read and write beyond
2GB in one read/write system call. If ncelab and ncsim fail with the errors shown above, use
a 64-bit kernel AIX machine to run designs that read/write simulation snapshots greater that
2GB.
CCR 235387: Multiple logical names mapping to a physical library errors

out when decompiling
Description: If multiple logical names are mapped to a single physical library in the
cds.lib file, the decompiler errors out upon reference to any logical library name other than
the first logical name.
For example, in the cds.lib file, multiple logical names are mapped to a physical library as
follows:
DEFINE lib1 ./work
DEFINE lib2 ./work
DEFINE lib3 ./work
The decompiler will only contain lib1 in the cds.lib file that it creates. This is because the
decompiler has no information on the aliases lib2 and lib3, and will error out on reference
to any of the two.
Solution: Avoid using multiple logical names in the cds.lib.
CCR 222103: Goto - Cause does not work with dynamic counter-example
waveforms
Description: If you are debugging an assertion failure using the dynamic waveform, the
Explore - Goto - Cause operation at a signal transition will not point to the HDL source line
that caused this transition. Instead, it will open the Source Browser with the Signal Flow
Tracer.
Solution: None.

June 2009
CCR 217136: ncdc does not reproduce cds.lib with IEEE_pure path when
required
Description: In designs where the IEEE library pointer is referencing the IEEE_pure version
located in install_dir/tools/files/IEEE_pure/IEEE instead of the default version
of IEEE in install_dir/tools/files/IEEE, ncdc is not able to reproduce a cds.lib
file that contains a path to use the IEEE_pure version of the libraries.
Solution: The cds.lib file that ncdc produces must be edited to contain the proper path
to use the IEEE_pure version of the IEEE library. For example:
include $CDS_INST_DIR/tools/inca/files/cds.lib
Must be changed to:

include $CDS_INST_DIR/tools/inca/files/IEEE_pure/cds.lib
CCR 41339: ncls errors out when different units have the same name in
mixed-language design
Description: ncls is unable to list a VHDL design unit in a mixed-language design if a

Verilog design unit with the same name exists. For example, consider a mixed-language
design with the following design units:
■ VHDL entity named truth_table (lowercase in the design file)
■ Architecture for truth_table is behave (lowercase in the design file)
■ Verilog module truth_table (lowercase in the design file)
ncls will error out if the case of the design unit name is not preserved. For example, the
following command generates a "No matching units found" error:
% ncls WORKLIB.TRUTH_TABLE:BEHAVE
However, the following ncls command will list the unit:

WORKLIB.truth_table:behave

June 2009
If there are no Verilog units with the same name in the work library, ncls treats the design unit
names in a case-insensitive manner.
Solution: Preserve the case while specifying the design unit name.
Product Level 2: PFI
CCR 522880: VHDL Event Synchronization with CPF behavior

Description: Cannot verify behavior of a VHDL (wakeup) block as the simulation is

producing the wrong results. The synchronizer is based upon a process that tries to update
the value of three signals - updating the first and then using its value to update the other two.
These update statements are written inside a VHDL process block.
Solution: Event ordering needs to be restructured in such cases. It is a user error if the
process block is expected to get the updated value of a signal/port within the process block.
These value updates are scheduled for the next available delta cycle in the simulation. Thus,
their values will be accurately reflected after that delta cycle simulation has been completed.
In the current cycle, all other signals/ports referring to the updated port will continue to see
its previous value.
CCR 406975: Incorrect logging of signals in SimVision data file

Description: Incorrect data may be stored in the SimVision data files. This shows up as a
signal that suddenly stops changing (when up to this point there were many transitions). The
waveforms for this signal will be correct at the source, but as the signal is traced through the
hierarchy, it will exhibit this incorrect behavior in other levels.
Solution: None.

June 2009
Product Level 2: SYSTEMVERILOG
CCR 261760: Dynamic arrays are not supported in structs

OS: LINUX Version: 3.0_IA32
Description: Dynamic arrays are not supported in structs
Solution: None.
Product Level 2: TCL
CCR 43502: Difference in behavior with VCD and EVCD dump while using
save and restart
Description: There is a difference in ncsim behavior with the Tcl save and restart
commands while creating VCD and EVCD dumps. The simulation time up to which the
dumping occurs can be different for an EVCD dump when compared to a VCD dump.
Solution: When dumping EVCD, close and then reinvoke the simulation instead of using the
save and restart commands.
CCR 31538: The NC-Sim Tcl expr command behaves differently on an

array
Description: The NC-Sim Tcl expr command behaves differently on an array, depending
on how the array was created.
For example, if the array was created as follows:

ncsim> set a(ns) 0
then the expr command behaves as expected:

June 2009
ncsim> expr {$a(ns) - $a(ns)}

0
However, if the array is created as follows:

ncsim> array set b {ns 0}
then the expr command does not behave as expected:

ncsim> expr {$b(ns) - $b(ns)}
1''h0
Solution: If the expr of the array is printed first, the behavior is normal.
ncsim> array set c {ns 0}
ncsim> expr {$c(ns)}
0
ncsim> expr {$c(ns) - $c(ns)}
0
Planned Release: IUS8.1
CCR 27140: Line breakpoints deleted erratically when simulation is reset

Description: When you have line breakpoints set within subprograms, within processes,
and so on, some of these breakpoints get deleted when you reset the simulation. This
behavior is erratic in that some breakpoints are deleted, while others are not.
Solution: Set the breakpoints again after the simulation is reset.
Product Level 2: VCD
CCR 184556: EVCD incorrect for VHDL ports of type OUT, when drivers
exist inside SMART model
Description: An EVCD database is missing information for ports that are coming direct out
of SMART models. These ports do not change as much as compared to their counterparts in
a VCD or SHM database. This indicates that the driver information from within the SMART
model is not being collected while doing the EVCD dump. These ports have multiple drivers

June 2009
of various strengths at any given time, and if the strongest driver is one coming from the
SMART model, that port will not show correct value changes.
Solution: None.
Product Level 2: VPI
CCR 485572: ncsim crashes when opening an external process

Description: A crash may occur when an external process is started through the VPI
interface, and when files are read in by the external process. The different run directories in
GUI and batch mode causes the crash. This problem only depends on the external process
and has nothing to do with the simulator or the VPI interface.
Solution: Link every file and directory that the process needs into the AMS run directory.
CCR 207862: Restart callback routines cannot be static on Linux

Description: Restart callback routines (that are invoked at the start or end of restart) cause
a segmentation violation if they are declared static on a Linux platform.
Solution: Do not declare restart callback routines as static if you intend to run your
application on a Linux platform.

June 2009
Product: NC-VERILOG
Product Level 2: IP_PROTECT
CCR 83680: Out-of-module-references may not work with protected

design units
Description: An out-of-module-reference (OOMR) from or to a protected design, may not

work if the target is a protected design unit. Access to objects in a protected design unit using
OOMRs is disabled to avoid revealing information in the protected code.
Solution: Avoid using OOMRs while protecting a design unit.
CCR 82567: The use of Verilog-2001 features in a protected cell may leak
protected information
Description: If you have used a Verilog configuration in a design, and have used ncprotect
to protect the design, the binding information for the protected code can be accessed using
VPI.
Solution: Avoid using IP Protection with Verilog-2001 constructs.
Product Level 2: NCELAB
CCR 485577: 32-bit version of the tool is returning a 64-bit integer


June 2009
Description: The $rtoi function returns a 64-bit value, while a subsequent

$dist_uniform function only uses a 32-bit value, so the following warning message is
generated:
ncelab: *W,INTWID (../rtl/data_generator4.v,155|54): Invalid width (64) on
argument, (32) expected.
For example, the following code will cause the warning to be generated:
module mytest;
integer i,v,lr,ur;
integer s,w;
initial
begin
s=2;
for(i=0; i <3; i = i +1)
begin
v = $dist_uniform(s,$rtoi(-10.0),$rtoi(10.0));
$display("The value of v is %d", v);
end
end
endmodule
Solution: The $rtoi function does not return an integer in the sense of a Verilog integer
(which is essentially a 32-bit quantity). This function returns the integer portion of a real
truncated to a 64-bit quantity. So it is actually defined as returning a signed 64-bit value. This
is true regardless of whether a 32-bit or 64-bit executable is being used.
The reason that $rtoi was defined as returning 64 bits was to allow for the fact that values
may be present in a real that may be too large to be represented in 32 bits.
Using the example shown above, the workaround to this warning is to assign $rtoi(-10.0)
to an interger first, and then use it in the function $dist_uniform. This will eliminate the
warning messages.
For example:
module mytest;
integer i,v,lr,ur;
integer s;
initial
begin
s=2;
for(i=0; i <3; i = i +1)
begin
lr=$rtoi(-10.0);
ur=$rtoi(10.0);
v = $dist_uniform(s,lr,ur);
$display("The value of v is %d", v);
end
end
endmodule

June 2009
CCR 32763: ncelab errors out if dumpvars including scope is declared

within @*
OS: SOLARIS Version: ALL
Description: If
$dumpvars(1, <scope_name>);
is used within the always @* block, ncelab errors out with the following message:
ncelab: *E,INNOTR an instance name is not a legal rvalue
Solution: Instead of using always @*, expand the contents of *. For example, use always
@(in1 or in2) instead of always @*.
CCR 20299: UDP does not get compiled via Design Prep if it is missing
instance name
Description: If a higher-level design instantiates a UDP without the instance name, the
instance name will not be in the pc.db file, and the 5.X config will not consider the UDP as
part of the design. The UDP will not be compiled via Design Prep.
Solution: There are two workarounds:

■ Compile all UDP cells from the command line before elaboration.
■ Add instance names for all instantiated cells.
CCR 8910: Design can elaborate via bindings but via config it fails
OS: SUN4U/5.7 Version: NONE
Description: Any time you have an implicit wire driven by only a VHDL instance, you get a
message. This is related to autoshelling.
Solution: None.

June 2009
Product Level 2: NCPREP
CCR 15486: ncprep +redirect+ causes cds.lib to point to incorrect work

library location
Description: When the +redirect+ option is used with ncprep (ncprep

+redirect+path), all output is redirected to the location specified in path. This includes the
INCA_libs directory, the RUN_NC script, cds.lib, hdl.var, and the ncsim.args,
ncelab.args, and ncvlog.args files.
However, the cds.lib file still contains the library path relative to the directory in which
ncprep was invoked. For example if ncprep was invoked from directory a as follows:
a> ncprep +redirect+./b *.v
All the files would be written to directory a/b/, but the cds.lib file in a/b/ would still
contain the path as ./b/INCA_libs/worklib. Thus, RUN_NC would not work when
invoked from a/b/ due to the incorrect path.
Solution: There are two workarounds:
1. After running ncprep, copy the cds.lib and hdl.var files from path to the directory
from which ncprep was invoked. In the example above, copy the files from a/b/ to a.
2. Use ncprep with the +nclibdirpath+ option instead of +redirect+:

ncprep +nclibdirpath+<path> *.v
This option creates the compiled libraries (INCA_LIBS) in the location specified by <path>,
and creates all other files (including cds.lib) in the current working directory.
Product Level 2: NCSIM
CCR 491222: Use of function call in bit-select or indexed part-select of an

assign statement or output port expression

June 2009
Description: If the left-hand side of an assign statement is a bit-select or indexed

part-select, and the index expression includes a function call, incorrect simulation or a crash
will result:
assign w[f(x)] = y;
assign w[f(x) +: 8] = z;
This also applies to port expressions connected to an output port.

mod u1 (.out(w[f(x)]));
The result of the above will be an "illegal port connection" error.
Solution: Use a local parameter to hold the value of the index expression. For example:
localparam p = f(x);
assign w[p] = y;
assign w[p +: 8] = z;
mod u1 (.out(w[p]));
CCR 486178: ncverilog shows different strength on a subset of a signal

Description: Concatenated signals passed using the multiplier into a module do not
represent the same signal strength.
In the following example, there are two signals, B and BB, which are both derived from a signal
DB. Signal B shows a strength of weak 1, while signal BB shows strength of strong 1, when it
should be weak 1. For example:
mymod U2 (.B(DB[0:10]), .BB({3{DB[3]}},DB[3:4]);
The signal BB shows a different strength than B.
Solution: Modify the netlist so that, instead of using the multiplier concatenation, you are
using "equivalent" concatenations. That is, modify:
mymod U2 (.B(DB[0:10]), .BB({3{DB[3]}},DB[3:4])
to:
mymod U2 (.B(DB[0:10]), .BB(DB[3],DB[3],DB[3:4])

June 2009
CCR 485711: Default timescale for Verilog-XL and NC-Verilog are different
when recording to database
Description: When `timescale is not defined in your HDL, you will get different simulation
data for Verilog-XL and for NC-Verilog. By default, Verilog-XL uses `timescale 1ns/1ns,
while NC-Verilog uses `timescale 1s/1s.
Solution: Define `timescale for your design.
CCR 485690: NCSIM fails when P-Threads are linked on the Linux
platform
OS: LINUX Version: RedHat7.0
Description: NCSIM fails when P-Threads are linked on the Linux platform. P-Threads are
not supported with NCSim on Linux. The threading library does not work consistently on this
platform.
Solution: Change your code to use QuickThreads instead of P-Threads.
CCR 485481: $sformat task does not return a value

Description: The $sformat task can be used to format values. According to the IEEE
LRM, it can be used in the following ways:
$sformat (output_reg, format_string, list_of_arguments);
length = $sformat (output_reg, format_string, list_of_arguments);
When used in the second manner, as in the following example, the elaborator generates an
error.
length = $sformat (output_reg, "%b %h %b", mem[15], mem[5], mem[11]);
The elaborator generates the following error message:

ncelab: *E,NOTUFN (./test.v,12|22): expecting a function name [2.7.3(IEEE)].
*** Error code 1

June 2009
Solution: It is not possible to use the same name for a system task and a system function.
NC-Verilog has chosen to implement $sformat as a system task. This CCR illustrates a bug
in the IEEE specification, which is being reported to the IEEE.
CCR 186558: $ftell() does not function correctly on Linux

Description: The Verilog system task $ftell() does not function correctly on Linux due
to an ftell() implementation bug in Linux's stdio library.
Solution: None.
CCR 29523: reset/restart commands disable statement trace writing

Description: Statement tracing gets disabled when the reset or restart commands are
used while running the simulation.
Solution: None.
CCR 29122: Edge to source may not work with non-blocking assignments
Description: Tracing the cause of a transition may not work with non-blocking assignments
that have delay control. Depending on the time delay involved, there may be an error in trying
to trace the statement that caused the transition.
Solution: None.

June 2009
Product Level 2: NCSIM_SHM
CCR 35452: wrapsize option with recordfile does not work with
NC-Verilog
Description: The wrapsize option to $recordfile does not work with NC-Verilog. The
documentation for all supported releases of NC-Verilog states that this option is supported.
However, it does not work for any version of NC-Verilog.
Solution: This option works with NC-Verilog if you add the following to your
LD_LIBRARY_PATH or SHLIB_PATH:
install_dir/tools/simvisdai/lib
CCR 30875: Database opened without the -statement option does not
have variable declaration
Description: When a database is opened without the -statement option, the Design
Browser does not recognize nets, registers, or variables. Therefore, if you try to use the
Select - Nets or Select - Registers menu choices, the Design Browser cannot select any
signal probed into the database.
Solution: None.
Product Level 2: NCSIM_TCL
CCR 286582: Tcl force command does not extend 'x' or 'z' values beyond
32 bits

June 2009
Description: In Verilog-2001, a Verilog value such as 'bx that does not have an explicit bit
size gets the bit size from the context where it is used. Prior to this, it was treated as a 32-bit
literal. This change has not been reflected in the Tcl force command, which is supposed to
behave identically to the Verilog force command.
Consider the following testcase:

module m;
reg [33:0] r;
initial #10 force r = 'bz;
endmodule
Simulating this model in interactive mode, the following commands illustrate the problem:
ncsim> force r = 'bz
ncsim> value r
34'h0zzzzzzzz
ncsim> run
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> value r
34'hzzzzzzzzz
ncsim>
The force from Tcl did not extend the z to all 34 bits, only the first 32. Prior to 2001, this was
correct. But now it has changed, as you can see from the equivalent Verilog force in the
model.
Solution: Use explicit bit size when the literal should be greater than 32 bits. For example:
ncsim> force r = 34'bz
CCR 126155: Describe and driver Tcl commands give value(s) of entire
multi-dimensional array
Description: The Tcl describe and drivers commands describe the entire array when
used on a multi-dimensional array or part-select of the array. The commands also show the
values of the entire array, and not the part-select under question.
Solution: None.

June 2009
Product Level 2: NCVLOG
CCR 201861: Same named file in a new working directory does not force
Verilog recompilation
Description: Invoking ncverilog causes recompilation of a design if either:

■ One of the source files previously used in the design changes.
■ The ncverilog command line is different from that of the previous run.
However, two separate working directories may have Verilog source files with the same
names. In this case, if you issue an ncverilog command from one directory, and then issue
the same command from the second directory, the second command does not update the
design being simulated.
Solution: To force the recompilation, make the command lines differ when compiling from
the two separate directories. For example, add different +name+name options to the two
ncverilog command lines.
CCR 35056: Verilog-XL and NC-Verilog produce different $dumpports

results
Description: In NC-Verilog, in cases where a net is connected to a supply net, the entire net
is treated as a supply net. Therefore, with NC-Verilog, there is no direction for a supply net.
This is not the case with Verilog-XL.
Solution: None.

June 2009
Product Level 2: NCXLMODE
CCR 211760: cds.lib in -y directory causes ncverilog to fail during

elaboration
Description: If a directory specified by the -y command-line option to the ncverilog

command contains a cds.lib file, the elaborator step fails with a NOUNCA error.
Solution: Avoid using cds.lib files in directories to be used later with the ncverilog -y
switch. For any testing with such a directory, use ncvlog in default mode. The default mode
generates a local work library in INCA_libs and does not require a cds.lib or hdl.var
file.
Product Level 2: OTHER
CCR 95733: ncdc will not decompile protected code

Description: When ncdc encounters a module that has been protected, it will produce the
following warning message:
WARNING (ncdc): Protected code is encountered, can't decompile!
Since this is not valid Verilog code, it will not pass through the ncvlog parser until this issue
has been resolved.
Solution: Keep the protected modules which were used in the design in a separate file which
can be parsed by ncvlog when you parse the output of ncdc. Go through the output of ncdc
and remove all modules that it could not decompile due to protection.

June 2009
CCR 17001: pak files do not get updated if you copy an existing library to
a new name
Description: If an existing library is copied to a new name, the library with the new name is
not usable.
Solution: Recompile the library after copying it. Recompiling will eliminate the problem.
Product Level 2: OVM_LIB_CDNS
CCR 620104: XBUS example does not work with -svpp switch
Description: Using the -svpp switch with the XBUS example provided in IUS 8.2 (and later)
results in an error of the form:
typedef class xbus_transfer;
|
ncvlog: *E,UNDIDN (./INCA_libs/irun.lnx86.08.20.nc/svpplib/specials/tlm_if_base_
xbus_transfer_xbus_transfer.svi,84|26): 'xbus_transfer': undeclared identifier [
12.5(IEEE)].
Solution: Do not use the -svpp switch when running the XBUS example.
Product Level 2: PERFORMANCE
CCR 257583: Fork/Join style testbench runs very slowly

Description: In some cases, optimizations for testbench fork/join blocks will not be applied
if there is a $stop and/or a $finish statement inside the block. In addition, an optimization
will not be applied if there are more than 10,000 statements in a block.

June 2009
Solution: Move the $stop or $finish statement out of the fork/join block and put them into
a separate initial statement.
CCR 20740: Slow vpiDriver access in vpi_iterate when const connected

to a vector bit
Description: The VPI call vpi_iterate(vpiDriver, simNetH) for a bus bit may have
slow performance if another bit of the same bus is connected to a constant (even if the other
bit is unused).
Solution: Modify the design by assigning wires to supplies and replacing each 1'b0/1'b1 bit
constant with the matching wire.
Product Level 2: PFI
CCR 607903: Automatic coverage model not generated on AIX 64-bit

platform
Description: The AIX 64-bit plaform does not support coverage generation. No coverage
model is generated when you use the -lps_verify command-line option.
Solution: None.
CCR 554371: Isolation between power domains not added to

SystemVerilog interface signals

June 2009
Description: In low-power simulation, SystemVerilog interfaces and modports are

supported at the power domain boundary or within a power domain. However, isolation
between power domains does not work for interfaces at the power domain boundary. When
module instances sharing an interface instance belong to different power domains, isolation
is not added to the interface signals.
Solution: None.
CCR 418860: Verilog netlist simulation with CPF fails

Description: When simulating a Verilog netlist with a CPF file, the output of the SRPG flip
flops goes to X when their power domain is turned off, but they remain X even after power is
restored. This should not happen, and the Q output should be restored to the value that it had
when the save pin of the flip flop was activated.
Solution: Change the polarity of the restore/save signal in the Verilog.
Product Level 2: RANDOMIZATION
CCR 484538: Function calls within an inline constraint expression cannot

have a prefix
Description: Inline constraint expressions cannot contain functions with prefixes. (A prefix
is used to specify a class handle.) For example, the following is not currently supported:
r = ch1.randomize() with { r1 == ch1.fun1(); };
Solution: To workaround this, remove the function call's prefix. Or, introduce a temporary
variable that is set in a pre_randomize function. For example:
r = ch1.randomize() with { r1 == fun1(); }; //Removes prefix ch1 in the function
call
Or:

June 2009
class ...
int tmp;
void function pre_randomize(); tmp = ch1.fun1(); //Creates a temporary
variable for the function call endfunction ... r = ch1.randomize() with { r1 ==
tmp; };
Planned Release: IUS8.1
CCR 437516: LRM restrictions on functions that are called in constraint

expressions are not fully enforced
Description: The IEEE P1800 LRM lists the following restrictions for functions that are
called in constraint expressions: 1) Cannot contain output or ref arguments 2) Should be
automatic, and have no side effects 3) Cannot call rand_mode or constraint_mode
The current implementation does not enforce these restrictions.
Solution: None.
Product Level 2: SVPP
CCR 454583: svpp does not support parameterized types and

specializations in different scope
Description: svpp has a current limitation such that the type used for a specialization must
be in the same scope as the parameterized type.
package pkg;
class myclass#(type T=int);
T value;
endclass
endpackage
module test;
import pkg::*;
class C;
endclass
myclass #(C) myc = new; endmodule

June 2009
Solution: The class used for the specialization must be in the same scope as the
parameterized type. In the example above, class C must be declared in package pkg (or class
myclass#(T) must be declared in module test).
package pkg;
class myclass#(type T=int);
T value;
endclass
class C;
endclass
endpackage
module test;
import pkg::*;
myclass #(C) myc = new;
endmodule
Product Level 2: SYSTEMVERILOG
CCR 341632: Named event probes are inaccurate after SystemVerilog

event assignments
Description: When an event assignment involves probed named events, some triggers of
the events might not be recorded. This issue occurs with SHM and VCD named event probes.
Solution: None.
CCR 270608: Cannot have a member of a struct with bit overflow

Description: ncelab gives *internal* when the element of the packed struct with bit overflow
:
module top();
struct packed{ bit [2:0][9999999999:0] a ;}abc;
endmodule
Solution: The workaround is as follows:

■ Use the members of struct within the specified limits so that there is no bit overflow.

June 2009
■ ncelab generates the internal error only when the -access +rwc option is used. If you
do not use this option, ncelab does not crash.
CCR 230533: Scope randomize calls cannot be made from protected

Verilog code.
Description: SystemVerilog does not support scope randomize calls from protected Verilog
code.
Solution: At this time, there is no workaround except to unprotect the Verilog code.
CCR 217696: AMS cannot make reference to SystemVerilog constructs or

data types.
Description: AMS cannot make reference to SystemVerilog constructs or data types.
Solution: At this time, there is no workaround except to remove AMS references to

SystemVerilog constructs or data types.
CCR 190036: The always_comb construct produces unexpected results.

Description: If a variable or signal on the right-hand side of an assignment is embedded

inside a non-local function call, the always_comb construct produces unexpected results,
unless the variable or signal is an argument of the function.
Non-local functions are functions that reside in another design unit (such as another module,
program block, package, or interface). Non-local function calls are usually invoked by
out-of-module references, unless the function has been imported from a package.

June 2009
Solution: Do one of the following:

■ Ensure that variables and signals on the right-hand side of an assignment that is
embedded within a function are passed into the function.
■ Replace the always_comb construct with an always block that has an explicit
sensitivity list.
CCR 156103: Interface references are not probed with $shm_probe()

Description: There is a current limitation on the probing of interfaces such that an interface
that is passed through a port is not probed by a call to $shm_probe() that designates a
portion of the hierarchy below the actual instance of the interface.
Solution: To probe the contents of the interface, you can call $shm_probe on the instance
of the interface itself and/or on any level of the design hierarchy at or above the interface
instance.
Product Level 2: TIMING
CCR 183443: Wrong file name may be given for SDF interconnect warning
Description: Incorrect SDF file names may be displayed when reporting errors or warnings
during interconnect annotation.
Interconnect verification is conducted long after SDF files have been read and processed.
While line numbers are tracked during the SDF process, file names are not. When warnings
(for example, SDFINC) are reported, the file name in the last $sdf_annotate is reported,
and if the -sdf_verbose option is used, the interconnect annotation information is also
reported to the log file specified in the last $sdf_annotate. This may not be correct if
multiple $sdf_annotate tasks exist.
Solution: None.

June 2009
CCR 28372: Multi-source interconnect delay with continuous assign

takes the interconnect path when multiple paths enabled
Description: A multi-source interconnect delay with a continuous assignment takes the

interconnect delay path when multiple paths are enabled instead of the one with zero delay.
| <--------INTERCONNECT -------->|
u1a
---------
in1 | Buffer | outa
-----| |--------------
| | |
--------- |
| |
| |
en1 | ------------
| | | out
------------ cont assign |------
u1b | | |
--------- | ------------
in2 | Buffer |outb |
-----| |--------------
| |
---------
|
|
en2
In the above scenario, when both buffers have their enable on, the output of the continuous
assign (out) gets the data flow from the flow of the interconnect (u1a) instead of the value of
the zero delay (u1b).
Solution: None.
CCR 3175: XL/NC difference on register use in timing checks

OS: ALL Version: NONE
Description: Verilog-XL allows registers to be used in timing checks, but NC-Verilog errors
out.

June 2009
Solution: The Verilog LRM states that vectored nets are supposed to be used in timing
checks and not registers. Change the register to a vectored net.
Product Level 2: URM
CCR 593287: ovm_component constructor must have name and parent

arguments in correct order
OS: LINUX Version: TEST
Description: Prior to OVM 2.0, the binding of the default constructor arguments, name and
parent, were bound by name in the factory. In OVM 2.0, the name and parent arguments
are bound by position. For example, the following code will not compile:
class mycomp extends ovm_component;
function new (ovm_component parent, string name); // Incorrect order
super.new(name,parent);
endfunction
`ovm_component_utils(mycomp) // Factory registration has compile error.
endclass
Solution: The name argument must be the first argument in the constructor and the
parent argument must be the second argument. For example, the following code will
compile correctly:
class mycomp extends ovm_component;
function new (string name, ovm_component parent); // Correct order
super.new(name,parent);
endfunction
`ovm_component_utils(mycomp)
endclass
Adding a third argument must follow the string name and ovm_component parent arguments
Product Level 2: VPI
CCR 485672: vpiProtected Boolean property always returns false


June 2009
Description: The vpiProtected property of the type vpiGenScope for Verilog-2001

generate blocks always returns false, whether the generate block is protected or not.
Solution: None.
CCR 146114: Stopping and resuming of SHM database in NC-Verilog

Description: NC-Verilog does not provide the system task $shm_suspend/$shm_resume

for stopping/resuming SHM database dump.
Solution: To stop/resume the SHM database, you can use the following:
■ The simulator Tcl command database -disable
■ The system tasks $recordoff/$recordon
CCR 80823: Port information is visible through VPI even if protected

Description: In a Verilog design in which a Verilog module is instantiated, if only the portmap
information of the instantiation is protected, the port information is visible through VPI.
Solution: Instead of protecting only the portmap information, protect the complete
instantiation statement, or protect the port declarations in the instantiated module.
CCR 50068: The vpi_get_value routine does not return a value for a
continuous assignment
Description: When you pass a handle to a continuous assignment statement, the

vpi_get_value routine does not return the value being driven by that statement. If multiple
drivers on a net are modeled by multiple continuous assignments, it is not possible to

June 2009
determine the contribution of each assignment to the resolved value of the net using the
handles to the continuous assignment statements themselves.
Solution: Use the value of the expression on the right-hand side of the continuous
assignment's equal sign, rather than the value of the assignment itself.
CCR 28838: Using C++ functions does not create the correct simulator
executables
Description: When C++ functions like cout are used in the PLI/VPI source files and linked
using the PLI Wizard utility (with the NC Simulators > NC-Verilog > libpli option),
libpli.so, ncelabC, and ncsimC are created. However, while running ncelabC, you will
get a relocation error.
Solution: None.
CCR 5826: Restart does not work with SWIFT models

OS: SUN4/5.5.1 Version: NONE
Description: If the design contains SWIFT models, you cannot restart from a saved
snapshot.
Solution: None.
CCR 5825: Reset does not work after a finish command has been
processed
OS: SUN4/5.5.1 Version: NONE
Description: Reset does not work if the reset is executed after a $finish. Resetting works
if the command is issued before $finish.

June 2009
Solution: Reset before the $finish command.

June 2009

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Cadence® NC-Verilog® Simulator Known

Problems and Solutions

Updated June 2009

June 2009 3 Product Version 8.2

June 2009 4 Product Version 8.2

CCR 485572: ncsim crashes when opening an external process . . . . . . . . . . . . 24

June 2009 5 Product Version 8.2

Product Level 2: NCVLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

June 2009 6 Product Version 8.2

CCR 156103: Interface references are not probed with $shm_probe() . . . . . . . . 42

June 2009 7 Product Version 8.2

June 2009 8 Product Version 8.2

Cadence NC-Verilog Simulator Known

Product Version 8.2

June 2009 9 Product Version 8.2

Product Level 2: DOC

Planned Release: Not currently planned.

Product Level 2: IP_PROTECT

Solution: The IP should be encrypted using:

Planned Release: Not currently planned.

June 2009 10 Product Version 8.2

Solution: Do not use Verilog system tasks with ncprotect.

Planned Release: Not currently planned.

CCR 84543: ncsim internals with SDI and protected code

Solution: Avoid using system tasks with protected design units.

Planned Release: Not currently planned.

CCR 82101: VHDL attributes may reveal protected information

Solution: Avoid using predefined attributes in the designs to be protected.

Planned Release: Not currently planned.

CCR 80102: $display system task displays protected instances

June 2009 11 Product Version 8.2

Planned Release: Not currently planned.

CCR 79122: Report statement inside protected IP may reveal protected

Planned Release: Not currently planned.

Product Level 2: IRUN

CCR 543309: Under irun the SPECMAN_PRE_COMMANDS are only seen

Description: The different stages of Specman compilation cannot rely on the

Planned Release: Not currently planned.

June 2009 12 Product Version 8.2

Product Level 2: NCELAB

CCR 263256: Changing the timestamp of a file regenerates intermediate

Planned Release: Not currently planned.

CCR 182523: Generated configuration files in hierarchical mode with

June 2009 13 Product Version 8.2

Planned Release: Not currently planned.

CCR 178499: Generation of configuration file fails for multiple library

Description: The configuration file generator (invoked with ncelab -conffile)

Planned Release: Not currently planned.

CCR 102260: Unable to elaborate large designs on the AIX platform

Planned Release: Not currently planned.

Product Level 2: NCSIM

June 2009 14 Product Version 8.2

Planned Release: IUS8.1-S

Solution: Rename the modules so that they have unique names.

Planned Release: Not currently planned.

CCR 308902: Built-in function IEEE.std_logic_arith does not report error

Solution: Use the -nobuiltin option during compilation.

Planned Release: Not currently planned.