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  • 14 Da 1 05 05 2023

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    Vanya Nandwani
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    This document outlines four digital design assignments: 1) Implement a full subtractor using various logic styles including pass transistor, transmission gate, pseudo NMOS, CVSL/DCVSL, and dynamic and domino logic. 2) Analyze and compare two designs of a 2-input AND gate in terms of speed, calculating path effort and delay based on input capacitances. 3) Explain the P-well CMOS fabrication process in detail. 4) Determine the combination of flip flops that should replace those in a flip flop pair diagram to achieve the maximum clock frequency of operation based on their timing specifications.

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    This document outlines four digital design assignments: 1) Implement a full subtractor using various logic styles including pass transistor, transmission gate, pseudo NMOS, CVSL/DCVSL, and dynamic and domino logic. 2) Analyze and compare two designs of a 2-input AND gate in terms of speed, calculating path effort and delay based on input capacitances. 3) Explain the P-well CMOS fabrication process in detail. 4) Determine the combination of flip flops that should replace those in a flip flop pair diagram to achieve the maximum clock frequency of operation based on their timing specifications.

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    12 views1 page

    14 Da 1 05 05 2023

    Uploaded by

    Vanya Nandwani
    This document outlines four digital design assignments: 1) Implement a full subtractor using various logic styles including pass transistor, transmission gate, pseudo NMOS, CVSL/DCVSL, and dynamic and domino logic. 2) Analyze and compare two designs of a 2-input AND gate in terms of speed, calculating path effort and delay based on input capacitances. 3) Explain the P-well CMOS fabrication process in detail. 4) Determine the combination of flip flops that should replace those in a flip flop pair diagram to achieve the maximum clock frequency of operation based on their timing specifications.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    VLSI System Design

    Digital Assignment-1

    Max. Marks -10M

    1. Implement Full subtractor using


    (i) Pass Transistor Logic
    (ii) Transmission gate Logic
    (iii) Pseudo nmos Logic (size according to Reference pseudo inverter)
    (iv) CVSL/DCVSL Logic
    (v) Dynamic and Domino Logic
    2. Consider the two designs of a 2-input AND gate shown in Figure. Give an Intuitive argument
    about which will be faster. Back up your argument with a calculation of the path effort, delay,
    and input capacitances x and y to achieve this delay.

    3. Explain in detail the P-well CMOS fabrication Process.


    4. Consider the below flip flop pair logic diagram and the table with three different flip flops FF1,
    FF2, and FF3 with their timing specifications.

    Which combination of flip flops should be replaced in the below flip flop pair to get the
    maximum clock frequency of operation.

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