1st International Conference on Advances in Science, Engineering and Robotics Technology 2019 (ICASERT 2019)

Effects of Wave Function Penetration on Gate

Capacitance and Threshold Voltage of p-Channel
Double Gate Junction Less Field Effect Transistor
Md. Mohsinur Rahman Adnan1∗ , Mohammad Shahidur Rahman1
1 Department of Computer Science and Engineering, Shahjalal University of Science and Technology,
Sylhet-3114, Bangladesh
*e-mail: adnanmohsin27@gmail.com

Abstract—Wave function penetration phenomenon had been

studied for a p-channel Double Gate Junction Less Field Effect
Transistor in terms of Capacitance-Voltage (C-V) characteristics.
It has been found that the gate capacitance differs visibly for
the two cases (i.e. with and without penetration) in device’s
accumulation mode only. As a result, it is safe to assume that the
threshold voltage is not dependent on wave function penetration
for this device; which had been established by extracting data
from the simulated C-V curves.
Fig. 1: Wave Function Penetration (WFP) effect in Double Gate Junction Less Field
Effect Transistor (DGJLFET). The structure is basically a quantum well with 1D
Index Terms—Junction Less Field Effect Transistor, Wave confinement. Being a finite potential well, it is safe to assume some penetration into
Function, Schrödinger-Poisson Solution, Gate Capacitance, gate oxide occurs as shown in (b), instead of ideal case with infinite barriers as depicted
Threshold Voltage. in (a).

I. I NTRODUCTION
The need for quantum mechanical modeling of Field Effect
Transistor (FET) devices’ characteristics was first described
and practically implemented by Stern [1]. To model the ultra-
small devices with micro-to-nanometer range feature lengths,
Stern employed self-consistent methodology which solved
Schrödinger and Poisson equations iteratively till a complete
description of charge distribution and potential profile inside
the FET structure was found. With the scaling of FET devices
to ever decreasing sizes, self-consistent modeling has become
a popular method to model their electrostatics now-a-days.
In his model, Stern assumed that the FET structures were
quantum confined i.e. well (1D) or wire (2D) with infinite
potential barriers surrounding the channel [1]. As a result, the
carrier wave function was assumed going to zero abruptly at
channel-oxide interface. But this is not really a valid scenario
as the potential barrier height arising from the difference in
band structure of channel and oxide materials’ is actually
equals to only a few electron volts [2]. As a result, assuming
carrier wave function does not penetrate into the gate oxide
of the device gives an incomplete picture of the potential
profile and charge distribution inside the FET structure [2].
So, in order to obtain a more complete description of charge
distribution, potential profile and other electrostatic properties
like gate capacitance and threshold voltage, a few previous
works [2], [3] have allowed carrier wave function to penetrate
into gate oxide. All of them studied Inversion Mode (IM)
MOSFET, so there is a scarcity of such modeling for other
FET devices in literature.
Recently, a new FET device called the Junction Less Field
Effect Transistor (JLFET) has been proposed [4]. While IM-
MOSFET has its carriers conducting at channel surface just be-
low the channel-oxide interface [3], the JLFET device’s carrier
conduction mostly happens at or near the channel center [4].
Specially during sub-threshold and near threshold operation,
the bulk conduction mechanism of JLFET can not be ignored
[4]. As a result, it is quite possible that considering wave
function penetration effect while self-consistently modeling
JLFET electrostatics is not so important as in the case of IM-
MOSFET modeling.
Indeed, a recent study of Capacitance-Voltage (C-V) char-
acteristics of n-channel Double Gate (DG) JLFET device has
demonstrated that the threshold voltage of n-JLFET remains
unchanged, whether penetration is allowed or not [5]. The
study also showed that wave function penetration phenomenon
has effect on C-V curves only in accumulation mode of n-
JLFET operation [5]. Even though definite proof of theory
now exists for n-JLFET, no such study was carried out for
p-JLFET yet. As the results for deep submicron n- and p-
MOSFETs were found to be different in [2], it is necessary to
carry out a similar study for p-JLFET. So, the present work
aims to first simulate the p-DGJLFET C-V characteristics both
allowing and disallowing wave function penetration and then
study gate capacitance and threshold voltage to find out if they

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Fig. 2: Self consistent solver [1].
Fig. 3: Double Gate Junction Less Field Effect Transistor (DGJLFET) structure.
are as affected as in the case of n-JLFET by the occurrence
of this phenomenon.
II. S IMULATION D ETAILS
An one-dimensional Schrödinger-Poisson solver, as de-
scribed in [1], had been designed. It simulates the C-V curves.
The solver’s mechanism is shown in Fig.2. JLT physics, as
described in [6], had been incorporated in the simulator design.
The permittivity value, band gap and band offset of gate
dielectric were taken form [3]. The valance band offset was
calculated by subtracting the conduction band offset from the
bandgap offset. Degeneracy data along with DOS and Quanti-
zation effective masses of holes were taken form [2]. The hole
effective mass inside gate oxide is taken as 0.5m0 , m0 being
electron’s rest mass [2]. Whenever wave function penetration
had to be ignored, the valance band offset was made very high.
The threshold voltage, as suggested by [7], had been extracted
assuming zero mobility variation. Then the threshold voltage
dCgate
Vth is given by the position of maximum peak of | dVgate | vs.
gate dC
Vgate curve. For p-channel JLFET, absolute value | dVgate | had
been plotted to observe the change only, ignoring its direction.
The range of uncertainity for all reported threshold voltage
values is limited to in between ±0.1 V.
III. R ESULTS
The device modeled is shown in fig.3. The gate is made
of n+ poly Si. The channel is of p-type Si. The oxide
is SiO2 . The used parameters are doping concentration,
NA = 1019 /cm3 , channel thickness, tsi = 10nm, and oxide
thickness, tox = 2nm. These parameters had been maintained
in most simulations.
To find the effect of changing oxide material, along with
SiO2 , other gate oxides used were Hf O2 and Y2 O3 . Fig.4
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dC
gate
and fig.5 depicts the C-V curves and | dVgate | vs Vgate curves
respectively.
The chosen channel thickness values were 6, 8 and 10 nm;
and results were studied. Fig.6 and fig.7 depicts the C-V curves
dCgate
and | dVgate | vs Vgate curves respectively.
The chosen oxide thickness values were 1, 1.5 and 2 nm;
and results were studied. Fig.8 and fig.9 depicts the C-V curves
dCgate
and | dVgate | vs Vgate curves respectively.
The chosen doping concentration values were 1019 /cm3 , 5∗
1018 /cm3 and 1018 /cm3 ; and results were studied. Fig.10 and
dCgate
fig.11 depicts the C-V curves and | dVgate | vs Vgate curves
respectively.
For the defined device structure, the flat-band voltage [6]
is −1.1V . In the C-V curves, saturation behavior occurs
beyond this voltage. This is also the voltage beyond which
gate capacitances differ due to penetration. So, from observing
the results it can be said that regardless of penetration the
gate capacitances are visibly matched up until accumulation
operation (i.e. saturation behavior ) [6].
dCgate
The maximum peak in the | dVgate | vs. Vgate curves occurs
at same Vgate =Vth regardless of penetration.
IV. C ONCLUSION
In p-JLFET, initially a space charge region arising from the
acceptor doping fills up the whole body region. As the gate
voltage is gradually raised in positive direction, the depletion
region reduces and free holes start to gather at the channel
center. With sufficient holes gathered at the channel center to
nullify the depletion charges, a string like path of neutral-Si
from source to drain is created [4]. After this condition known
as threshold has occurred, applying a suitable drain to source
voltage will make conduction possible. As channel center and
channel-oxide interface are as far as they could be within the
structure, it is expected that wave function penetration into
gate oxide should have minimal effect on threshold voltage,
which has been established from the results of this work.
Moreover, no perceivable effect of wave function penetra-
tion on gate capacitance in full or partial depletion mode of
device operation is observed. The gate capacitance is defined
as,
qδ(p − NA− )
Cgate =
δVgate
where, q=charge of a hole, qp=mobile charge arising from
holes(+ve) and qNA− =depletion charge arising from acceptors
(-ve). In this equation, only the mobile charge, qp is variable.
This term is affected by wave function penetration only when
the holes are present near channel-oxide interface. Only then
the probability of holes tunneling into gate oxide takes on
a moderate value. This does not happen in full or partial
depletion mode of operation. Only beyond flat-band, when all
of p-JLFET channel is available for conduction [4], then the
mobile charge term is affected by wave function penetration.
So, the observations in this work comply with both theoretical
notions and the results for n-JLFET.
 (a) SiO2 (a) Channel 10 nm thick

(b) Y2 O3 (b) Channel 8 nm thick

(c) Hf O2 (c) Channel 6 nm thick

Fig. 4: C-V characteristics allowing and not allowing penetration while oxide material Fig. 6: C-V characteristics allowing and not allowing penetration while channel thickness
is varied. is varied.

(a) Not Allowing Penetration (a) Not Allowing Penetration

(b) Allowing Penetration (b) Allowing Penetration

Fig. 5: Threshold voltage extracted allowing and not allowing penetration while oxide Fig. 7: Threshold voltage extracted allowing and not allowing penetration while channel
material is varied. The maximum peaks, regardless of penetration, occur at the same gate thickness is varied. The maximum peaks, regardless of penetration, occur at the same
voltages (Vth ) i.e. 0 V for SiO2 , −0.4 V for Y2 O3 , and −0.5 V for Hf O2 . gate voltages (Vth ) i.e. 0 V for 10 nm, −0.2 V for 8 nm, −0.4 V for 6 nm.

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 (a) Oxide 1 nm thick (a) Doping concentration 1019 /cm3

(b) Oxide 1.5 nm thick (b) Doping concentration 5 ∗ 1018 /cm3

(c) Oxide 2 nm thick (c) Doping concentration 1018 /cm3

Fig. 8: Threshold voltage extracted allowing and not allowing penetration while oxide Fig. 10: Threshold voltage extracted allowing and not allowing penetration while doping
thickness is varied. concentration is varied.

(a) Not Allowing Penetration (a) Not Allowing Penetration

(b) Allowing Penetration (b) Allowing Penetration

Fig. 9: Threshold voltage extracted allowing and not allowing penetration while oxide Fig. 11: Threshold voltage extracted allowing and not allowing penetration while doping
thickness is varied. The maximum peaks, regardless of penetration,occur at the same concentration is varied. The maximum peaks, regardless of penetration, occur at the same
gate voltages (Vth ) i.e. −0.3 V for tox 1 nm, −0.2 V for tox 1.5 nm and 0 V for gate voltages (Vth ) i.e. 0 V for 1019 /cm3 , −0.4 V for 5 ∗ 1018 /cm3 and −0.7 V
tox 2 nm. for 1018 /cm3 .

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 R EFERENCES
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