A Project Report on

LOW POWER AREA EFFICIENT ALU USING GDI

BASED FULL ADDER

submitted
In partial fulfillment of the requirements for the award of the Degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

By

NAGAM HARIKRISHNA JAYASURYA 18751A04A7

NAGIRI ESWAR 18751A04A8
KARAMALA NAGABHUSHANACHARI 18751A0475
MAVITI LOKESH 18751A04A2

Under the Guidance of

Dr.S.VIJAYAKUMAR, Ph.D,
PROFESSOR, DEPARTMENT OF ECE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT STUDIES
(Autonomous)

Affiliated to J.N.T.U.A, Anantapuramu , NBA & Accredited

CHITTOOR-517 127
(2021-2022)

i
DEPARTMENT OF ELECTRONICS ANDCOMMUNICATION ENGINEERING

SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT STUDIES

(Autonomous)

Affiliated to J.N.T.U.A, Anantapuramu & NBA

Accredited CHITTOOR-517 127

CERTIFICATE

This is to certify that the project report entitled "LOW POWER AREA
EFFICIENT ALU USING GDI BASED FULL ADDER " that is being submitted by

Mr. NAGAM HARIKRISHNA JAYASURYA (18751A04A7),Mr. NAGIRI ESWAR

(18751A04A8), Mr. KARAMALA NAGABHUSHANACHARI (18751A0475), Mr.
MAVITI LOKESH (18751A04A2), in partial fulfillment for the award of the Degree
of Bachelor of Technology in ELECTRONICS AND COMMUNICATION
ENGINEERING to the Jawaharlal Nehru Technological University Anantapuramu, is a
record of bonafide work carried out under my guidance and supervision. The results
embodied in this project report have not been submitted to any other University or Institute
for the award of any degree.

Dr.S.VIJAYAKUMAR,Ph.D Dr.K.GOPI,M.Tech,Ph.D
Professor, Dept of ECE Head of the
Department Internal Guide Dept. of ECE
Submitted for University Examination (Viva-Voce) held on

Internal Examiner External Examiner

ii
 ACKNOWLEDGEMENT

The successful completion of this project work was made possible with the and
guidance received from various quarters. we would like to available this opportunity to
express oursincere thanks and gratitude to all of them.

We would like to express the heartfelt gratitude to our Management, Chairperson

Sri. K. RANGANATHAM GARU for providing excellent institutional support to
complete this project.

We would like to express the profound gratitude to our beloved principal

Dr.M.SARAVANAN,Ph.D, for giving us the opportunity to embark upon this course and
makeuse of the facilities available in the college.

We pay my sincere note of felicitation to Dr. K.GOPI,Ph.D, Professor &Head of

the ECE Department for providing excellent departmental support as well as
motivation which enhance the thrust to complete the project.

We thank my project guide Dr. S.VIJAYAKUMAR,Ph.D, Professor of ECE

Department for his valuable guidance, support and offering necessary material and
willingly giving us advice whenever needed.

We Finally, we thank all the teaching faculty and non-teaching staff of the
Department of Electronics and Communication Engineering for giving their advices and their
help during the course of our project work as well as studies.

NAGAM HARIKRISHNA JAYASURYA 18751A04A7

NAGIRI ESWAR 18751A04A8
KARAMALA NAGABHUSHANACHARI 18751A0475
MAVITI LOKESH 18751A04A2

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 Course Outcomes for project work

On completion of project work we will be able to,

CO1.Demonstrate in-depth knowledge on the project topic.
CO2.Identify ,analyze and formulate complex problem chosen for project work to attain
sustained conclusion
CO3.Design solutions to the chosen project problem.
CO4.Undertake investigation of project problem to provide valid conclusions.
CO5.Use the appropriate techniques, resources and modern engineering tools necessary for
project work.
CO6.Apply project results for sustainable development of the society.
CO7.Understand the impact of project results in the context of environmental sustainability.
CO8.Understand professional and ethical responsibilities while executing the project work.
CO9.Function effectively as individual and a member in the project team.
CO10.Develop communication skills, both oral and written for preparing and presenting
project report.
CO11.Demonstrate knowledge and understanding of cost and time analysis required for
carrying out the project.
CO12.Engage in lifelong learning to improve knowledge and competence in the chosen area
of the project.

CO-PO MAPPING
COs\
POs

CO1 √

CO2 √

CO3 √

CO4 √

CO5 √

CO6 √

CO7 √

CO8 √

CO9 √

CO10 √

CO11 √
CO12 √

iv
 Evaluation Rubrics for Project work:
Rubric (CO) Excellent (Wt = 3)
Select a latest topic through
Selection of Topic (CO1) complete knowledge
offacts and concepts.
Analysis and Synthesis Thorough comprehension
(CO2) through analysis/
synthesis.
Thorough comprehension
Problem Solving (CO3) about what is proposed
inthe literature papers.
Extensive literature survey
Literature Survey (CO4)
with standard references.
Clearly identified and has
Usage of Techniques complete knowledge of
& Tools (CO5) techniques & tools used
in the project work.
Project work impact Conclusion of project
on Society (CO6) workhas strong impact on
society.
Conclusion of project work
Project work impact
has strong impact
on Environment (CO7) onEnvironment.
Clearly understands ethical
Ethical attitude (CO8)
and social practices.
Did literature survey
Independent Learning
andselected topic with a
(CO9)
little guidance
Presentation in logical
sequence with key
Oral Presentation (CO10)
points,clear conclusion
and excellent language
Status report with clear and
Report Writing (CO10) logic sequence of chapters
using excellent language
Time and Cost Analysis Comprehensive time
(CO11) andcost analysis
Continuous learning Highly enthusiastic towards
(CO12) continuous learning
v
Good (Wt = 2) Fair (Wt = 1)
Select a topic through Select a topic through
partial knowledge improper knowledge of
offacts and facts and concepts.
concepts.
Reasonable Improper comprehension
comprehension through through analysis/
analysis/ synthesis. synthesis.
Reasonable
Improper comprehension
comprehension about
about what is proposed in
what is proposed in
the literature.
the literature papers.
Considerable literature Incomplete literature
survey with standard survey with substandard
references. reference.
Identified and has Identified and has
sufficient knowledge inadequate knowledge of
oftechniques & tools techniques & tools used
in the project work. in project work.
Conclusion of Conclusion of project
projectwork has work has feeble impact
considerable on society.
impact on society.
Conclusion of project Conclusion of project
work has considerable work has feeble impact
impact environment. environment.
Moderate understanding Insufficient
of ethical and understanding ethical
socialpractices. and social practices.
Did literature survey Selected a topic as
andselected topic with suggested by the
considerable guidance
supervisor
Presentation with key Presentation with
points, conclusion insufficient key points
andgood language and imprope conclusion
Status report with
logicalsequence of Status report not properly
chapterusing language organized
Moderate time and Reasonable time and cost
costanalysis analysis
Interested in Inadequate interest in
continuouslearning continuous learning
 ABSTRACT

In day-to-day development of transportable digital applications, the requirement for

reducing delay, decreasing in size, and low power dissipation various analysis efforts . We
would like to enhance the performance of logic circuits, once supported ancient CMOS
technology, and resulted within the development of the many logic style techniques
throughout the last twenty years. GDI (Gate diffusion input) is a method of low power
digital combinable style. This method permits less power consumption and reduced
propagation delay with minimum range of transistors as compare to alternative presently
used logic style designs, like CMOS, PTL, CPL and TG. But within the GDI
technology output voltage swing degradation, fabrication complexness, & power
consumption issues are the disadvantages. Attributable to this reason changed GDI was
planned. Modified GDI technology is additional economical in terms of power
consumption, fabrication complexness, and low output voltage swing degradation when
put next to GDI technology. In this paper, the design of a 4-Bit Arithmetic Logic Unit
(ALU) using Modified Gate Diffusion Input technique is being done which is implemented
using minimum transistor full adder and also adapts hardware reuse method which has
advantages of minimum transistors requirement, more switching speed and low power
consumption with respect to the conventional CMOS techniques. 4-Bit Arithmetic Logic
Unit (ALU) is being implemented with MGDI technique in DSCH 3.5 and layout
generated in Microwind tool. The Simulation is done using 65 nm technology at 1.2 v
supply voltage. The 4-bit ALU and its blocks were designed using GDI& modified GDI.
The results show that the proposed design consume less power uses less number of
transistors, while achieving full swing operation compared
to previous work.

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 CONTENTS

CHAPTER TOPIC PAGE NO

NO
LIST OF FIGURES ix

LIST OF TABLES xi
LIST OF ABBREVIATIONS xii
1 INTRODUCTION 1
1.1 Need For low power 3
1.2 Need for low Power VLSI chips 3
2 LITERATURE SURVEY 6
2.1 Design of Low power ALU using 7
8T FA and PTL based Mux circuits
2.2 A review paper on 3T XOR cells 7
and 8T adder design in cadence
180nm
2.3 Design of low power high speed 7
ALU using feedback switch logic
2.4 Low power sub-threshold 7
asynchronous QDI static
logic transistor level
2.5 Design of a low power , sub- 8
threshold ,asynchronous ALU using
a bi-directional adder
2.6 Energy efficient,high 8
performance circuits for arithmetic
unit
2.7 A low power 10-transistor full- 9
adder cell for embedded
architecture
2.8 An implementation of 1-bit low 9
power Full Adder based on
multiplexer and pass transistor logic
2.9 A fast ALU design in CMOS for 9
low voltage operation
3 PROPOSED APPROACH 10
4 EXISTING SYSTEM 16
4.1 Power dissipation types 17
4.2 Gate diffusion input technique 19
4.3 ALU using GDI technique 21
4.4 Multiplexer 22
4.5 Design of arithmetic and logic 23
unit
5 VLSI DESIGN 24
5.1 Introduction 25

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 5.2 Verilog advantages over VHDL 27
5.3 VLSI designs classification 27
5.3.1 Analog 27
5.3.2 ASICS or Application Specific 27
Integrated Circuits
5.3.3 SOC or System on a chip 28
5.4 VLSI design styles 28
5.4.1 Field Programmable Gate 28
Array (FPGA)
5.4.2 Gate array design 29
5.4.3 Standard-cells based design 30
5.4.4 Full custom design 31
5.5 Tool (DSCH & Ex-port Micro 32
wind)
5.6 Simulation environment 37
5.6.1 DSCH (Digital Schematic ) 37
5.6.2 Micro wind 38
6 SIMULATION RESULTS 43
6.1 Existing method 44
6.1.1 1-Bit ALU 44
6.1.2 4-Bit ALU 46
6.1.3 GDI cell 47
6.1.4 GDI 1-Bit ALU 48
6.1.5 GDI 4-Bit ALU 50
6.2 Proposed system 51
6.2.1 Modified GDI 1-Bit ALU 51
6.2.2 Modified GDI 4-Bit ALU 53
6.3 Comparision results 54
6.4 advantages of the proposed work 56
6.5 applications of the project 56
7 CONCLUSION AND FUTUR SCOPE 57
REFERENCES 59

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 LIST OF FIGURES

CHAPTER TOPIC PAGE

NO. NO.
1.2 Internal block diagram of FPGA 5
3.1 MGDI Based 2x1 Multiplexer 11
3.2 MGDI Based 4x1 Multiplexer 11
3.3 Full Adder cell for ALU 12
3.4 Schematic of 1-bit ALU stage using GDI 12
3.5 Schematic of 4-bit ALU stage using GDI 13
3.6 Schematic of 1-bit ALU stage using MGDI 14
3.7 Schematic of 4-bit ALU stage using MGDI 15
4.1 Traditional 1-Bit ALU 19
4.2 Basic GDI cell 20
4.3 4-Bit ALU 21
4.4 Multiplexer 22
4.4.1 2x1 Multiplexer using GDI Technique 22
4.4.2 4x1 Multiplexer using GDI Technique 22
4.4.3 GDI Based XOR Gate Full Adder 23
4.4.4 GDI Based 1-Bit Full Adder Cell 23
5.5 N-Channel and P -Channel 33
5.5.1 The Transmission Gate 33
5.5.2 Logics of Inverter 34
5.5.3 Logic symbol of the NAND gate 35
5.5.4 CMOS inverter circuits 36
5.5.5 CMOS inverter simulation 36
5.5.6 CMOS Inverter Wave forms 37
5.6 5.6.1 Symbol of NMOS and PMOS 37
5.6.2 Creating the N-channel MOS transistor 39
5.6.3 N-channel MOS characteristics 40
5.6.4 Selecting the PMOS device 40
6.1 6.1.1 1-Bit ALU 44
6.1.1.1 Traditional 1-Bit ALU 44
6.1.1.2 1-Bit ALU Schematic 44
6.1.1.3 1-Bit ALU Layout 45
6.1.1.4 1-Bit ALU Output 45
6.1.2 4-Bit ALU 46
6.1.2.1 4-Bit ALU Schematic 46

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 6.1.2.2 4-Bit ALU Layout 46
6.1.2.3 4-Bit ALU output 47
6.1.3 GDI cell 47
6.1.3.1 Basic GDI cell 48
6.1.3.2 4-Bit ALU 48
6.1.4 GDI 1-Bit ALU 48
6.1.4.1 GDI 1-Bit ALU Schematic 48
6.1.4.2 GDI 1-Bit ALU Layout 49
6.1.4.3 GDI 1-Bit ALU Output 49
6.1.5 GDI 4-Bit ALU 50
6.1.5.1 GDI 4-Bit ALU Schematic 50
6.1.5.2 GDI 4-Bit ALU Layout 50
6.1.5.3 GDI 4-Bit ALU Output 51
6.2.1 Modified GDI 1-Bit ALU 51
6.2.1.1 Modified GDI 1-Bit ALU Schematic 51
6.2.1.2 Modified GDI 1-Bit ALU Layout 52
6.2.1.3 Modified GDI 1-Bit ALU Output 52
6.2.2 Modified GDI 4-Bit ALU 53
6.2.2.1 Modified GDI 4-Bit ALU Schematic 53
6.2.2.2 Modified GDI 4-Bit ALU Layout 53
6.2.2.3 Modified GDI 4-Bit ALU Output 54

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 LIST OF TABLES

CHAPTER TOPIC PAGE NO

NO
4.2 Basic functions using GDI cell 20
5.5 Logic levels 32
5.5.3 Basic gates 35
6.3.1 Comparison of 1-Bit ALU 54
6.3.2 Comparison of 4-Bit ALU 55

xi
 LIST OF ABBREVIATIONS
 VLSI- Very Large Scale Integration
 ALU- Arithmetic and Logical Unit
 CMOS- Complementary Metal Oxide Semiconductor
 DSCH- Digital Schematic
 FPGA- Field Programmable Gate Array
 HDL- Hardware Description Language
 PLD- Programmable Logic Devices
 PROM- Programmable Read Only Memory
 CLB - Configurable Logic Blocks
 LUT- Look Up Table
 IC- Integrated Circuit
 IEEE- Institute of Electrical and Electronics Engineers
 VHSIC- Very High Speed Integrated Circuits
 VHDL- Very High Speed Integrated Circuit Hardware Description Language
 ASIC-Application Specific Integrated Circuit
 SOC-System On Chip
 CLB-Configurable Logic Blocks
 RAM- Random Access Memory
 MOS-Metal Oxide Semiconductor
 GA- Gate Array
 SOG- Sea Of Gates
 PLA- Programmable Logic Array
 DRC-Design Rule Check
 CPL-Complementary Pass transistor Logic
 GDI-Gate Diffusion Input
 CPU-Central Processing Unit
 DSP-Digital Signal Processors
 AOI-And Or Invert
 OAI-Or And Invert

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 CHAPTER-1

INTRODUCTION

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 CHAPTER-1

INTRODUCTION

The increasing demand for low-power very large scale integration (VLSI) can be
addressed at different design levels, such as the architectural, circuit, layout, and the
process technology level . At the circuit design level, considerable potential for power
savings exists by means of proper choice of a logic style for implementing combinational
circuits. This is because all the important parameters governing power dissipation
switching capacitance, transition activity, and short-circuit currents are strongly influenced
by the chosen logic style. Depending on the application, the kind of circuit to be
implemented, and the design technique used, different performance aspects become
important, disallowing the formulation of universal rules for optimal logic styles.
Investigations of low-power logic styles reported in the literature so far, however, have
mainly focused on particular logic cells, namely full-adders, used in some arithmetic
circuits. In this paper, these investigations are extended to a much wider set of logic gates,
and with that, to arbitrary combinational circuits. The power dissipation characteristics of
various existing logic styles are compared qualitatively and quantitatively by actual logic
gate implementations and simulations under realistic circuit arrangements and operating
conditions . Investigations of sequential elements, such as latches and flip-flops, were not
included in this work, but can be found elsewhere in the literature .
The increasing speed and complexity of today’s designs implies a significant
increase in the power consumption of very-large-scale integration circuits. Voltage is
increased to attain higher speed of operation with the penalty of increased power
consumption. To meet this challenge, researchers have developed many different design
techniques to reduce power. CMOS technology scaling has now moved to a power
constrained condition. Circuit techniques to reduce chip standby leakage have become a
key enabler. Scaling is a tradeoff between performance and leakage. One of the key
features that led to the success of complementary metal-oxide semiconductor technology
was its intrinsic low-power consumption . This meant that circuit designers and electronic
design automation (EDA) tools could afford to concentrate on maximizing circuit
performance and minimizing circuit area. Another interesting feature of CMOS technology
is its nice scaling properties, which has permitted a steady decrease in the feature size,
allowing for more and more complex systems on a single chip, working at higher clock
frequencies . In fact, power consumption is regarded as the limiting factor in the continuing

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scaling of CMOS technology.

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 The tremendous growth in battery - operated and power-sensitive applications has
created a global demand for low-power semiconductors. Today’s power-sensitive
designers face stricter system power limits, specifications, and standards that put a cap on
the total power consumed by the system. Simultaneously, for these applications, the
demand for increased features, performance, and complexity continues to grow, but at the
expense of power. The art of power analysis and optimization of integrated circuits are
used to be a narrow specialty in analog circuit design. The newer generations of
semiconductor processing technologies present more stringent requirements to the power
dissipation of digital chips due to increased device density, speed and complexity. Power is
the rate at which energy is delivered or exchanged. In a VLSI chip, electrical energy is
converted to heat energy during operation. The rate at which energy is taken from the
source and converted in to heat is the power dissipation. Heat energy has to be completely
dissipated from the system in order to avoid increase in chip temperature, which can cause
permanent or temporary circuit failure.
1.1. Need For Low Power
As the demand for high speed, Low power consumption and high performance
continues to grow each year, there is a need to scale the devices to smaller dimensions. As
the market trend moves towards a greater scale of integration, the move toward a reduction
in supply voltage also have the advantage of improving the reliability of the chip. As the
complexity of the chip increases design problems occurs such as layout of a chip and
simulation for the circuit and these are all becomes more intense. Power consumption is
regarded as the limiting factor in the present technology. High power supply affects the
temperature and further influences the cooling cost of the chip. If the temperature increases
it directly reflects the environmental problems. Noise and reliability is the one more big
issue in the field of high power consumption devices. With all this, high power
consumption will defiantly degrade Battery life of the electronics devices.
1.2 NEED FOR LOW POWER VLSI CHIPS
As the scale of integration improves, more transistors, faster and smaller than their
predecessors, are being packed into chip. This leads to the steady growth of the operating
frequency and processing capacity per chip, resulting in increased power dissipation. The
Moore’s law predicts the growth rate of integrated circuits. New generation of processing
technology are being developed at a faster rate than Moore’s law. A need for low power
VLSI chips arises from such evolution forces integration circuits. Another factor that fuels

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the needs for low power chips is the increased market demand for portable consumer
electronics powered by batteries. The craving for smaller, lighter and more durable
electronic products indirectly translates to low power requirements. Ironically, high
performance computing system characterized by large power dissipation also drives the
low power needs. Power dissipation has a direct impact on the packaging cost of the chip
and the cooling cost of the system. Another major demand for low power chips and
systems comes from environmental concerns. Since electricity generation is a major source
of air pollution, insufficient energy usage in computing equipment indirectly contributes to
environmental Pollution.
A. Design Types
The VLSI low power design problems can be broadly classified into two types such
as Analysis and Optimization. Analysis problems are concerned about the accurate
estimation of the power or energy dissipation at different phases of the design process. The
purpose is to give assurance that the power consumption specifications are not violated.
The accuracy of analysis depends on the availability of design information. Here, better
accuracy is demanded and longer analysis time is allowed. Analysis techniques also serve
as the foundation of design optimization. Optimization is the process of generating the best
design, given an optimization goal, without violating design specifications. An automatic
design optimization algorithm requires a fast analysis engine to evaluate the merits of
design choices.
A design to apply a particular low power technique often tradeoffs from different
sources pulling in various directions. The major criteria to be considered are the impact to
the circuit delay, which affects the performance and throughput of the chip, and the chip
area, which directly translates to manufacturing costs. Other factors of the chip design such
has design cycle time, testability, quality, reliability, reusability, risk etc may all be
affected by a particular design to achieve low power requirement.
B. Introduction to FPGA
The Field Programmable Gate-Array is the most powerful programmable integrated
circuit. It consists of an array of logic blocks that can be connected by general
interconnection resources. FPGAs are programmed using a logic circuit diagram or a
source code in a hardware description language (HDL). The FPGA industry sprouted from
programmable read only memory (PROM) and programmable logic devices (PLDs).
Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first
commercially viable field programmable gate array in 1985 – the XC2064. The

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XC2064 had

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programmable gates and programmable interconnects between gates, the beginnings of a
new technology and market. The XC2064 boasted a mere 64 configurable logic blocks
(CLBs), with two 3-input lookup tables. The FPGA is an integrated circuit that contains
many (64 to over 10,000) identical logic cells that can be viewed as standard components.

Figure 1.2 Internal Block diagram of FPGA

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 CHAPTER -2
LITERATURE SURVEY

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 CHAPTER-2

LITERATURE SURVEY

2.1 Design of Low Power ALU using 8T FA and PTL Based Mux Circuits
In this paper they proposed an ALU using novel 8T FA and pass transistor logic
based multiplexers. A 4:l mux and a 2:l mux were used to design an ALU. FA is an
essential component for designing all types of processors like digital signal 5 processors
(DSP), microprocessors, etc. In existing method, FA and multiplexers were designed using
transmission gate logic. To reduce the number of transistors, multiplexers were designed
using pass transistor logic while FA is designed using 8 transistors logic in the
implementation of ALU. The power and the area were greatly reduces to more than 70%
compared to the existing method.
2.2 A Review Paper on 3T XOR cells and 8T Adder Design in Cadence 180nm
This paper gives a review of already existing 3T XOR cells and provides an
optimized value of width/length (W/L) on the basis simulation results obtained which
helped to improve the driving capability as to improve the threshold loss problems present
in the existing designs of 3T XOR cells. However, the driving capability obtained is not
sufficient for large circuits like multipliers. From their best improved version of 3T XOR
cell obtained, they designed a FA circuit. They implement all the basic circuits and their
improved versions in Cadence Virtuoso for 180nm technology and 1.8V source.
2.3 Design of Low Power High Speed ALU Using Feedback Switch Logic
A new dynamic like static circuit family called Feedback-Switch Logic (FSL) has
been proposed in this paper. The FSL is suitable for high speed and low power because it
offers fast switching, reduced capacitance and input-switching dependent activity factor
without the need of clock connection. This paper presents the design of low power high
speed 32-bit ALU based on static CMOS and FSL logics at 90nm CMOS process in
CADENCE design tool. Simulation results shows that the design of ALU using FSL
achieves 14% reduction in delay but at the cost of 8% increased power consumption
compared to static CMOS logic. This ALU combines adder, shifter and logical units which
are having low power consumption, less delay and uses lesser area. ALU using FSL
attained low power and high speed by optimal sizing of transistors.
2.4 Low Power Sub-Threshold Asynchronous QDI Static Logic Transistor Level
Implementation (SLTI) 32-bit ALU In, they proposed an asynchronous-logic
Quasi- Delay-Insensitive (QDI) static logic transistor-level implementation (SLTI)

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approach for

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low power sub-threshold operation. The approach is implemented to design 32-bit
pipelined ALUs, the primary computation core for microprocessors, and benchmarked
against the reported Pre-Charged Half-Buffer (PCHB). There are two key attributes in this
proposed design. First, the proposed SLTI ALU design can perform dynamic voltage
scaling seamless by only changing the Vdd from nominal (1V) to sub threshold (~0.2V)
regions for high speed/low power operation. Second, the ALU achieves ultra-low power
dissipation (3.5μW) at the lowest Vdd point (~0.15V). For fair of comparison, both
implemented ALUs have identical functionality and functional blocks, are implemented
using the same 65nm CMOS process. Based on the simulations, the minimum energy point
occurs at Vdd of 0.2V for SLTI-based ALU and at Vdd of 0.3V for PCHB based ALU.
The SLTI-based ALU have
~93% and ~89% lower energy on the arithmetic and logic operations respectively from
Vdd of 1V to Vdd of 0.2V. At Vdd of 0.2V, with 9 MHz input switching rate, the
asynchronous ALU based on their proposed SLTI approach dissipates ~51% and ~44%
lower power than the reported PCHB counterpart on the arithmetic and logic operations
respectively.
2.5 Design of a Low Power, Sub-Threshold, Asynchronous ALU Using a Bidirectional
Adder
A novel asynchronous bidirectional ALU is introduced in this paper. The adder in
the proposed design is a ripple carry adder with the bidirectional characteristic. The ALU
is designed with asynchronous dual rail circuit style. Several ALUs with sizes ranging
from 4 bits to 32 bits were built. Their power and performance metrics were compared
with the conventional ALUs built with the fast adders designed with dynamic logic style.
Significant power reduction with the sub-threshold operating voltage is achieved. Also the
design is compared with the ALU design proposed for reversible quantum computers in the
CMOS context to show the logic efficiency of 7 the proposed design around 30 % in area.
Power reduction of 9 - 26% was achieved for the addition operation and 19.5 - 75.1% for
the logical operation on the proposed 32 bit ALU, compared to the conventional dynamic
logic based ALU operated over the voltage range 0.2-0.3V.
2.6 Energy – Efficient, High Performance Circuits for Arithmetic Units
This paper present a new full adder structure based on complementary pass
transistor logic (CPL) which is faster and more energy efficient than the existing structures.
They also proposed a new technique of implementing multiplier circuit using
decomposition logic which improves speed and reduces power consumption by reducing

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the spurious transition on international nodes. There is substantial improvement in the
performance of the multiplier structure with the combination of the new adder structure
and the decomposition logic. The

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proposed circuits were implemented using TSPICE for simulation in TSMC 180nm
technology.
2.7 A Low Power 10-transistor Full Adder Cell for Embedded Architecture
This paper has proposed a full adder cell using 10T which has the advantage of low
power consumption and high operating speed. It occupied a small area due to the small
transistor count. The objective of low power is achieved at the circuit level by reducing the
number of internal node capacitances by eliminating direct paths between the supply
voltage and the ground, by maintaining low switching activity in the circuit. The proposed
cell is compared with standard transmission gate adder cell and a 16T adder cell and
characterized by its low power consumption compared to other adder cells. Using the
proposed adder cell, one 4-bit multiplier is constructed and used as a test vehicle to check
the performance of the new proposed design in embedded architecture. The circuit is
developed using 0.35μm CMOS technology using Cadence development tools and
simulated using HSPICE. The circuit consumed 75.2μW at a frequency of 500 MHz.
2.8 An Implementation of 1-bit Low Power Full Adder Based on Multiplexer and
Pass Transistor Logic
This paper presents the design of low power full adder based on XOR pass
transistor logic and transmission gate for carry. They have not connected power supply
rail directly, instead of that inputs are given directly to reduce the transition activity and
charge recycling capability and this result in great amount of reduction in power
consumption. The proposed 14T full adder has been developed using Tanner SPICE
simulation. Based on their result, there is saving of power supply by the factor of 30% as
compared to 10T full adder and a reduction in power by 26% as compared to the
conventional 28T CMOS adder.
2.9 A Fast ALU Design in CMOS for Low Voltage Operation
In this paper, a high-speed 4-bit ALU has been designed for 1V operation to
demonstrate the usefulness of the back-gate forward substrate bias (BGFSB) method in
1.2μm n-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is
capable of performing eight operations which are four arithmetic and four logical
operations. The BGFSB has been limited to |0.4|V. The delay time measurements are
taken for all operations from the SPICE simulations with and without the back-gate
forward substrate bias.

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 CHAPTER -3

PROPOSED APPROACH

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 CHAPTER -3

PROPOSED APPROACH

In this paper the MGDI technique is used to realize the circuits. Components

required to design the ALU as follows:

A. 2x1 Multiplexer
A multiplexer is a digital switch which chooses the output from several inputs
based on a select signal , shown in Figure 3.1 , 2x1 multiplexer consists of 2 transistors.

Figure 3.1 MGDI Based 2x1 Multiplexer

B. 4x1 Multiplexer
Using the previously discussed 2x1 multiplexer a 4x1 multiplexer is realized as
shown in Figure 3.2.,it consists of only 6 transistors.

Figure 3.2 MGDI GDI 4x1 Multiplexer

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 B. Full Adder
A full adder is a combinational circuit that performs the arithmetic sum of three
input bits. It consists of three inputs and two outputs. The adder cell used in this design
realized using full-swing AND, OR, and XOR gates. This design was has low power
operation, it has the lowest delay and with some modifications it performs the logic
operations such as AND,OR,XOR, & XNOR as well, these modifications will save large
area of the ALU design

Figure 3.3 Full Adder cell for ALU

VI. DESIGN OF
ALU
An ALU is a critical component in the Central Processing Unit (CPU) of any
computer; even the simplest microprocessors contain one. It performs arithmetic
operations such as addition, subtraction, increment, decrement and logic operations such as
AND, OR, XOR and XNOR .

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 Figure 3.4 Schematic of 1-Bit ALU Stage using GDI

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 The figure 3.5 shows the 4-bit ALU design using GDI logic, 4-bit ALU consists of
three selection bits, eight 4×1 MUX, eight 2×1 MUX & four processing units.

Figure 3.5 Schematic of 4-Bit ALU Stage using GDI

The proposed design of the 4-Bit Arithmetic Logic Unit consists of 4 stages, each
stage is an 1-Bit ALU block realized using the previously designed circuits as follows:
Each 1-Bit ALU stage consists of two 2x1 multiplexers, two 4x1 multiplexers and one full
adder cell, this design requires 48 transistors as depicted in Fig.3.5. Any desired operation
can be performed based on the selection line S0, S1, S2 code; Table II summarizes the
truth table of the proposed ALU.
The 4x1 multiplexer at the input is responsible for the selection of B input based on
the values of S0 and S1 selection lines it selects from logic 1, B, B' And logic 0 to perform
the Decrement, Addition, Subtraction and the Increment operations respectively, S2
chooses between the arithmetic and the logic operations.

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 Figure 3.6 Schematic of 1-Bit ALU Stage using MGDI

To realize the 4-Bit ALU , four stages were used as shown in Figure 3.6, While the
carry input of ALU0 connected to selection line S1 to obtain logic 1 which needed for
subtraction and increment operations, however the other values don’t affect the results of
the logic operations.

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 Figure 3.7 Schematic of 4-Bit ALU Stage using MGDI

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 CHAPTER-4

EXISTING SYSTEM

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 CHAPTER-4

EXISTING SYSTEM

The existing 4-bit ALU is designed using 3T XNOR Gates and multiplexers. The
total numbers of transistors used are 88 when compared to 96 Transistors using GDI
Technique or by using only 2T XOR gates. These further results in lower power
dissipation. Drawbacks:
The existing design uses 3T XNOR gates and multiplexers.
Remedy:
1. Use GDI Multiplexer based design for ALU.
2. Use transistor sizing for reducing power dissipation.

4.1 POWER DISSIPATION TYPES

A. Static Power Dissipation
Static power dissipation related to the logical states. Leakage current is the only
source of static power dissipation. Leakage current exists as a natural phenomenon of the
semiconductor device operation.
Static power is given by,
Pstat = Vcc x Icc (1)
Where,
Vcc – Supply Voltage
Icc – Current into the device which is a sum of leakage currents
Two major source of leakage current are:
• Reverse bias PN junction current
• Sub threshold channel conduction current

B. Dynamic Power Dissipation

This is caused by the switching activity of the circuit. The source of dynamic power
dissipation is charging and discharging of capacitance. The capacitance forms due to
parasitic effects of inter connection wires and transistors.
Dynamic power is given by,
Pdyna = CTV2 f (2)
Where,
V – Supply Voltage

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f – Input Signal Frequency
CT – Total Capacitance
Effect
C. Basic types of low power design
• Reduce Switching Voltage:
The method used to reduce switching voltage is to reduce the operating voltage of
the circuit. Other method to reduce voltage swing by well known circuit techniques such as
charge sharing, transistor threshold voltage etc. There are many trade off to be considered
in voltage reduction. The main reason is that the threshold voltage of the transistor does not
scale accordingly with the operating voltage to avoid excessive leakage current.
• Reduce Capacitance:
Signals with high switching frequency should be routed with minimum parasitic
capacitance to conserve power. Conversely nodes with large parasitic capacitance should
not be allowed to switch at high frequency. Capacitance reduction can be achieved at most
design abstraction level materials, circuit techniques, transistor sizing, architectural
transformation and alternative computation algorithms.
• Reduce Switching Frequency:
The techniques are often applied to logic level design. Reductions of switching
frequency also have the side effects of improving the reliability of the chip as some failure
mechanism is related to switching frequency. One effective method of reducing switching
frequency is to eliminate logic switching that is not necessary for computation. Other
method involves logic implementation since there are many ways to design a logic network
to perform an identical function.
• Reduce Static Current:
Leakage power problem mainly appears in very low frequency circuits or ones with
sleep modes. Leakage reduction techniques are applied at low level design abstraction such
as process, device and circuit design. Static current can be reduced by transistor sizing,
layout techniques and careful circuit designing. Circuit modules that consume static current
should be turned off if not used.

D. Arthimetic & Logical Unit:

The arithmetic and logic unit (ALU) performs all arithmetic operations (addition,
subtraction, multiplication, and division) and logic operations. Logic operations test
various conditions encountered during processing and allow for different actions to be

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taken based on the results. The data required to perform the arithmetic and logical
functions are inputs

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from the designated CPU registers and operands. The ALU relies on basic items to perform
its operations.

Figure 4.1 Traditional 1 Bit ALU

The 4-bit ALU is designed using GDI based multiplexer design. Further the design is
optimized for power dissipation using transistor sizing
4.2 GATE DIFFUSION INPUT TECHNIQUE
Main concept of GDI is that gate of PMOS and NMOS is diffused. In these days in
digital circuits design, for a digital circuit designer’s a high speed, high throughput and
small silicon area and also low- power consumption in digital circuit is most essential
things for a designers. GDI is such a technique that we can use for design of low power
digital circuits. And it is also a novel design method of a low power digital circuit. In GDI
cell using only two transistors allows implementation of a wide range of complex logic
functions. In GDI by using only two transistor (PMOS AND NMOS) many function such
as AND, OR, XOR and XNOR can be implemented.GDI method is suitable for designing
of fast, low power circuits, using reduced number of transistor as compared to CMOS
techniques and also improving power characteristics. As compared to CMOS, fast, low
power circuits can be designed bu using gdi technique. The main advantage of GDI is that
it require less number of transistors as compared to CMOS. Therefore area is reduced.
Therefore delay is less and speed is increased. Morgenshtein has proposed basic GDI cell
shown in Fig 4.1.
Approach for designing low power digital combinational circuit is a GDI
Technique. GDI technique is basically two transistor implementation of complex logic
functions which provides in-cell swing restoration under certain operating condition. This

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approach leads to reduction in power consumption, propagation delay and area of digital
circuits. while having

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low complexity of logic design. An important feature of GDI cell is that the source of the
PMOS in a GDI cell is not connected to VDD and the source of the NMOS is not
connected to GND. Drain terminals of the two transistors are taken as output. Source
terminal of Pmos is acting as one input, and Source of Nmos is acting as another input.
Therefore GDI cell gives two extra input pins for use which makes the GDI design more
flexible than CMOS design.

Fig.4.2 Basic GDI Cell

There are three inputs in a GDI cell - G (common gate input of NMOS and PMOS),
P (input to the source/drain of PMOS) and N (input to the source/drain of NMOS).Bulks of
both NMOS and PMOS are connected to N and P respectively. Table 4.2 shows different
logic functions implemented by GDI logic based on different input values. So, various
logic functions can be implemented with less power and high speed with GDI technique as
compared to conventional CMOS design.

Table 4.2 Basic functions using GDI cell

It can be seen that large number of functions can be implemented using the basic
GDI cell. MUX design is the most complex design which requires 8-12 transistors with the
traditional CMOS, that can be implemented with GDI, which requires only 2 transistors.
Many functions can be implemented efficiently by GDI with minimum number of
transistor. Function1 and Function2 are universal set for GDI, and consists of only two
transistors, compared to NAND and NOR. When compared to CMOS, the GDI

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Technique use less

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transistors and power dissipation is also less. A new technique of low power digital circuit
design is a GDI (Gate Diffusion Input). Power consumption, delay and area of digital
circuits is reduced by This technique, maintains low complexity of logic design. Since GDI
cell has no power supply connected to it, there will be a voltage drop at the output. This
drop will be negligible for small circuits. Implementations of GDI circuits in SOI or twin-
well CMOS processes are expected to supply more power- delay efficient design.
Due to the use of a complete cell library with reduced transistor count. Because of
less number of transistors, the switching is reduced and hence there will be a less power,
delay and also reduced area. Because of the less number of transistors the switching node
capacitance will be reduced that results in reduction of dynamic power 1.2 ALU An ALU
is one of the main components of a microprocessor.ALU also contribute to one of the
highest power- density locations on the processor, as it is clocked at the highest speed and
is busy mostly all the time which results in thermal hotspots and sharp temperature
gradients within the execution core. Therefore, this motivate us strongly for a energy
efficient ALU designs that satisfy the high- performance requirements, while reducing
peak and average power dissipation. Basically ALU is a combinational circuit that
performs arithmetic and logical operations on a pair of n bit operands. Arithmetic Unit
Employing fast and efficient adders in arithmetic logic unit will aid in the design of low
power high performance system. In this paper Arithmetic Unit consists of adder and
substractor and logical unit consists of AND, OR.
4.3 ALU USING GDI TECHNIQUE

Fig 4.3: 4 bit ALU

ALU can perform various logic operations like NOT, AND, OR, NAND, NOR,
XOR, XNOR etc. For these operations a special unit is made called as Logical Unit. This

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Logic Unit performs all logic operations asked to perform. A MUX operated by select
lines, for which particular logic operation to perform, is used inside this logic block

4.4 MULTIPLEXER
Multiplexer is a digital switch. The multiplexer has numbers of input data lines and
one output line. The selection of a particular input line is controlled by a set of selection
line. There are ‘2n’ input lines and ‘n’ selection lines whose bit combinations determine
which input is selected. Fig 4.3 shows implementation of basic 2x1multiplexer using GDI
cell. The 4x1 multiplexer has four inputs, two selection lines and one output. Depending on
thetwo selection lines, one output is selected at a time among the four input lines. Fig. 4.4.1
shows implementation of 4x1multiplexer using GDI cell.

Fig. 4.4.1 2x1 Multiplexer using GDI technique

Fig 4.4.2 4x1 Multiplexer using GDI technique

XOR Gate The main building block of full adder circuit is XOR gate which gives
sum output. So the overall performance of full adder circuit can be improved by optimizing
XOR gate.Fig.4.4.2 shows the implementation of XOR gate using GDI technique . It uses
less number of transistors as compared to conventional design of XOR gate using CMOS
logic Units.

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 Fig. 4.4.3 GDI Based XOR Gate Full Adder
The Full Adder circuit adds three one-bit binary numbers(A, B & C) and outputs
two one-bit binary numbers, a sum(S) and a carry (Cout). The full adder is usually a
component in cascade of adders, which add 4, 8, 16 etc. binary numbers. Implementation
of full adder circuit using GDI technique which is a basic building block of arithmetic and
logic unit has been shown in Fig. 4.4.3.

Fig.4.4.4 GDI based 1-bit full adder cell

4.5 DESIGN OF ARITHMETIC AND LOGIC UNIT (ALU)
An arithmetic logic unit (ALU) is a fundamental building block of the Central
Processing Unit (CPU) of a computer and even the simplest microprocessors contain one.
It is responsible for performing arithmetic and logic operations such as addition,
subtraction, increment, and decrement, logical AND, logical OR, logical XOR and logical
XNOR. ALU consists of eight 4x1 multiplexers, four 2x1multiplexers and four full adders.
The 4-bit ALU is designed in 250nm, n-well CMOS technology. When logic ‘1’andlogic
‘0’ are applied as an input INCREMENT and DECREMENT operations takes place
respectively. An INCREMENT operation is analyzed as adding ‘1’ to the addend and
DECREMENT is seen as a subtraction operation .

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 CHAPTER-5
VLSI DESIGN

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 CHAPTER-5
VLSI DESIGN
5.1 INTRODUCTION

The electronics industry has achieved a phenomenal growth over the last two
decades, mainly due to the rapid advances in integration technologies, large-scale systems
design - in short, due to the advent of VLSI. The number of applications of integrated
circuits in high-performance computing, telecommunications, and consumer electronics
has been rising steadily, and at a very fast pace. Typically, the required computational
power (or, in other words, the intelligence) of these applications is the driving force for the
fast development of this field. Gives an overview of the prominent trends in information
technologies over the next few decades. The current leading-edge technologies (such as
low bit-rate video and cellular communications) already provide the end-users a certain
amount of processing power and portability. This trend is expected to continue, with very
important implications on VLSI and systems design. One of the most important
characteristics of information services is their increasing need for very high processing
power and bandwidth (in order to handle real-time video, for example). The other
important characteristic is that the information services tend to become more and more
personalized (as opposed to collective services such as broadcasting), which means that
the devices must be more intelligent to answer individual demands, and at the same time
they must be portable to allow more flexibility/mobility.

Very-large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistor-based circuits into a single chip. VLSI began in the
1970s when complex semiconductor and communication technologies were being
developed. The microprocessor is a VLSI device. The term is no longer as common as it
once was, as chips have increased in complexity into the hundreds of millions of
transistors. VLSI stands for "Very Large Scale Integration". This is the field which
involves packing more and more logic devices into smaller and smaller areas. Thanks to
VLSI, circuits that would have taken board full of space can now be put into a small space
few millimeters across! This has opened up a big opportunity to do things that were not
possible before. VLSI circuits are everywhere your computer, your car, your brand new
state-of-the-art digital camera, the cell-phones, and what have you. All this involves a lot
of expertise on many fronts within the same field, which we will look at in later sections.

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 VLSI has been around for a long time, there is nothing new about it ... but as a side
effect of advances in the world of computers, there has been a dramatic proliferation of
tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the
capability of an IC has increased exponentially over the years, in terms of computation
power, utilization of available area, yield. The combined effect of these two advances is
that people can now put diverse functionality into the IC's, opening up new frontiers.
Examples are embedded systems, where intelligent devices are put inside everyday objects,
and ubiquitous computing where small computing devices proliferate to such an extent that
even the shoes you wear may actually do something useful like monitoring your heartbeats.
Verilog was developed at a time when designers were looking for tools to combine
different levels of simulation. In the early 1980s, there were switch-level simulators, gate-
level simulators, functional simulators (often written ad-hoc in software) and no simple
means to combine them. Further, the more-widespread, traditional programming languages
themselves were/are essentially sequential and thus "semantically challenged" when
modeling the concurrency of digital circuitry.

Verilog was created by Phil Moore in 1983 at Gateway Design Automation and the
first simulator was written a year later. It borrowed much from the existing languages of
the time: the concurrency aspects may be seen in both Modula and (earlier) Simulate; the
syntax is deliberately close to that of C; and the methods for combining different levels of
abstraction owe much to Hilo.

In 1989, Gateway Design Automation (and rights to Verilog) was purchased by

Cadence who put Verilog in the public domain in the following year. This move did much
to promote the use of Verilog since other companies were able to develop alternatives tools
to those of Cadence which, in turn, allowed users to adopt Verilog without dependency on
a single (primarily workstation-tool) supplier. In 1992, work began to create an IEEE
standard (IEEE-1364) and in December 1995 the final draft was approved. Thus Verilog
has become an n international standard - which will further increase its commercial
development and use. At present, there is standards activity to extend Verilog beyond
purely digital circuits. This includes Verilog-MS for "mixed signal specification" and
Verilog A for "analog" design; the latter was recently approved (June 1996) by the board
of Open Verilog International and is now under consideration by the IEEE. In addition,
work is underway to automate the proof of "equivalence behavioral and synthesizable

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specifications".

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 While Verilog emerged from developments within private companies, its main rival
came from the American Department of Defense (DOD). In 1981, the DOD sponsored a
workshop on hardware description languages as part of its Very High Speed Integrated
Circuits (VHSIC) program, and the outcome formed a specification for the VHSIC
hardware description language (VHDL) in 1983. There is, of course, the question as to
which language is better. And this, of course, is a hard question to answer without causing
excitement and rebuttals from the marketing departments of the less preferred language.
However, the following points featured in a recent debate in the VHDL and Verilog news
groups.

The main factor is the language syntax - since Verilog is based on C and VHDL is
based on ADA. Verilog is easier to learn since C is a far simpler language. It also produces
more compact code: easier both to write and to read. Furthermore, the large number of
engineers who already know C (compared to those who know ADA) makes learning and
training easier. VHDL is very strongly typed, and allows programmer to define their own
types although, in practice, the main types used are either the basic types of the language
itself, or those defined by the IEEE. The benefit is that type checking is performed by the
compiler which can reduce errors; the disadvantage is that changing types must be done
explicitly.

5.2 VERILOG ADVANTAGES OVER VHDL

It allows switch-level modeling - which some designers find useful for exploring
new circuits. It ensures that all signals are initialized to "unknown" who ensures that all
designers will produce the necessary logic to initialize their design - the base types in
VHDL initialize to zero and the "hasty" designer may omit a global reset.

5.3 VLSI DESIGNS CLASSIFICATION

There are THREE CATEGORIES in today`s VLSI domain they are

5.3.1 Analog:

Small transistor count precision circuits such as Amplifiers, Data converters, filters,
Phase locked loops, Sensors etc.

5.3.2 ASICS or Application Specific Integrated Circuits:

Progress in the fabrication of IC's has enabled us to create fast and powerful circuits

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in smaller and smaller devices. This also means that we can pack a lot more of
functionality

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into the same area. The biggest application of this ability is found in the design of ASIC's.
These are IC's that are created for specific purposes - each device is created to do a
particular job, and do it well. The most common application area for this is DSP - signal
filters, image compression, etc. To go to extremes, consider the fact that the digital
wristwatch normally consists of a single IC doing all the time-keeping jobs as well as extra
features like games, calendar, etc.

5.3.3 SOC or Systems on a chip:

These are highly complex mixed signal circuits (digital and analog all on the same
chip). A network processor chip or a wireless radio chip is an example of a SOC.

5.4 VLSI DESIGN STYLES

Several design styles can be considered for chip implementation of specified

algorithms or logic functions. Each design style has its own merits and shortcomings, and
thus a proper choice has to be made by designers in order to provide the functionality at
low cost.

5.4.1 FIELD PROGRAMMABLE GATE ARRAY (FPGA)

Fully fabricated FPGA chips containing thousands of logic gates or even more,
with programmable interconnects, are available to users for their custom hardware
programming to realize desired functionality. This design style provides a means for fast
prototyping and also for cost-effective chip design, especially for low-volume applications.
A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of
configurable logic blocks (CLBs), and programmable interconnect structures. The
programming of the interconnects is implemented by programming of RAM cells whose
output terminals are connected to the gates of MOS pass transistors. A more detailed view
showing the locations of switch matrices used for interconnect routing.

A simple CLB (model XC2000 from XILINX) It consists of four signal input
terminals (A, B, C, D), a clock signal terminal, user-programmable multiplexers, an SR-
latch, and a look-up table (LUT). The LUT is a digital memory that stores the truth table of
the Boolean function. Thus, it can generate any function of up to four variables or any two
functions of three variables.

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 CLB is configured such that many different logic functions can be realized by
programming its array. More sophisticated CLBs have also been introduced to map
complex functions. The typical design flow of an FPGA chip starts with the behavioral
description of its functionality, using a hardware description language such as VHDL. The
synthesized architecture is then technology-mapped (or partitioned) into circuits or logic
cells. At this stage, the chip design is completely described in terms of available logic cells.
Next, the placement and routing step assigns individual logic cells to FPGA sites (CLBs)
and determines the routing patterns among the cells in accordance with the net list.

Performance of the design can be simulated and verified before downloading the
design for programming of the FPGA chip. The programming of the chip remains valid as
long as the chip is powered-on or until new programming is done. In most cases, full
utilization of the FPGA chip area is not possible - many cell sites may remain unused.
The largest advantage of FPGA-based design is the very short turn-around time,
i.e., the time required from the start of the design process until a functional chip is
available. Since no physical manufacturing step is necessary for customizing the FPGA
chip, a functional sample can be obtained almost as soon as the design is mapped into a
specific technology.
The typical price of FPGA chips are usually higher than other realization
alternatives (such as gate array or standard cells) of the same design, but for small-volume
production of ASIC chips and for fast prototyping, FPGA offers a very valuable option.

5.4.2 GATE ARRAY DESIGN

In view of the fast prototyping capability, the gate array (GA) comes after the
FPGA. While the design implementation of the FPGA chip is done with user
programming, that of the gate array is done with metal mask design and processing. Gate
array implementation requires a two-step manufacturing process: The first phase, which is
based on generic (standard) masks, results in an array of uncommitted transistors on each
GA chip. These uncommitted chips can be stored for later customization, which is
completed by defining the metal interconnects between the transistors of the array Since
the patterning of metallic interconnects is done at the end of the chip fabrication, the turn-
around time can be still short, a few days to a few weeks. a corner of a gate array chip
which contains bonding pads on its left and bottom edges, diodes for I/O protection,
NMOS transistors and PMOS transistors for chip output driver circuits in the neighboring
areas of bonding pads, arrays of
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NMOS transistors and PMOS transistors, underpass wire segments, and power and ground
buses along with contact windows.

Magnified portion of the internal array with metal mask design (metal lines
highlighted in dark) to realize a complex logic function. Typical gate array platforms allow
dedicated areas, called channels, for inter cell routing. The availability of these routing
channels simplifies the interconnections, even using one metal layer only. The
interconnection patterns to realize basic logic gates can be stored in a library, which can
then be used to customize rows of uncommitted transistors according to the net list. While
most gate array platforms only contain rows of uncommitted transistors separated by
routing channels, some other platforms also offer dedicated memory (RAM) arrays to
allow a higher density where memory functions are required. The layout views of a
conventional gate array and a gate array platform with two dedicated memory banks.

With the use of multiple interconnect layers, the routing can be achieved over the
active cell areas; thus, the routing channels can be removed as in Sea-of-Gates (SOG)
chips. Here, the entire chip surface is covered with uncommitted NMOS and PMOS
transistors. As in the gate array case, neighboring transistors can be customized using a
metal mask to form basic logic gates. For intercell routing, however, some of the
uncommitted transistors must be sacrificed. This approach results in more flexibility for
interconnections, and usually in a higher density. The basic platform of a SOG chip is
shown in offers a brief comparison between the channeled (GA) vs. the channel less (SOG)
approaches.

5.4.3 STANDARD-CELLS BASED DESIGN

The standard-cells based design is one of the most prevalent full custom design
styles which require development of a full custom mask set. The standard cell is also called
the police. In this design style, all of the commonly used logic cells are developed,
characterized, and stored in a standard cell library. A typical library may contain a few
hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-
latches, and flip- flops. Each gate type can have multiple implementations to provide
adequate driving capability for different fan outs. For instance, the inverter gate can have
standard size transistors, double size transistors, and quadruple size transistors so that the
chip designer can choose the proper size to achieve high circuit speed and layout density.
The characterization of each cell is done for several different categories. It consists of

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  delay time vs. load capacitance

 circuit simulation model

 timing simulation model

 fault simulation model

 cell data for place-and-route ,mask data

To enable automated placement of the cells and routing of inter-cell connections,
each cell layout is designed with a fixed height, so that a number of cells can be abutted
side- by-side to form rows. The power and ground rails typically run parallel to the upper
and lower boundaries of the cell, thus, neighboring cells share a common power and
ground bus. The input and output pins are located on the upper and lower boundaries of the
cell. Notice that the NMOS transistors are located closer to the ground rail while the
PMOS transistors are placed closer to the power rail.
5.4.4 FULL CUSTOM DESIGN
Although the standard-cells based design is often called full custom design, in a
strict sense, it is somewhat less than fully custom since the cells are pre-designed for
general use and the same cells are utilized in many different chip designs. In a fuller
custom design, the entire mask design is done anew without use of any library. However,
the development cost of such a design style is becoming prohibitively high. Thus, the
concept of design reuse is becoming popular in order to reduce design cycle time and
development cost. The most rigorous full custom design can be the design of a memory
cell, be it static or dynamic. Since the same layout design is replicated, there would not be
any alternative to high density memory chip design. For logic chip design, a good
compromise can be achieved by using a combination of different design styles on the same
chip, such as standard cells, data-path cells and PLAs. In real full-custom layout in which
the geometry, orientation and placement of every transistor is done individually by the
designer, design productivity is usually very low - typically 10 to 20 transistors per day,
per designer.
In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost.
Exceptions to this include the design of high-volume products such as memory chips, high-
performance microprocessors and FPGA masters. The full layout of the Intel 486
microprocessor chip which is a good example of a hybrid full-custom design. Here, one
can identify four different design styles on one chip: Memory banks (RAM cache), data-
path units consisting of bit-slice cells, control circuitry mainly consisting of standard cells

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and PLA blocks.

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5.5 TOOL (DSCH& Export Micro wind)
The DSCH3 program is a logic editor and simulator. DSCH3 is used to validate the
architecture of the logic circuit before the microelectronics design is started. DSCH3
provides a user-friendly environment for hierarchical logic design, and fast simulation with
delay analysis, which allows the design and validation of complex logic structures. Some
techniques for low power design are described in the manual. DSCH3 also features the
symbols, models and assembly support for 8051 and 18f64. DSCH3 also includes an
interface to SPICE. The MICROWIND3program allows the student to design and simulate
an integrated circuit at physical description level. The package contains a library of
common logic and analog ICs to view and simulate. MICROWIND3includes all the
commands for a mask editor as well as original tools never gathered before in a single
module (2D and 3D process view, Verilog compiler, tutorial on MOS devices). You can
gain access to Circuit Simulation by pressing one single key. The electric extraction of
your circuit is automatically performed and the analog simulator produces voltage and
current curves immediately.

THE MOS DEVICE:

Logic Levels:

Three logic levels 0,1 and X are defined as follows:

Fig. 5.1 Logic Levels.

The MOS transistor is basically a switch. When used in logic cell design, it can be
on or off. When on, a current can flow between drain and source. When off, no current
flow between drain and source. The MOS is turned on or off depending on the gate
voltage. In CMOS technology, both N-channel (and NMOS) and P-channel MOS (or
PMOS) devices exist. The NMOS and PMOS symbols are reported below. The symbols
for the ground voltage source (0 or VSS) and the supply (1 or VDD).

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 Fig. 5.5 N-Channel and P-Channel.

The N-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In
contrary, the P-channel MOS device requires a logic value 0 to be on. When the MSO
device is on, the link between the source and drain is equivalent to a resistance. The order
of range of this ‘on’ resistance is 100Ω-5KΩ. The ‘off’ resistance is considered infinite at
first order, as its value is several MΩ.

THE TRANSMISSION GATE:

Both NMOS devices and PMOS devices exhibit poor performances when
transmitting one particular logic information. The NMOS degrades the logic level 1, the
PMOS degrades the logic level 0. Thus, a perfect pass gate can be constructed from the
combination of NMOS and PMOS devices working in a complementary way, leading to
improved switching performances. Such a circuit is called the transmission gate. In
DSCH3, the symbol may be found in the Advance menu in the palette. The transmission
gate includes one inverter, one NMOS and one PMOS.

Figure. 5.5.1 The Transmission Gate.

THE LOGIC INVERTER:

In this section, an inverter circuit is loaded and simulated. Click File→ Open in the
main menu. Select INV.SCH in the list. In this circuit are one button situated on the left
side of the design, the inverter and a led. Click Simulate→ Start simulation in the main
menu.

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 Fig.5.5.2 Logics of Inverter.
Now, click inside the buttons situated on the left part of the diagram. The result is
displayed on the leds. The red value indicates logic 1; the black value means logic 0. Click
the button Stop simulation shown in the picture below. You are back to the editor.

Click the chronogram icon to get access to the chronograms of the previous simulation.
As seen in the waveform, the value of the output is the logic opposite of that of the input.

Double click on the INV symbol; the symbol properties window is activated. In this
window appear the VERILOG description (left side) and the list of pins (right side). A set
of drawing options is also reported in the same window. Notice the gate delay (0.03ns in
the default technology), the fan out that represents the number of cells connected to the
output pin (1 cell connected), and the wire delay due to this cell connection (An extra
0.140ns delay).

BASIC GATES:

Table gives the corresponding symbol to each basic gate as it appears in the logic
editor window as well as the logic description. In this description, the symbol & refers to
the logical AND, | to OR, ~ to INVERT, NAND ^ to XOR.

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 Table:5.5.3 Basic gates

The Nand Gate:

The truth-table and logic symbol of the NAND gate with 2 inputs are shown below.
In DSCH select the NAND symbol in the palette, add two buttons and one lamp as shown
above. Add interconnects if necessary to link the button and lamps to the cell pins. Verify
the logic behavior of the cell.

Figure.5.5.3 Logic Symbol of the NAND gate.

THE CMOS INVERTER:

The CMOS inverter design is detailed in the figure below. Here the P-channel MOS
and the N-channel MOS transistors function as switches. When the input signal is logic 0
the NMOS is switched off while PMOS passes VDD through the output. When the input
signal is logic 1, the PMOS is switched off while the NMOS passes VSS to the output.

The fan-out corresponds to the number of gates connected to the inverter output.
Physically, a large fan-out means a large number of connections, that is a large load
capacitance. If we simulate an inverter loaded with one single output, the switching delay
is small. Now, if we load the inverter by several outputs, the delay and the power
consumption are increased due to the current needed to charge and discharge that

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capacitance.

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 Figure. 5.5.4 CMOS Inverter Circuits.

Inverter Simulation:

The inverter simulation is conducted as follows. Firstly, a VDD supply source

(1.2V) is fixed to the upper metal2 supply line, and a VSS supply source (0.0V) is fixed to
the lower metal2 supply line. The properties are located in the palette menu. Simply click
the desired property, and click on the desired location in the layout. Add a clock on the
inverter input node (The default node name clock1 has been changed into Vin) and a
visible property on the output node Vout.

Figure. 5.5.5 CMOS Inverter Simulation.

The command Simulate → Run Simulation gives access to the analog simulation.
Select the simulation mode Voltage vs. Time. The analog simulation of the circuit is
performed. The time domain waveform, proposed by default, details the evolution of the
voltages in1 and out1 versus time. This mode is also called transient simulation.

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 Figure.5.5.6 CMOS Inverter Wave forms.

5.6 SIMULATION ENVIRONMENT

The simulation parameters have been analyzed with the help of the Micro wind tool
and DSCH for the schematic verification.

5.6.1 DSCH (DIGITAL SCHEMATIC):

DSCH is software for logic design. Based on primitives, a hierarchical circuit can
be built and simulated. It also includes delay and power consumption evaluation. Silicon is
for 3D display of the atomic structure of silicon, with emphasis on the silicon lattice, the do
pants, and the silicon dioxide.

MOS as a Switch:

The MOS transistor is basically a switch. When used in logic cell design, it can be
on or off. When on, a current can flow between drain and source. When off, no current
flow between drain and source. The MOS is turned on or off depending on the gate
voltage. In CMOS technology, both N-channel (and NMOS) and P-channel MOS (or
PMOS) devices exist. The NMOS and PMOS symbols are reported below.

Fig. 5.6.1 Symbol of NMOS and PMOS.

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 The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In
contrary, the p-channel MOS device requires a logic value 0 to be on. When the MSO
device is on, the link between the source and drain is equivalent to a resistance. The order
of range of this ‘on’ resistance is 100Ω-5KΩ. The ‘off’ resistance is considered infinite at
first order, as its value is several MΩ.

Connecting Procedure:

Instantiate NMOS or PMOS transistors from the symbol library and place them in
the editor window. Connect Vdd and GND to the schematic. Connect input button and
output LED. The simulation output can be observed as a waveform after the application of
the inputs as above. Click on the timing diagram icon in the icon menu to see the timing
diagram of the input and output waveforms. The Verilog, Hierarchy and Net list window
appears. This window neither shows the Verilog representation of NOR gate. Click OK to
save the Verilog as a .txt file.

5.6.2 MICROWIND:

Micro wind is a tool for designing and simulating circuits at layout level. The tool
features full editing facilities (copy, cut, past, duplicate, move), various views (MOS
characteristics, 2D cross section, 3D process viewer), and an analog simulator. The Micro
wind program allows designing and simulating an integrated circuit at physical description
level. The package contains a library of common logic and analog ICs to view and
simulate.

Micro wind includes all the commands for a mask editor as well as original tools
never gathered before in a single module (2D and 3D process view, Verilog compiler,
tutorial on MOS devices). You can gain access to Circuit Simulation by pressing one
single key. The electric extraction of your circuit is automatically performed and the
analog simulator produces voltage and current curves immediately.

MOS Layout:
Micro wind is used to draw the MOS layout and simulate its behavior. The Micro
wind display window includes four main windows:.

1. The main menu

2. The layout display window

3. The icon menu

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 4. The layer palette.

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 The layout window features a grid, scaled in lambda (λ) units. The lambda unit is
fixed to half of the minimum available lithography of the technology. The default
technology is a CMOS 6-metal layers 0.12µm technology, consequently lambda is 0.06µm
(60nm). The palette is located in the lower right corner of the screen. A red color indicates
the current layer. Initially the selected layer in the palette is polysilicon. By using the
following procedure, you can create a manual design of the n-channel MOS.

1. Fix the first corner of the box with the mouse. While keeping the mouse button
pressed, move the mouse to the opposite corner of the box. Release the button. This
creates a box in polysilicon layer. The box width should not be inferior to 2 λ,
which is the minimum width of the polysilicon box.

2. Change the current layer into N+ diffusion by a click on the palette of the Diffusion
N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-
diffusion box at the bottom of the drawing as in Figure. 6.2 N-diffusion boxes are
represented in green. The intersection between diffusion and polysilicon creates the
channel of the nMOS device.

Fig. 5.6.2 Creating the N-channel MOS transistor.

Static MOS Characteristics:

The MOS size (width and length of the channel situated at the intersection of the
polysilicon gate and the diffusion) has a strong influence on the value of the current. In
Figure, the MOS width is 1.74µm and the length is 0.12µm. A high gate voltage (Vg
=1.2V) corresponds to the highest Id/Vdd curve. For Vg=0, no current flows. You may
change the voltage values of Vdd, Vg, Vs by using the voltage cursors situated on the right
side of the window. A maximum current around 1.5mA is obtained for Vg=1.2V,
Vdd=1.2V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3.

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 Fig. 5.6.3 N-Channel MOS characteristics.

Manual Layout Design:

Click the icon MOS generator on the palette. The following window appears. By
default the proposed length is the minimum length available in the technology (2 lambda),
and the width is 10 lambda. In 0.12µm technology, where lambda is 0.06µm, the
corresponding size is 0.12µm for the length and 0.6µm for the width. Simply click
Generate Device, and click on the middle of the screen to fix the MOS device. Click again
the icon MOS generator on the palette. Change the type of device by a tick on p-channel,
and click Generate Device. Click on the top of the NMOS to fix the PMOS device.

Fig.5.6.4 Selecting the PMOS device.

Connection between Devices:

Metal to Poly:

As polysilicon is a poor conductor, metal is preferred to interconnect signals and

supplies. Consequently, the input connection of the inverter is made with metal. Metal and
polysilicon are separated by an oxide which prevents electrical connections. Therefore, a

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box of metal drawn across a box of polysilicon does not allow an electrical connection. To
build an electrical connection, a physical contact is needed. The corresponding layer is
called "contact". You may insert a metal-to-polysilicon contact in the layout using a direct
macro situated in the palette.

Supply Connections:

The next design step consists in adding supply connections, that is the positive
supply VDD and the ground supply VSS. We use the metal2 layer (Second level of
metallization) to create horizontal supply connections. Enlarging the supply metal lines
reduces the resistance and avoids electrical overstress. The simplest way to build the
physical connection is to add a metal/Metal2 contact that may be found in the palette. The
connection is created by a plug called "via" between metal2 and metal layers. The final
layout design step consists in adding polarization contacts. These contacts convey the VSS
and VDD voltage supply close to the bulk regions of the device. Remember that the n-well
region should always be polarized to a high voltage to avoid short-circuit between VDD
and VSS. Adding the VDD polarization in the n-well region is a very strict rule.

Interconnects:
Up to 6 metal layers are available for signal connection and supply purpose. A
significant gap exists between the 0.7µm 2-metal layer technology and the 0.12µm
technology in terms of interconnects efficiency.
Firstly, the contact size is 6 lambda in 0.7µm technology, and only 4 lambda in
0.12µm. This features a significant reduction of device connection to metal and metal2.
Notice that a MOS device generated using 0.7µm design rules is still compatible with
0.12µm technology. But a MOS device generated using 0.12µm design rules would violate
several rules if checked in 0.7µm technology. Secondly, the stacking of contacts is not
allowed in micro technologies. This means that a contact from poly to metal2 requires a
significant silicon area as contacts must be drawn in a separate location. In deep-submicron
technology (Starting 0.35µm and below), stacked contacts are allowed.

Simulation:

A simulation window appears with inputs and output, shows the tphl, tplh and tp of
the circuit. The power consumption is also shown on the right bottom portion of the
window. If you are unable to meet the specifications of the circuit change the transistor
sizes. Generate
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the layout again and run the simulations till you achieve your target delays. Depending on
the input sequences assigned at the input the output is observed in the simulation.

Checking the Layout:

The Design Rule Checker (DRC) scans the design and verifies a set of design rules.
The errors are highlighted in the display window, with an appropriate message giving the
nature of the error. Details about the position and type of errors appear on the screen. Only
an error-free layout can be sent to fabrication.

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 CHAPTER-6

SIMULATION RESULTS

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 CHAPTER-6

SIMULATION RESULTS

6.1 EXISTING METHOD

6.1.1 1 Bit ALU

Fig.6.1.1.1 : Traditional 1 Bit ALU

Fig.6.1.1.2 :1-Bit ALU Schematic

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 Fig.6.1.1.3 :1-bit ALU Layout

Fig.6.1.1.4 :1-bit ALU Output

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6.1.2. 4-bit ALU

Fig.6.1.2.1:4-bit ALU Schematic

Fig.6.1.2.2:4-bit ALU Layout

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 Fig.6.1.2.3:4-bit ALU Output

6.1.3 GDI CELL

Fig.6.1.3.1:Basic GDI Cell

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 Fig 6.1.3.2: 4 bit ALU

6.1.4 GDI 1 BIT ALU

Fig.6.1.4.1: GDI 1-Bit ALU Schematic

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 Fig.6.1.4.2: GDI 1-Bit ALU Layout

Fig.6.1.4.3: GDI 1-Bit ALU Output

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6.1.5 GDI 4-bit ALU

Fig.6.1.5.1: GDI 4-Bit ALU Schematic

Fig.6.1.5.2: GDI 4-Bit ALU Layout

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 Fig.6.1.5.3: GDI 4-Bit ALU Output

6.2 PROPOSED SYSTEM

6.2.1 Modified GDI 1 bit ALU

Fig.6.2.1.1: Modified GDI 1-Bit ALU Schematic

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 Fig.6.2.1.2: Modified GDI 1-Bit ALU Layout

Fig.6.2.1.3: Modified GDI 1-Bit ALU Output

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6.2.2. Modified GDI 4-bit ALU

Fig.6.2.2.1: Modified GDI 4-Bit ALU Schematic

Fig.6.2.2.2:Modified GDI 4-Bit ALU Layout

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 Fig.6.2.2.3: Modified GDI 4-Bit ALU Output

6.3 COMPARISION RESULTS

Parameters Number of transistors Area Power Delay

used utilized dissipation
CMOS based ALU 54 19.7% 34.832uW 1.998ns
GDI based ALU 20 13.4% 13.023uW 2.982ns
Modified GDI based 18 12.4% 6.991uW 3.006ns
ALU

Table 6.3.1: Comparison of 1 – bit ALU

For 1-bit ALU, the number of transistors in modified GDI based ALU is less by
10% when compared with GDI based ALU and 66.67% when compared with CMOS based
ALU. The area utilized in modified GDI based ALU is less 7.46% when compared with
GDI based ALU and 37.05% when compared with CMOS based ALU. The power
dissipated by modified GDI based ALU is less 46.318% when compared with GDI based
ALU and 79.92% when compared with CMOS based ALU. But the trade off or
compromise is in delay i.e., delay is increased in modified GDI based ALU by 0.8% when
compared with GDI based ALU and 50.48% when compared with CMOS based ALU.

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 Table 6.3.2: Comparison of 4 – bit ALU

Parameters Number of Area Power Delay

transistors used utilized dissipation
CMOS based ALU 216 50.9% 0.1mW 8ns
GDI based ALU 80 45.6% 0.113mW 2.002ns
Modified GDI based 72 45.7% 0.107mW 2.002ns
ALU

For 4-bit ALU, the number of transistors in modified GDI based ALU are less 10%
when compared with GDI based ALU and 66.67% when compared with CMOS based
ALU. The area utilized in modified GDI based ALU is more by 0.2% when compared with
GDI based ALU and less by 10.216% when compared with CMOS based ALU. The power
dissipated by modified GDI based ALU is less 5.3% when compared with GDI based ALU
and is 7% more when compared with CMOS based ALU. The delay is decreased in
modified GDI based ALU by 0% when compared with GDI based ALU and 74.97% when
compared with CMOS based ALU.

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6.4 ADVANTAGES OF THE PROPOSED WORK

1. Easy to use for digital circuits.

2. It reduces the time delay.
3. Low power consumption.
4. Flexible and reliable.
5. This application is simple and easy to implement.
6. Cost effective.
7. Increase battery life.
8. Portability is easy.

6.5 APPLICATIONS OF THE PROJECT

1. Increased the speed of microprocessors and different DSP processors.

2. Proposed logic will helps in designing.
3. Low power and high speed and efficient energy.
4. Used in mainly DSP processors.

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 CHAPTER-7

CONCLUSION AND FUTURE SCOPE

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 CHAPTER-7

CONCLUSION AND FUTURE SCOPE

This work presents a 4-Bit ALU designed in 65nm CMOS Design using the MGDI
technique and simulated using the DSCH & MICROWIND simulator. Simulation results
showed an advantage of the proposed ALU design in terms of power consumption and
transistor count, while maintaining FullSwing Operation. The proposed design consists of
72 transistors and operates under 1V supply voltage.
This technology used for less area and low power with 3T XNOR full adder and Gate
Diffusion Input(GDI) multiplexer. Various methods of multiplexer and full Adder are implemented
and compared. Compared with previous paper, it reduces the power and area to 44% . the 2x1
multiplexer and 4x1 multiplexer are designed using Gate Diffusion Input technique. Full adder
based proposed technique consumes 10.190micro watts , but 3T XNOR technique consumes
8.639microwatts .Using these techniques, Full adder power leads to reduce, therefore the ALU
design also lends to reduced. Power dissipation, Propagation delay and number of transistors are
compared using GDI,PTL,2T XOR and 3T XNOR technique.

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 REFERENCESS

1. A. Srivastava and D. Govindarajan. (2002). A Fast ALU Design in CMOS for Low
Voltage Operation, VLSI Design, pp. 315-327
2. Yang, Y., Chandrakasan, A.P., Sheng, S. and Brodersen, R.W. (1992). LowLower
CMOS Digital Design, IEEE Journal of Solid-State Circuits 27(4), pp. 822- 839
3. Basak, S., Saha, D., Mukherjee, S., Chatterjee, S. and Sarkar, C.K. (2012). Design and
Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder
Cell, Modified with the concept of MVT Scheme, International Symposium on
Electronic System Design, pp. 130-134
4. Nehru, K., Shanmugam, A. and Darmila Thenmozhi, G. (2012). Design of Low Power
ALU Using 8T FA and PTL Based MUX Circuits, IEEE-International Conference on
Advances in Engineering, Science and Management, pp. 145-149
5. Khan, A.A., Pandey, S. and Pathak, J. (2014). A Review Paper on 3-T Xor Cells and
8- T Adder Design in Cadence 180nm, International Conference for Convergence of
Technology, pp. 1-6
6. Prakash, P. and Saxena, A.K. (2009). Design of Low Power High Speed ALU Using
Feedback Switch Logic, International Conference on Advances in Recent
Technologies in Communication and Computing, pp. 899-902
7. Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee and Chang, J.S. (2013). Low
Power Sub-Threshold Asynchronous QDI Static Logic Transistor-level
Implementation (SLTI) 32-Bit ALU, IEEE International Symposium, pp. 353-356 43
8. Jiaoyan Chen, Vasudevan, D., Popovici, E. and Schellekens, M. (2011). Design of a
Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit using a
Bidirectional Adder, 14th Euromicro Conference on Digital System Design, pp. 301-
308
9. Agarwal, S., Pavankumar, V.K. and Yokesh, R. (2008). Energy – Efficient, High
Performance Circuits for Arithmetic Units, 21st International Conference on VLSI
Design, pp. 371-376
10. Fayed, A.A. and Bayoumi, M.A. (2001). A Low Power 10-transistor Full Adder Cell
for Embedded Architecture, The 2001 IEEE International Symposium on Circuits and
Systems, pp. 226-229
11. [11] Parihar, R., Tiwari, N., Mandloi, A. and Kumar, B. (2014). An Implementation of
1-bit Low Power Full Adder based on Multiplexer and Pass Transistor Logic.
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 Outcome attained and its justification

POs Justification

The knowledge on concept of Very large Scale Integration was gained through
PO1
thisproject work.

PO2 This problem analysis and literature had been done on existing work.

PO3 Analysis and test data to gives the results of classified output.

PO4 The software DSCH&MICROWIND had been used for implementing

this project.
This project had been used for reducing power consumptions and hardware
PO5
designs.
The engineer and society: Apply reasoning informed by the contextual
PO6
knowledgeto assess Societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
Environment and sustainability: Understand the impact of the professional
PO7
engineering solutions in societal and environmental contexts, and demonstrate
the knowledge of, and need for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and
PO8
responsibilities and norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as a member
PO9 or leader in diverse teams, and in multidisciplinary settings.

Communication: Communicate effectively on complex engineering activities

with the engineering community and with society at large, such as, being able to
PO10
comprehend and write effective reports and design documentation, make
effective presentations, and give and receive clear instructions.
Project management and finance: Demonstrate knowledge and understanding of
theengineering and management principles and apply these to one’s own work,
PO11
as a member and leader in a team, to manage projects and in
multidisciplinary
environments.
Life-Long learning Recognize the need for, and have the preparation and ability
P012
toengage in independent and life-long learning in the broadest content of
technological change.

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