Course Course Course L T P C

18CSC203J COMPUTER ORGANIZATION AND ARCHITECTURE C Professional Core

Code Name Category 3 0 2 4
Pre-requisite Co-requisite Progressive
Nil Nil 18CSC207J
Courses Courses Courses
Course Offering Department Computer Science and Engineering Data Book / Codes/Standards Nil

Course Learning Rationale (CLR): The purpose of learning this course is to: Learning Program Learning Outcomes (PLO)

CLR-1 : Utilize the functional units of a computer 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CLR-2 : Analyze the functions of arithmetic Units like adders, multipliers etc.
CLR-3 : Understand the concepts of Pipelining and basic processing units
CLR-4 : Study about parallel processing and performance considerations.

Environment & Sustainability

Analysis, Design, Research
Level of Thinking (Bloom)

Expected Proficiency (%)

Expected Attainment (%)

Have a detailed study on Input-Output organization and Memory Systems.

Individual & Team Work

CLR-5 :

Engineering Knowledge

Design & Development

Project Mgt. & Finance

Modern Tool Usage

Life Long Learning

CLR-6 :

Problem Analysis

Society & Culture

Communication

PSO – 3
PSO - 1

PSO - 2
Ethics
Course Learning Outcomes (CLO): At the end of this course, learners will be able to:

CLO-1 : Identify the computer hardware and how software interacts with computer hardware 2 80 70 H H - - - - - - M L - M - - -
CLO-2 : Apply Boolean algebra as related to designing computer logic, through simple combinational and sequential logic circuits 3 85 75 H H H - H - - - M L - M - - -
CLO-3 : Analyze the detailed operation of Basic Processing units and the performance of Pipelining 2 75 70 H H H H - - - - M L - M - - -
CLO-4 : Analyze concepts of parallelism and multi-core processors. 3 85 80 H - - H - - - - M L - M - - -
CLO-5 : Identify the memory technologies, input-output systems and evaluate the performance of memory system 3 85 75 H - H H - - - - M L - M - - -
CLO-6 : Identify the computer hardware, software and its interactions 3 85 75 H H H H H - - - M L - M - - -

Duration (hour) 15 15 15 15 15
Addition and subtraction of Signed Fundamental concepts of basic processing
SLO-1 Functional Units of a computer Parallelism Memory systems -Basic Concepts
numbers unit
S-1
Need, types and applications of
SLO-2 Operational concepts Problem solving Performing ALU operation Memory hierarchy
Parallelism
Execution of complete instruction, Branch
SLO-1 Bus structures Design of fast adders Parallelism in Software Memory technologies
instruction
S-2
Ripple carry adder and Carry look ahead Instruction level parallelism and Data
SLO-2 Memory locations and addresses Multiple bus organization RAM, Semiconductor RAM
adder level parallelism

SLO-1 Memory operations Multiplication of positive numbers Hardwired control Challenges in parallel processing ROM,Types
S-3
Architectures of Parallel Systems - Flynn’s
SLO-2 Instructions, Instruction sequencing Problem Solving Generation of control signals Speed,size cost
classification
SLO-1 Lab 1: To recognize various Lab-12: Study of Carry Save
Lab 3:Study of TASM Lab-10: Study of Array Multiplier Multiplication
S Lab-6: Design of Half Adder
components of PC-Input Output systems Addition and Subtraction of 8-bit
4-5 SLO-2 Processing and Memory units Design of Full Adder Design of Array Multiplier Program to carry out Carry Save
number
Multiplication
S-6 SLO-1 Addressing modes Signed operand multiplication Micro-programmed control- SISD,SIMD Cache memory

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 SLO-2 Problem solving Problem solving Microinstruction MIMD, MISD Mapping Functions
Introduction to Microprocessor and Fast multiplication- Bit pair recoding Hardware multithreading
SLO-1 Micro-program Sequencing Replacement Algorithms
Assembly language of Multipliers
S-7 Coarse Grain parallelism, Fine Grain
Writing of assembly language
SLO-2 Problem Solving Micro instruction with Next address field Problem Solving
programming parallelism
SLO-1 ARM Processor Carry Save Addition of summands Basic concepts of pipelining Uni-processor and Multiprocessors Virtual Memory
S-8
Performance considerations of various
SLO-2 Basics of IO operations. Problem Solving Pipeline Performance Multi core processors
memories
Lab-2:To understand how different
SLO-1 components of PC are connected to Lab-13: Understanding Processing
S Lab 4: Addition of 16-bit number Lab-7: Study of Ripple Carry Adder Lab-11: Study of Booth Algorithm
work properly unit
9-10 Subtraction of 16-bit number Design of Ripple Carry Adder Program to carry out Booth Algorithm
SLO-2 Assembling and Disassembling of Design of primitive processing unit
System Components
SLO-1 // Kindly fill the session content Integer division – Restoring Division Pipeline Hazards-Data hazards Multi-core processors Input Output Organization
S-11
SLO-2 // Kindly fill the session content Solving Problems Methods to overcome Data hazards // Kindly fill the session content Need for Input output devices

SLO-1 // Kindly fill the session content
S-12
SLO-2 // Kindly fill the session content
SLO-1 // Kindly fill the session content
S-13
SLO-2 // Kindly fill the session content
SLO-1
S Lab-5: Multiplication of 8-bit number
// Kindly fill the session content
14-15 SLO-2
Non Restoring Division Instruction Hazards
Hazards on conditional and Unconditional
Solving Problems
Branching
Floating point numbers and operations Control hazards
Solving Problems Influence of hazards on instruction sets
Lab-8: Study of Carry Look-ahead Adder
Factorial of a given number Design of Carry Look-ahead Adder
// Kindly fill the session content
// Kindly fill the session content
// Kindly fill the session content
// Kindly fill the session content
// Kindly fill the session content
Memory mapped IO
Program controlled IO
Interrupts-Hardware, Enabling and
Disabling Interrupts
Handling multiple Devices
Lab-14: Understanding Pipeline
concepts
Design of basic pipeline.

1. Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, 5th ed., McGraw-Hill, 2015 5. William Stallings, Computer Organization and Architecture – Designing for Performance, 10 th ed.,
Learning 2. Kai Hwang, Faye A. Briggs, Computer Architecture and Parallel Processing”, 3rd ed., McGraw Hill, 2016 Pearson Education, 2015
Resources 3. Ghosh T. K., Computer Organization and Architecture, 3rd ed., Tata McGraw-Hill, 2011 6. David A. Patterson and John L. Hennessy Computer Organization and Design - A Hardware
4. P. Hayes, Computer Architecture and Organization, 3rd ed., McGraw Hill, 2015. software interface, 5th ed., Morgan Kaufmann,2014

Learning Assessment
Continuous Learning Assessment (50% weightage)
Bloom’s Final Examination (50% weightage)
CLA – 1 (10%) CLA – 2 (15%) CLA – 3 (15%) CLA – 4 (10%)#
Level of Thinking
Theory Practice Theory Practice Theory Practice Theory Practice Theory Practice
Remember
Level 1 20% 20% 15% 15% 15% 15% 15% 15% 15% 15%
Understand
Apply
Level 2 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
Analyze
Evaluate
Level 3 10% 10% 15% 15% 15% 15% 15% 15% 15% 15%
Create
Total 100 % 100 % 100 % 100 % -
# CLA – 4 can be from any combination of these: Assignments, Seminars, Tech Talks, Mini-Projects, Case-Studies, Self-Study, MOOCs, Certifications, Conf. Paper etc.,

Course Designers

SRM Institute of Science & Technology – Academic Curricula (2018 Regulations)

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Experts from Industry Experts from Higher Technical Institutions Internal Experts
1. T. V. Sankar, HCL Technologies Ltd, Chennai, sankar_t@hcl.com 1. Prof. A.P. Shanthi, ANNA University Chennai, a.p.shanthi@cs.annauniv.edu 1.Dr. V. Ganapathy, SRMIST
2. 2. 2. Dr. C. Malathy, SRMIST

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SRM Institute of Science & Technology – Academic Curricula (2018 Regulations)
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