University of Engineering

&
Technology, Taxila

DSD
Lab Manual# 16
GROUP NO 3

6TH SEMESTER

OMEGA SECTION

SUBMITTED TO: ENGR.ASGHAR ISMAIL

Dated;
18/07/2023
 LAB MANUAL NO 16

TASK NO 1
Write a Verilog code for designing the shift and add multiplier design.
Objectives:
The objective of this project is to design a shift and add multiplier using Verilog. The shift and add
algorithm is a commonly used method for performing multiplication in digital circuits. The goal is
to implement the Verilog code for the multiplier and evaluate its performance in terms of accuracy
and speed.
Apparatus List:

• Verilog HDL
• FPGA Development Board
• Xilinx Vivado or any other Verilog simulation and synthesis tool
Procedure:

• Design the Verilog code for the shift and add multiplier.
• Simulate the Verilog code to verify its correctness and functionality.
• Synthesize the Verilog code to obtain the gate-level implementation.
• Implement the synthesized design on an FPGA development board.
• Verify the functionality and performance of the multiplier on the FPGA.

Logic Circuit:
The shift and add multiplier utilizes the concept of shifting and addition to perform multiplication.
It involves shifting the multiplicand and adding it to an accumulator based on the bits of the
multiplier. The circuit consists of three main components: the multiplier, the multiplicand, and the
accumulator. The multiplier and multiplicand are input signals, and the accumulator stores the
intermediate results during the multiplication process.
The logic circuit operates in iterations based on the number of bits in the multiplier. In each
iteration, the multiplier bit is examined, and the multiplicand is shifted accordingly. If the multiplier
bit is 1, the shifted multiplicand is added to the accumulator. This process continues until all the
bits of the multiplier are processed.

Truth Table:
The shift and add multiplier doesn't have a traditional truth table that lists all possible input-output
combinations. Instead, its behavior is determined by the underlying logic implemented in the
Verilog code.

K-Map:
Karnaugh Maps (K-Maps) are not applicable for the shift and add multiplier, as it is a sequential
circuit and involves shifting and addition operations rather than direct boolean functions.

Boolean Expression:
The shift and add multiplier doesn't have a single boolean expression that represents its entire
functionality. It involves sequential shifting and addition operations based on the bits of the
multiplier.

Schematic Diagram:
A schematic diagram represents the gate-level implementation of the shift and add multiplier. It
shows the interconnections between logic gates and the overall structure of the circuit.

Code:
module shift_add_multiplier(
input [3:0] multiplicand,
input [3:0] multiplier,
 output reg [7:0] product
);

reg [3:0] shifted_multiplicand;

reg [7:0] accumulator;

always @(posedge clk)

begin
if (reset)
accumulator <= 8'b0;
else
begin
if (multiplier[0] == 1'b1)
accumulator <= accumulator + multiplicand;

shifted_multiplicand <= {shifted_multiplicand[2:0], multiplicand[3]};

multiplier <= multiplier >> 1;
end
end

assign product = accumulator;

endmodule

Results:
Simulation Results:
Simulate the Verilog code using a simulation tool (e.g., ModelSim or Vivado Simulator) to verify
the correctness of the design. Verify that the circuit produces the expected output for different
input test cases.

Synthesis Results:
Synthesize the Verilog code using a synthesis tool (e.g., Xilinx Vivado) to obtain the gate-level
implementation. Analyze the synthesis report to evaluate the area, power, and timing
characteristics of the circuit.

FPGA Implementation Results:

Implement the synthesized design on an FPGA development board. Verify the functionality of the
circuit on the FPGA and measure its performance in terms of speed and resource utilization.

Conclusion:
The shift and add multiplier is a commonly used method for performing multiplication in digital
circuits. The Verilog code implementation of the shift and add multiplier provides an effective
solution for multiplying two numbers. The performance of the multiplier can be evaluated by
simulating, synthesizing, and implementing the design on an FPGA development board. The
results obtained from the simulations and FPGA implementation will help analyze the accuracy,
speed, and resource utilization of the shift and add multiplier.

TASK NO 2
Write a Verilog code for Wallace Tree reduction for efficient addition of the partial products.
Objectives:
The objective of this project is to implement a Wallace Tree reduction circuit using Verilog. The
Wallace Tree reduction technique is widely used to optimize the addition of partial products in
multiplication circuits. By reducing the number of partial product bits to be added, it improves the
overall efficiency and reduces the area and power consumption of the circuit.

Apparatus List:
• Verilog HDL
• FPGA Development Board
• Xilinx Vivado or any other Verilog simulation and synthesis tool

Procedure:
• Design the Verilog code for the Wallace Tree reduction circuit.
• Simulate the Verilog code to verify its correctness and functionality.
• Synthesize the Verilog code to obtain the gate-level implementation.
• Implement the synthesized design on an FPGA development board.
• Verify the functionality of the circuit on the FPGA.

Logic Circuit:
The Wallace Tree reduction circuit is designed to efficiently add the partial products generated
during the multiplication process. It employs a tree-like structure to reduce the number of bits to
be added at each stage, resulting in faster and more efficient addition.
The logic circuit consists of three main components:
Partial Product Generation:
This component generates the partial products for the multiplication operation.
Partial Product Reduction:
This component performs the reduction of partial products using the Wallace Tree algorithm.
Final Addition:
This component adds the reduced partial products to obtain the final product.
Truth Table:
Since the Wallace Tree reduction circuit is a combinational circuit, it doesn't have a traditional
truth table. Instead, the circuit's behavior is described by the combinational logic implemented in
the Verilog code.

K-Map:
Karnaugh Maps (K-Maps) are not applicable for the Wallace Tree reduction circuit, as it is a
combinational circuit and the logic is expressed directly in the Verilog code.

Boolean Expression:
The Wallace Tree reduction circuit doesn't have a single boolean expression that represents its
entire functionality. It consists of multiple stages and combinational logic components to efficiently
add the partial products.

Schematic Diagram:
A schematic diagram represents the gate-level implementation of the Wallace Tree reduction
circuit. It shows the interconnections between logic gates and the overall structure of the circuit.
Code:
module wallace_tree_reduction (
input [3:0] partial_products,
output reg [6:0] result
);

wire [3:0] g, p, c;
wire [1:0] carry_in;

// Generate and Propagate signals

assign g[0] = partial_products[0];
assign p[0] = partial_products[0];
assign c[0] = 1'b0;
assign g[1] = partial_products[1] & partial_products[0];
assign p[1] = partial_products[1] ^ partial_products[0];
assign c[1] = partial_products[1] & partial_products[0];
assign g[2] = partial_products[2] & partial_products[1] & partial_products[0];
assign p[2] = partial_products[2] ^ partial_products[1] ^ partial_products[0];
assign c[2] = (partial_products[2] & partial_products[1]) | (partial_products[2] &
partial_products[0]) | (partial_products[1] & partial_products[0]);
assign g[3] = partial_products[3] & partial_products[2] & partial_products[1] & partial_products[0];
assign p[3] = partial_products[3] ^ partial_products[2] ^ partial_products[1] ^ partial_products[0];
assign c[3] = (partial_products[3] & partial_products[2] & partial_products[1]) | (partial_products[3]
& partial_products[2] & partial_products[0]) | (partial_products[3] & partial_products[1] &
partial_products[0]) | (partial_products[2] & partial_products[1] & partial_products[0]);

// Carry-save adders
assign carry_in[0] = c[0];
assign carry_in[1] = c[1];
assign carry_in[2] = c[2];
assign carry_in[3] = c[3];

wire [6:0] sum;

assign sum = {g[3], p[3], g[2], p[2], g[1], p[1], g[0]} + {3'b000, carry_in};

// Carry-propagate adder
assign result = sum + {1'b0, carry_in[3]};
endmodule

Results:
Simulation Results:
Simulate the Verilog code using a simulation tool (e.g., ModelSim or Vivado Simulator) to verify
the correctness of the design. Verify that the circuit produces the expected output for different
input test cases.
Synthesis Results:
Synthesize the Verilog code using a synthesis tool (e.g., Xilinx Vivado) to obtain the gate-level
implementation. Analyze the synthesis report to evaluate the area, power, and timing
characteristics of the circuit.
FPGA Implementation Results:
Implement the synthesized design on an FPGA development board. Verify the functionality of the
circuit on the FPGA and measure its performance in terms of speed and resource utilization.

Conclusion:
The Wallace Tree reduction circuit is an efficient approach for adding partial products in
multiplication circuits. By reducing the number of partial product bits to be added at each stage, it
improves the overall efficiency, reduces area and power consumption, and enhances the
performance of the circuit. The Verilog code implementation of the Wallace Tree reduction circuit
provides an effective solution for optimizing multiplication operations in digital systems.