A Practical Approach To CML Technology Design Flow and Implementation

A practical approach to CML technology
design flow and implementation
Alex Unnervik alex.unnervik@epfl.ch

Benoit Lovis benoit.lovis@epfl.ch
under supervision of
Demirci Tugba tugba.demirci@epfl.ch

Baltaci Can can.baltaci@epfl.ch
Prof. Yusuf Leblebici yusuf.leblebici@epfl.ch
in the
Microelectronic Systems Laboratory LSM
Electrical Engineering Section
June 2013
Acknowledgements
We have both greatly appreciated the help of Can Baltaci and Tugba Demirci who have
dedicated a lot of time to answer our questions and helped us analyze the problems we
have faced. Special thanks to Nikola Katic and Radisav Cojbasic who were initially
not involved in our project but still have been present to help us in the worst times,
not forgetting to mention professor Yusuf Leblebici who despite his busy schedule has
offered us some important advice and comments.
iii
Contents
Acknowledgements iii
List of Figures vii
List of Tables ix
Abbreviations xi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Report organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 CML logic 5
2.1 Working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 CML Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Semi-custom design flow for CML 9

3.1 Standard cells library creation and characterization . . . . . . . . . . . . . 10
3.1.1 Standard cells library creation . . . . . . . . . . . . . . . . . . . . 10
3.1.2 Library characterization flow . . . . . . . . . . . . . . . . . . . . . 11
3.1.2.1 Logical views creation . . . . . . . . . . . . . . . . . . . . 12
3.1.2.2 SPICE netlists extraction . . . . . . . . . . . . . . . . . . 13
3.1.2.3 LEF file creation . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2.4 GDS files creation . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2.5 Milkyway files creation . . . . . . . . . . . . . . . . . . . 14
3.1.2.6 Library characterization . . . . . . . . . . . . . . . . . . . 15
3.1.2.7 Library compilation . . . . . . . . . . . . . . . . . . . . . 15
3.1.2.8 Verilog library compilation . . . . . . . . . . . . . . . . . 15
3.2 Top-down design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 HDL model design . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.3 Placement and routing . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 DES algorithm top-down design with CML and CMOS logic 21

4.1 DES working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 CMOS and CML implementation of DES : comparison . . . . . . . . . . . 28
4.2.1 HDL design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.2 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
v
Contents vi
4.2.2.1 CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.2.2 CML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.2.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.3 Placement and routing . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.3.1 CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.3.2 CML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Conclusion 35
5.1 Encountered difficulties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 What we learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
A Semi-custom design directories architecture 39
B VHDL implementation of DES algorithm 41
Bibliography 85
List of Figures
2.1 General CML topology. See [14]. . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Example of BDDs. Top left: BUFFER, top right: INVERTER, bottom
left: OR, bottom right: AND. . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Two input NAND gate BDD and its CML equivalent. See [12]. . . . . . . 8
3.1 Standard library creation and characterization design flow. See [14]. . . . 10
3.2 Fat pins and wires placement. See [14]. . . . . . . . . . . . . . . . . . . . . 11
3.3 CML 2 inputs AND gate schematic and layout. See [13]. . . . . . . . . . . 12
3.4 Top-down design flow. See [1]. . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Synthesis flow. See [17]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Overview of the primary loop in the DES. See [16] . . . . . . . . . . . . . 22

4.2 Initial permutation block. See [15] . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Inverse initial permutation block. See [15] . . . . . . . . . . . . . . . . . . 23
4.4 Details of the F-function schematic. See [16] . . . . . . . . . . . . . . . . 24
4.5 Details of the expansion block. See [15] . . . . . . . . . . . . . . . . . . . 24
4.6 Details of the S-Box. See [15] . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Details of the permutation block. See [15] . . . . . . . . . . . . . . . . . . 26
4.8 Details of the PC1. See [15] . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.9 Details of the Key Scheduler. See [16] . . . . . . . . . . . . . . . . . . . . 27
4.10 Details of the shifters. See [15] . . . . . . . . . . . . . . . . . . . . . . . . 27
4.11 Details of the PC2. See [15] . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.12 Details of the DES FSM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.13 Details of the key scheduler FSM. . . . . . . . . . . . . . . . . . . . . . . . 29
4.14 Final pared DES in CMOS 90nm technology . . . . . . . . . . . . . . . . 33
vii
List of Tables
4.1 CMOS synthesized DES performances . . . . . . . . . . . . . . . . . . . . 30

4.2 CML synthesized DES performances . . . . . . . . . . . . . . . . . . . . . 31
4.3 Driving strength and bias current for different gates . . . . . . . . . . . . 31
4.4 CMOS pared DES performances . . . . . . . . . . . . . . . . . . . . . . . 32
ix
Abbreviations
API Application Programmable Interface

BJT Bipolar Junction Transistor
(M)CML (MOS) Current Mode Logic
CMOS Complementary MOS
DRC Design Rules Check
FSM Final State Machine
GDS Graphic Database System
HDL Hardware Description Langage
LEF Layout Exchange Format
LVS Layout Versus Schematic
NMOS N-channel MOS
P&R Placement & Routing
PMOS P-channel MOS
RTL Register Transfert Level
SCL Source Common Logic
SDF Standard Delay Format
TCL Tool Command Language
xi
Chapter 1
Introduction
In the early 1970s, when the BJT was the most widely used transistor, the MOS tran-
sistor was discovered. It was a game changer at the time because of its zero static
power consumption. Throughout its lifetime, the MOS transistor has encountered many
changes in the aim of a better, smaller and faster transistor. This has mainly been
achieved by reducing its size to the nanoscale: a dramatic modification. However, these
optimizations have come with an increasingly bigger price to pay: quantum physics
phenomenon have started to interfere with the correct behaviour of the MOS transistor,
leading to an explosion of the static power consumption. It has reached orders of magni-
tudes the initial value, reducing the MOS’s initial huge advantage. This leakage current
becomes an increasingly bigger proportion of the global power consumption and can
not be neglected anymore. The CMOS technology is thus reaching a dead end but the
demand for processing power is still exponentially increasing: we are therefore entering
the post CMOS area and are searching for a substitute harder than ever.
Current-mode logic (also called Source Common Logic) presents many advantages over
CMOS and could be a good candidate, offering improvements in both speed and power
consumption if designed well. Indeed, since the CML cells are mainly relying on NMOS
transistors in saturation and linear regime, they operate extremely fast. The small
output swing reduces the dynamic power consumption and is suitable for differential
routing with reduced crosstalking. The constant current source which powers the device
is independant on the switching activity and is not source of any noise on the power rails,
1
Current-mode Logic 2
which makes it extremely appropriate for mixed signal design. Finally, the differential
signals are far more immune to external noise. The CML might be the future.
The goal of this project is to aggregate previous studies on CML and differential signal
integration with modern tools, in order to define a how-to and general guideline to semi-
custom design with a CML library to facilitate future work as well as exposing a concrete
example of CML implementation in Top-Down design flow.
1.1 Motivation
The cryptography domain relies heavily on security. Hiding the key is essential to its
encoding and decoding efficiency. Attacks aimed at recovering the key can be extremely
sophisticated: Side Channel Attack is a typical kind of attack CMOS circuits are vul-
nerable to. It consists on analyzing the variations in the power supply resulting of the
noise introduced by the switching activity of the CMOS circuit. This can lead to critical
information being disclosed to the hacker.
On the contrary to CMOS circuits, CML based circuits are totally immune to these kind
of attacks since the power consumption is totally independant on the switching activity:
it is constant wether the circuit is idle or not. For this reason, CML technology is very
suitable for cryptography.
In addition to the advantage in cryptography, is the high speed. It enables high band-
width transfers. This is already used in DVI and HDMI video links which require very
high bitrates.
These are some of the reasons we focus on the CML technology today.
1.2 Report organization
The report is organized as follows: Chapter 2 introduces CML logic and explains the
working principle behind this new way of designing logic. Chapter 3 explains the steps
needed to design an architecture with CML logic, from full-custom design of the cells to
the library characterization, synthesis and finally place and route. Chapter 4 illustrates
the previously explained design-flow with the cipher/decipher DES algorithm. HDL
Design, synthesis and placement and routing using both standard CMOS library and
CML library will be compared in this chapter. Finally, conclusions are given in Chapter
5.
Chapter 2
CML logic
In order to understand more clearly how the CML topology is used and operates, below
is a more in depth description of the CML mechanics.
2.1 Working principle
Analyzing the construction of a standard CML cell from top to bottom, leads us to
three different parts. First, attached to the positive power supply is the active load. Its
purpose is to convert the current into voltage, readable at the output. There are two
parallel branches which lead to a differential output signal. The active load is the only
part of the CML circuit that is realized with PMOS transistors. What differentiates
the active load in a CML circuit from a standard active load is how the Bulk of the
PMOS transistors are connected. Instead of being connected to the source (and power
supply) as usual, they are connected to the drain. This decreases the response delay
and increases the resistance. For further explanations on how and why this is realized,
see [7].
Below the active load is the specific part linked to the function that the cell needs to
execute. It is realized entirely with NMOS transistors. Explanations on how this specific
core function can be easily obtained is described in the next part. All inputs to this bloc
are differential since they work very similarly to a differential pair. Blocs can be serially
connected by linking the differential outputs of the previous cell to the differential inputs
of the next cell, much like traditional CMOS logic gates.
5
Figure 2.1: General CML topology. See [14].
At the bottom is the single current source, connected to the specific core function and to
the negative power supply. It is common to the whole cell and draws a constant current.
It is the key to the consumption of the device. The DC source enables the device to
not react to switching on the power lines, but also prevents it from having zero power
consumption in idle state. The current influences the consumption but also the speed.
The higher the current, the faster the cell can charge and decharge the connected load.
The formula for the delay of the cell is:
Vsw
td = τ · ln(2) = Cload · ln(2)
ISS
It increases with the swing and the load capacitance but decreases with the bias current.
In figure 2.1 is a representation of how a standard CML cell is constructed. We can easily
identify the different parts described previously (active load with differential output,
specific core function with differential inputs and current source). Notice how easy it is
to obtain the inverted function or to use the function with inverted inputs: simply swap
the inputs or outputs of the differential signals. This way a NAND gate can become a
AND gate and reversely.
2.2 CML Circuits
An advantage of the CML circuits is the extreme ease of realizing the core logic function.
It can be easily obtained with the Binary Decision Diagram (i.e. BDD). In the example
below, we can compare the BDD with the CML equivalent. The vertices in the BDD
can be identified in the CML circuit. The signal in each vertex will be the one powering
each corresponding stage.
Figure 2.2: Example of BDDs. Top left: BUFFER, top right: INVERTER, bottom
left: OR, bottom right: AND.
In figure 2.2 are examples of a few basic BDDs. The diagram is read from the first
vertex (in blue) to the final value (in orange). Let’s consider the OR gate: it contains
two inputs X and Y. It does not matter if you connect A to X and B to Y or the
other way round. The first vertex, A, is either ‘1’ or ‘0’. If A is ‘1’ the output is ‘1’
independantly of the value of B (simply follow the arrow of the chosen value). However,
if A is ‘0’, the output value will be determined by B. The value in the orange square
is the resulting value at the output when the input is set with the values of the chosen
path.
In figure 2.3 is an example of CML cell realizing the NAND function with two (differ-
ential) inputs and one (differential) output. The lower two transistors circled together
represent the bottom vertex with input A and the two transistors above circled together
represent the vertex with input B. Notice how they are connected exactly the same way
the vertexes are connected. This is a very handy way of obtaining the core logic func-
tion: draw the BDD and “map” it on the CML template (the active load and the current
source) by placing a differentiel pair everytime there is a vertex, and use the input that
Figure 2.3: Two input NAND gate BDD and its CML equivalent. See [12].
is indicated in the vertex. Connect it the same way it is connected on the BDD. Pay
attention to where the signal and its inverted value are connected. If swapped, the input
is inverted. This is equally important for the output.
Chapter 3
Semi-custom design flow for CML
There are two ways to design an integrated circuit. The first one is the full-custom
approach, where every transistor is designed and optimized by hand. This method is
very time consuming and challenging, but it leads to optimal speed, consumption and
area performance, and it provides the most liberty to the designer: he can virtually do
all he wants. This approach is the best when designing small circuits, but when it comes
to circuits with millions or even billions of transistors, it is not possible anymore to place
all of them manually.
This is why big circuits are done with a semi-custom approach. In this method, different
cells of a standard cell library are used to build the desired function. The designer
doesn’t need to create the schematic of the circuit any more. He now can describe it
with a hardware description langage (HDL) like VHDL or Verilog, and use synthesis
and placement and routing (P&R) tools in order to build the circuit. This method is
faster and cheaper than placing every transistor manually, but offers less liberty since
standard cells have to be used and therefore can’t be changed by the designer.
This chapter will explain the steps needed to design a circuit with a semi-custom ap-
proach using CML. These steps can be separated in two main sections: standard cells
library creation and characterization on one hand, and top-down design on the other
hand.
9
3.1 Standard cells library creation and characterization
This first section is mandatory if you want to design your own standard cells library.
If the library is already designed and characterized, you will only need to describe
the desired function with a HDL, do the synthesis and the P&R. These steps will be
explained further.
The standard library creation and characterization design flow is illustrated in figure
3.1. It is separated in two subsections: standard cells library full-custom design and its
characterization using scripts.
Figure 3.1: Standard library creation and characterization design flow. See [14].
3.1.1 Standard cells library creation
A standard cell library consists of different standard cells which implement a logic or
storage function. As these cells will be used by synthesis and P&R tools they have to
be well built and optimized in order to achieve the greatest performance.
We used the CML standard cells library designed in 180 nm CMOS technology by
Mohammad BEIKAHMADI during his master project. We will explain basic principles
and layout methodology, for more information please consult the master thesis [13].
When creating a library, the first thing to do is to draw the schematic of each cell wanted
in the library. Then comes a simulation part where every cell is tested to see if they work
properly. After that, every cells transistors can be optimized to reach the best speed,
area and power performance. Once the designer is satisfied with his optimization, he
can start the layout.
As explained in the previous chapter, one of the great advantages of CML is the capa-
bility to use differential inputs/outputs, but it is also a problem for semi-custom design
because synthesis and P&R tools don’t handle differential inputs/outputs. So we will
have to use some “tricks” to fool these tools.
The first “trick” concerns the input/output pins; to enable automatic differential routing,
fat pins are introduced. These fat pins combine differential pins to a fat one as shown
on figure 3.2. Then during the P&R step, fat pins will be routed with fat wires. Then,
these wires will be splitted up to get two normal wires. See section 3.2.3 for more details.
This trick will also create an abstract single inputs/outputs version of each cell that will
be regrouped in a single I/O library.
Figure 3.2: Fat pins and wires placement. See [14].
Once the layout is done, DRC and LVS must succeed. DRC ensures that the layout is
physically possible and LVS checks if all layout nets match schematic layout.
You can see in figure 3.3 the CML schematic and layout of a two inputs AND gate.
3.1.2 Library characterization flow
Once all the needed cells are built and verified, the next step is to characterize the
library. It is during this step that all necessary files needed by synthesis and P&R tools
will be created. As this is a very repetitive task, we will use scripts. These scripts
Figure 3.3: CML 2 inputs AND gate schematic and layout. See [13].
permit us to perform the same actions on every cell in the library. They are written in
SKILL, C-shell, Perl and TCL. We used the scripts created by Stephane BADEL during
his PhD at LSM.
For each step of the creation of the necessary files, we will explain the purpose of the
step and the working principle of the corresponding script. All scripts are consultable
at LSM. Notice that you will need to be connected via SSH to a LSM server to access
various files during running the scripts.
Remark: for this section, all path are given from the /rev0 folder.
3.1.2.1 Logical views creation
The first script to run is written in SKILL, which is a language developped to access
each Cadence tool using an API. It removes the H and L extensions from the name of
the differential signals and creates a new view in the library called “logical”.
Before running the script you should place it in the same directory the Cadence environ-
ment is launched. Then open the script and change the LIB variable to match your li-
brary name. To finally run the script, enter the command Load(“create logical views.il”)
in the Cadence command line environment.
3.1.2.2 SPICE netlists extraction
Since the delay of a cell depends on the internal parasitic (and output load) capacitance,
it is important to extract these values because it will later enable us to determine the
“speed” of the cell. To do so, we first need the netlist extracted from the cell to which
will be added the induced parasitic capacitors calculated by the Assura simulator. This
netlist is stored in a SPICE file which contains the component list with (in order):
• Their type and reference (e.g. C1)
• The nodes to which they are connected to (for a n-pin component, there are n
nodes)
• The component value in simple case (e.g. 1KΩ for a resistor)
• Possibly the model used
• Possibly a parameters list allowing modification of the model
The script “avextract.csh” will run the parasitic extraction and will store the .sp (SPICE)
files in the /rev0/lib d/spice folder. Before running the script you should 1) change the
CDB LIB variable in the META file located in the /.script folder to match your library
name and 2) include your library in the cds.lib file located in the /lib d/cdb folder.
Finally run the script from the /.script folder typing avextract.csh in the terminal. It
will prompt the succesfully extracted cells and create a avextract.log file which contains
informations, warnings and errors generated by the script, located in the /.script folder.
3.1.2.3 LEF file creation
The LEF file contains information about the abstract view of each cell: geometrical
aspect, I/O pins and optionally blockage restricting over-the-cell routing. It is necessary
for the P&R tool.
The LEF file is generated with the create lef.csh script which will use the Cadence
abstract generator. It will create a stscl.lef file and a stscl.rpt report in the /lib s/lef
folder. Before running the script, you should include your library in the cds.lib file
located in the /rev0 folder.
To run the script, type create lef.csh in the terminal from the /.script folder. A cre-
ate lef.log file will be created in the same folder, and four abstract views will be added.
Other abstract options including the metal layer definitions, power pin names etc. can be
set in the “abstract options.il” and “abstract options fat.il” files located in the /.script
folder. It is also during this step that single inputs/outputs abstract views of each cell
will be created.
3.1.2.4 GDS files creation
The GDS file is the final output product of the IC design cycle and is given to IC
foundries for IC fabrication. It is a binary file format representing planar geometric
shapes, text labels, and other information about the layout in hierarchical form.
To run the script, type create gds.csh in the terminal from the /.script folder. The
created GDS file will be placed in the /lib d/gds folder.
3.1.2.5 Milkyway files creation
The milkyway libraries are created from the LEF files and they are used by physical
compilers such as dc shell in topographical mode. The script “create mw.csh” also
generates the technology files (.tf) and the physical libraries (.plib, .pdb). A detailed log
file named “Milkyway.log” is also created by the script in the /lib d/milkyway directory.
To run the script, type create mw.csh in the terminal from the /.script folder. It will
create the .plib and .pdb files in the /lib d/liberty folder, the .tf file and the milkyway
library in the /lib d/milkyway folder.
3.1.2.6 Library characterization
The process of characterization consists on measuring all the characteristics of each cell
in the library. It includes delays, consumption, capacitance etc. It uses pin functions of
the cells which are defined in the “cell definitions.tcl” and “flipflop definitions.tcl” files.
The cells are characterized for a supply voltage of 0.5 V, a swing voltage of 200mV and
a bias current of 100 pA but these corners can be easily modified in the characterize.tcl
file. These corners are defined in a ultra-low power purpose.
The characterization is done here with the “characterize.csh script”. To run it, type
characterize.csh in the terminal from the /.script folder. It will create the liberty files
(.lib) in the /lib s/liberty folder.
Remark: this script has not been successfully debugged.
3.1.2.7 Library compilation
Once all the scripts have been successfully executed, the final step is to compile the
library. This means the liberty files will be compiled in a .db file that will later be
imported in the synthesis tool, and a VHDL version of the library will be created in the
/lib d/vhdl. The .db files will be located in the /lib s/liberty/<corner name>folder.
To run the script, type compile lib.csh in the terminal from the /.script folder.
3.1.2.8 Verilog library compilation
In order to be able to do post-synthesis and post-P&R simulations, we need to compile

the Verilog library created during the library characterization step. This will create a
library usable by Modelsim.
To do so, first launch Modelsim from the /MGC MSIM folder, and create a new li-
brary typing vlib ../DLIB/CML lib in the Modelsim terminal. Then type vlog +acc
<LIB PATH.v>-work CML lib. In our case, the stscl.v file is in the /lib s/verilog/
folder.
After these eight steps, the library is completly characterized, meaning that all necessary
files have been created. These files can be imported in synthesis and P&R tools.
3.2 Top-down design
The top-down design is an approach in which the designer mainly focuses on the the
“big picture” of the system. It aims to describe functionality at a very high level, then
partition it repeatedly into more detailed levels one level at a time. It includes HDL
model design, synthesis and P&R, we will describe each of these steps in the following
subsections. The top-down design flow is illustrated in figure 3.4. Notice that it requires
a fully characterized standard cells library with all necessary files (see section 3.1).
Remark: for this section, we used the folder architecture provided by Alain Vachoux
during the EDATP course, see Appendix A for more details.
Figure 3.4: Top-down design flow. See [1].

3.2.1 HDL model design
The first step in top-down design is the creation of synthesizable RTL models. Such
models describe the structure and the behavior of the design at a relatively high level
of abstraction. The model has to be synthezible in order to be correctly mapped during
the next step. It is described in a HDL such as Verilog or VHDL.
Once the model is described, it has to be validated with a pre-synthesis simulation to

be sure that it has been well implemented. No timing are considered at that stage as
the description is technology independant. This step is illustrated in section 4.2.1 with
the DES algorithm. If the model is functionnal, it can be synthesized.
3.2.2 Synthesis
Logic synthesis is the process of converting a high level description of the design into
an optimized gate level representation, given a standard cell library and certain design
constraints. The synthesis step generates three output files: a Verilog gate-level netlist
that can be used for post-synthesis simulation and input for the P&R step, a SDC design
contraints file that will be later used for P&R, and a SDF description which contains
delay information. These delays are correct for the gates but only estimated for the
interconnections. The synthesis steps are shown in figure 3.5.
Figure 3.5: Synthesis flow. See [17].

To synthesize a HDL model with the CML library, we used a TCL script written by
Stephane BADEL during his PhD. Every step can be done by writing manually the
command in the synthesis tool terminal, but it is faster to run a script. This script
includes in the synthesis tool a .db technology file as target library, a .pdb physical
technology file and the milkyway library generated during the various CML library
characterization steps.
This DES 1.tcl script is located in the /SNPS DC/BIN folder. Before running it you
should modify the MCML HOME variable to match your home library directory. If
necessary change the name of process, cell library, used corner and technology directory.
Then modify the project variables (PROJECT DIR, DESIGN, ARCH NAME, ...) to
use the design you want to synthesize.
Finally, modify the synthesis constraints in the constraints.tcl file located in the same
folder that the main script. Modify the CLK PERIOD variable to the desired one and
the CLK NAME variable to match your design clock name.
To run the script, open the Synopsys synthesis tool DC SHELL from the SPNS DC
folder by typing dc shell -f BIN/DES 1.tcl. It will run the DES 1.tcl script. The three
files mentionned earlier (located in /HDL for the .v file, /SNPS DC/SDC for the .sdc
file and /SNPS DC/TIM for the .sdf file) and different reports that can be found in the
/SNPS DC/RPT folder.
Once the synthesis is done, the designer can run a post-synthesis simulation in order
to have a timing estimation of his design. This estimation will only take into account
timing delays of physical cells and no interconnect delays. The same testbench as the one
developed for the RTL model verification is used. It is during this step that the Verilog
library compiled at section 3.1.2.8 is used. See [1] for more details. After successful
verification, the P&R can begin.
3.2.3 Placement and routing
The last step of semi-custom design flow is the placement and routing of the synthesized
design. During this operation, each cell is placed according to the input Verilog gate-level
netlist, and interconnections are made between the cells. Special nets such as power or
ground wires and clocks are usually routed separately to meet specific contraints (voltage
drop, clock skew, ...). At the end, a complete layout of the design is released. This step
needs several input files: a Verilog gate-level netlist and a SDC timing constraint file,
both generated during synthesis, as well as LEF technology files and .lib timing librairies
generated during the library characterization.
The CML P&R is particular since each cell has differential inputs and outputs. The
P&R tool will first place the cells normally, but the routing will be decomposed in two
different part. The fat pins created during the library characterization step will be
routed with fat wires, like a normal non-differential design. In a second time, a special
script will split up these wires to get two normal wires. This way ensure the same path
length for the differential signal and therefore exclude the problem of different signal
delays for the differential signals.
To do so, a TCL script also written by Stephane BADEL during his PhD will be used.
This script is located in the /CDS SOCE/BIN folder. To run the script, first launch the
Cadence P&R tool Encouter by typing Encouter in the terminal from the /CDS SOCE
folder, then type source BIN/DES CML.tcl. Three files will be created: a geometric
description (layout) in GDS2 format that will be used for tape-out, a new Verilog gate-
level netlist containing optimizations made by Encounter (e.g. buffer insertion) and a
SDF file including now accurate delays of both cells and interconnect. These files are
respectively located in /CDS SOCE/DEX, /CDS SOCE/HDL and /CDS SOCE/TIM.
To validate the P&R stage, .sdf and .v files previously generated are used to run a
post-place+route simulation. The functionnality of the design with final timing can be
checked, and the layout can be sent for tape-out.
Chapter 4
DES algorithm top-down design

with CML and CMOS logic
In this Chapter, we will illustrate the use of the newly obtained CML library with a
concrete example: the DES algorithm. The DES is a very popular encryption algorithm.
It stands for Data Encryption Standard and was invented in the early 1970s at IBM.
4.1 DES working principle
We chose an encryption algorithm because CML has an advantage to be used in cryp-

tography (see chapter 2).
The primary part of the DES algorithm is formed by the following blocks:
• Two 32bits register (named R and L for the Right and Left part of the message)
• A bloc named the F-function
• A two input 32bits XOR gate
• A key scheduler (i.e. a key generator)
• An initial permutation block
• An Inverse initial permutation block
21
Figure 4.1: Overview of the primary loop in the DES. See [16]
The blocks are connected together as seen in figure 4.1.
It is important to realize that there are in reality only one L register, R register, F-
function and XOR gate. They are looped in a way that L(t+1)=R(t), R(t+1)=L(t)
XOR F(t) and F(t)=F(R(t)) with the key K(t). It is a synchronous design and at each
clock cycle, the loop is executed once, requiring 16 cycles in order to complete the total
16 times the loop. At initialization, L(0) equals the left 32bits of the message and R(0)
equals the right 32bits of the message. When the encoding is finished, the result is
contained in L(15) and R(15). At the input of this loop is the initial permutation block,
given in figure 4.2 and at the output of this loop is the inverse initial permutation block,
given in figure 4.3.
The output of the inverse initial permutation block contains the encoded message.
Figure 4.2: Initial permutation block. See [15]
Figure 4.3: Inverse initial permutation block. See [15]
Let’s now analyze the content of the F-function more in detail. It is formed by the
following parts:
• An expansion unit
• A two input 48bits XOR gate
• Eight S-boxes
• A permutation block
The parts are connected as shown in figure 4.4. The expansion block is used to convert
the 32bits input from the R register to a 48bits value. In order to achieve this, half of
the input (i.e. 16bits) are duplicated. Additionally, they are permutated.
The details of which bits are duplicated and how they are permutated can be found in
figure 4.5. The table should be read the following way: the output bit is the position
of the table, and the number indicated at that position is the input bit. If we consider
the position 11 (2nd row, 5th colomn), the value is 8. This means that the input bit 8
is now the output bit 11. The hardware implementation of the expansion block simply
consists in wires since this expansion is a constant function.
Figure 4.4: Details of the F-function schematic. See [16]
Figure 4.5: Details of the expansion block. See [15]
The result of the expansion block is then ‘XORED’ with the KEY. The output of this
XOR gate is then separated in eight 6bits values which each enter one of the eight S-
boxes. Each S-box transforms the 6bits input to a 4bits value, following the principle
described in figure 4.6. In this figure, the column is given by the bits 2,3,4 and 5 while
the row is given by the bits 1 and 6: e.g. assume bits 1 to 6 are equal to ‘110010’. The
row is then ‘10’ which is 2 in decimal. The column is then ‘1001’ which is 9 in decimal.
The output of the S-box is thus 12, ‘1100’ in binary.
The output of all the S-boxes are then connected to a Permutation block which simply
rewires the 32bits input to a new 32bits output. The details of the Permutation block
are described in figure 4.7.
Finally, the DES includes a Key Scheduler. The Key Scheduler relies on a specific Key.
This key will generate all the necessary ‘subkeys’ for the decryption and encryption.
The key scheduler contains the following parts:

Figure 4.6: Details of the S-Box. See [15]

Figure 4.7: Details of the permutation block. See [15]
• An input permutation block (PC1)
• An output permutation block (PC2)
• Two 28bits registers C and D
• Binary ‘rollers’ that will shift the registers left
The primary key is a 64bits code. The initial step is to permutate this key with the help
of PC1. PC1 is a permutation block that also reduces the size of the input binary code
from 64bits to 56bits. The hardware implementation of this block consists of wires since
it is a constant permutation. The details on the rewiring of PC1 is detailed in figure
4.8.
Figure 4.8: Details of the PC1. See [15]
Similarly to the primary encryption loop (with the R, L registers), the key scheduler is
a synchronous circuit that is looped on itself. The ‘unlooped’ version of the circuit is
given in figure 4.9.
The content of the register C and D are rolled by either 1 or 2 depending on which key
we are generating, see figure 4.10 (the rollers apply a real rotation, not a simple shift).
After every clock cycle, the content of the registers C and D are concatenated and
connected to the second permutation block PC2, given in figure 4.11. The output of
PC2 is the desired key.
Figure 4.9: Details of the Key Scheduler. See [16]
Figure 4.10: Details of the shifters. See [15]
Figure 4.11: Details of the PC2. See [15]
The key scheduler also works in sixteen clock cycles and each key given at every cycle
is the one necessary to the F-function at the same step in the primary encryption loop.
Since the DES algorithm relies heavily on loops, it is very compact because little hard-
ware is needed. The huge advantage of the DES is the fact that both encryption and
decryption can be done by the exact same hardware. The principle is to chose in which
direction the loops should be executed. By generating the keys in reverse order, the
circuit decodes instead of encoding.
4.2 CMOS and CML implementation of DES : comparison
This section is dedicated to the practical study of the CML library. We designed the
DES algorithm in both CMOS and CML technologies in order to be able to observe
differences in size, consumption and general performance.
4.2.1 HDL design
The DES algorithm is implemented with a FSM. The FSM is done with five states:
• IDLE
• INITIALIZE
• WAIT KEY
• OPERATE
• PRINT
The states are linked as shown in figure 4.12.
Figure 4.12: Details of the DES FSM.
The IDLE state is the default state. During idle, the loop counter is reset and the DES
is waiting for the start signal to be set. Once the start signal is set, the DES enters the
INITIALIZATION state which performs the “initial permutation” on the input message
and assigns it to the L and R registers. The following state, WAIT KEY state, is an
empty state useful for synchronizing the key generation with the correct step in the DES
primary loop. The next state, OPERATE state, is dedicated to the primary DES loop.
During this step, the DES cycles through the loop sixteen times as intended by the
algorithm. Each cycle, the L and R registers are updated with the and the loop counter
is incremented. Once the loop counter reaches sixteen, the DES enters the PRINT state
which executes the final permutation of the concatenated value of L and R registers.
Finally, the value is assigned to the output and the DES returns in the IDLE state.
A full encryption/decryption process takes 19 clock cycles. The VHDL code of the DES
algorithm can be found in appendix B.
In parallel to primary loop is the key scheduler. The FSM of the key scheduler is
displayed in figure 4.13.
Figure 4.13: Details of the key scheduler FSM.
The key scheduler FSM is composed of only three states. The default state is the IDLE
state. The key scheduler is waiting for a start signal and depending on the mode that is
selected (decoding = ‘1’ and encoding = ‘0’) the key scheduler will enter either mode.
Both modes are identical in the difference that the rolling of the C and D registers will
be done in two different directions. For encoding, the registers are rolled to the left and
for decoding, the registers are rolled to the right. So at each clock cycle, a subkey is
generated by the key scheduler and “sent” to the DES FSM.
The permutations and expansions blocs were simply coded as rewiring blocks, as de-
scribed above.
The DES implemented could have been improved in several ways. It could have been
included in the DES to encode and decode in fewer clock cycles. We could have used
the same state for decoding and encoding in the key scheduler, simply using a roll to
the right or to the left depending on the selected mode. The purpose here, however, was
not to design the most efficient DES but simply to prove that it was possible to design
it with the CML library.
4.2.2 Synthesis
This section will show and compare the results of the DES synthesis with CMOS 90 nm
and CML library.
4.2.2.1 CMOS
The DES has been synthesized with a 1.2 ns clock period constraint, using a modified
version of a synthesis script provided by Alain Vachoux during the EDATP course. The
speed, area and power performances are resumed in table 4.1. For more details, please
consult the dedicated reports in the /SNPS DC/RPT folder.
Slack 0.0 ns (MET)

Speed 833.3 MHz
Area 14108.08 µm2
Power 4.2268 mW
Number of cells 1923
Table 4.1: CMOS synthesized DES performances
The mapped design was successfully simulated in Modelsim with a clock period of 1.2
ns.
4.2.2.2 CML
Due to the corner used for the CML library characterization process (supply voltage
of 0.5 V, swing voltage of 200mV and bias current of 100 pA), we were only able to
synthesis the DES with a 0.4 ms clock period, using the script mentionned in section
3.5. The speed, area and power performances are resumed in table 4.2. For more details,
please consult the dedicated reports in the /SNPS DC/RPT folder.
Slack 1.56 ns (MET)

Speed 2.5 KHz
Area 326555.6 µm2
Power 316.01 pW
Table 4.2: CML synthesized DES performances
The mapped design was successfully simulated in Modelsim with a clock period of 0.4
ms. However the power doesn’t seem correct. We expected the consumption to be in
the order of:
n
X
P = Ibias · VDD
i=1
where n is the number of gates. The calculated value, taking into consideration table
4.3, is described below:
1 1 1
P = 100·10−12 (293· + 8· + 993·1 +111·2 +163·4 +3· + 131·1 +188·2 +73·4 +11·1
2 4 4
1 1
+28·2+81·4+76· +14·1+63·2+50·4+140·1+1·4+5· +2·1+9·2+51·4+1·2)·0.5
2 2
P = 100 · 10−12 · 3956.75 · 0.5 ≈ 198nW
Driving Strength X1 X2 X4 X8 X16

1
FFs, HA and FA gates 2 · ISS ISS 2 ·ISS 4 · ISS 8 · ISS
1 1
Other gates 4 · ISS 2 · ISS ISS 2 ·ISS 4 · ISS
Table 4.3: Driving strength and bias current for different gates
We can see that the theoretical power consumption is more than 600 times the one
obtained in the synthesis. We believe that our synthesis tool doesn’t understand how
the CML cells actually work; that there are sources that draw constant current from the
power lines. The other parameters, however, seem consistent.
4.2.2.3 Comparison
Doing a comparison between the two different libraries is difficult because they differ
in many ways. the CMOS 90 nm library has a supply voltage of 0.9 V and the CML
library has a supply voltage of 0.5 V specially made for ultra-low power applications.
This is why the CML synthesized DES consumes a few nW, but is very slow compared
to the CMOS 90nm synthesized DES.
We can also see that the CML version is more than 23 times bigger than the CMOS.
This isn’t surprising since the CMOS library is designed in a 90 nm technology and the
CML library is made in a 180 nm technology and also that CML cells are really big due
to the load and tail transistors. Moreover the differential input/output pins occupy a
relatively large area in the layout.
4.2.3 Placement and routing
4.2.3.1 CMOS
The mapped DES has been placed and routed with a 1.2 ns clock cycle constraint, using
a modified version of the P&R script provided by Alain Vachoux during the EDATP
course. You can see the final layout in figure 4.14. The speed, area and power perfor-
mances are resumed in table 4.4. For more details, please consult the dedicated reports
in the /CDS SOCE/RPT folder.
Slack 0.037 (MET)

Speed 833.3 MHz
Total area of chip 27391.388 µm2
Power 8.478 mW
Table 4.4: CMOS pared DES performances
The pared design was successfully simulated in Modelsim.

Figure 4.14: Final pared DES in CMOS 90nm technology
4.2.3.2 CML
Despite many hours spent trying to make the P&R CML script work we weren’t able to
fix the errors, meaning that the final CML DES has not been pared. The reasons and
the further work will be described in the conclusion.
Chapter 5
Conclusion
During this project, our goal was to make a complete semi-custom design flow with a
CML library. Having faced different problems, the first conclusion is that today’s micro-
electronic is completly dependant of the EDA tools available on the market. As CML
is not as popular as standard CMOS logic, these tools are not designed to handle CML
synthesis and routing operations. This means that even if you find a new breakthrough
logic family and use it massively you have to wait on the EDA companies to implement
it in their tools.
While comparing the actual implementation of a CML design with an equivalent CMOS
design is irrelevant at the moment, the CML has clearly shown many advantages espe-
cially with ultra-low power embedded applications. Even if the CML implementation of
our DES runs with a 2.5 KHz clock which is not that fast, it only consumes approxi-
mately 200 nW, which is almost nothing. As a consequence, this logic could be used for
very power hungry parts of a circuit, while the rest could be done in standard CMOS
logic.
5.1 Encountered difficulties
During this project we faced two main problems that couldn’t entirely be solved. The
first one was to make the library characterization scripts work. Having no knowledge
of SKILL, C-shell, Perl languages and Linux environment nor commands, it was hard
to understand what exactly they were doing. Furthermore these scripts were poorly
35
documented and were written in 2009 so many links pointing on files in LSM server
were broken, and various Assura and Cadence licenses were outdated. We spent tens
of hours searching for Perl packages and QRC extraction files in the server and despite
hours passed with LSM collaborators trying to repair the scripts, we were unable to
fix the characterize.csh script. Characterize.csh runs undefinitely and it has been really
troublesome to find exactly where the problem lies due to a very vaste and complex folder
structure. Since this characterization step is mandatory to use the CML library in a
semi-custom design approach, we used the library found in the LSM archives compiled
by Mohammad Beikahmadi during his master project to do the DES synthesis and P&R.
The second problem was to include the compiled CML library files into Design Vision
and Encouter tools. The synthesis and P&R scripts supposed to work ’as is’ were harder
to fix and to understand than expected, especially with the Milkyway library setup in
synthesis script. We finally manage to make the CML synthesis script work but the
P&R script is still bugging. It needs a Perl environment that we didn’t find and due to
the operation complexity, we couldn’t place and route the DES as planned.
5.2 What we learned
Our work was exclusively in the linux environment. We became familiar with it and
learned some useful commands necessary to be able to freely navigate and manage files.
The study of all kinds of scripts in SKILL, Perl, C-shell and TCL has made us more
comfortable with the respective languages. We now have a good overview of the steps
needed to fully characterize a homemade library in order to use it in a semi-custom
approach. We also increased our knowledge of Modelsim, Design Vision and Encounter
tools that will be very useful for our future career.
We discovered that there are other ways to design integrated circuits than with regular
CMOS logic. The CML topology works in a totally different way as logic operations are
made in current domain instead of the traditionnal voltage domain. This has given us
a broader view of the electronics design methodology.
We finally learned the importance of documenting and commenting the work done. It
doesn’t matter much ’prima facie’ but it really helps other ingeneers to continue the
work done and then save time and money. That’s what we tried to do with this report.
5.3 Future work
The work is yet to be finished due to the faced problems. It has slowed us down and
have unabled us to do all the planned steps. The next thing to do would be to fix
the characterize.csh and P&R scripts. It requires a very good understanding of Perl
language, library characterization process and P&R steps.
Then a good comparison between CMOS and CML libraries could be done using the
same technology in both standard librairies and the same supply voltage. As the speed
of CML cells only depends on the bias current, the characterization paramaters can be
modified until CMOS and CML P&Red design speeds are similar. This would enable
help us to compare relevantly both power and area.
Appendix A
Semi-custom design directories

architecture
39
Appendix B
VHDL implementation of DES

algorithm
1 library ieee ;
use ieee . std_lo gic_1164 . all ;
3 use ieee . numeric_std . all ;
5 entity DES is
port (
7 TEXT_IN : IN s t d _ l o g ic _ v e c t o r (0 to 63);
KEY : IN s t d _ l o g i c _ v e c t o r (0 to 63);
9 CLK : IN std_logic ;
MODE : IN std_logic ; -- cipher : 0 , d e c i p h e r : 1
11 START : IN std_logic ;
RST_b : IN std_logic ;
13 TEXT_OUT : OUT s t d _ lo g i c _ v e c t o r (0 to 63)
);
15 end entity ;
17 architecture rtl of DES is

type state_type is ( state_idle , state_init , state_wait_key , state_op ,
19 state_print );
signal state_reg , state_next : state_type ;
21
signal R_reg , R_next , L_reg , L_next : unsigned (0 to 31);
23 signal TEXT_OUT_reg , TEXT_OUT_next : s t d _ l o g i c _ v e c t o r (0 to 63);
signal K_i_reg , K_i_next : st d _ l o g i c _ v e c t o r (0 to 47);
25 signal round_counter_next , r o u n d _ c o u n t e r _ r e g : unsigned (3 downto 0);
27 signal Initial_Permutation_in , Initial_permutation_out ,

Final_Permutation_in , F i n a l _ P e r m u t a t i o n _ o u t : s t d _ l o g i c _ v e c t o r (0 to 63);
29 signal Ffunction_in , Ffunction_out : s t d _ l o g i c _ v e c t o r (0 to 31);
41
31 signal start_ks : std_logic ;
33 -- C o m p o n e n t s
component Ffunction
35 port (
R : IN s t d _ l o g i c _ v e c t o r (0 to 31); -- input to cipher
37 K : IN s t d _ l o g i c _ v e c t o r (0 to 47); -- key
Y : OUT s t d _ l o g i c _ v e c t o r (0 to 31)); -- c i p h e r e d output
39 end component ;
41 component I n i t i a l P e r m u t a t i o n
port (
43 Input : in s t d _ l o g i c _ v e c t o r (1 to 64);
Output : out s t d _ l o g i c _ v e c t o r (0 to 63));
45 end component ;
47 component F i n a l P e r m u ta t i o n
port (
51 end component ;
53 component KeyScheduling is
port (
55 KEY : IN s t d _ l o g i c _ v e c t o r (0 to 63);
START : IN std_logic ;
57 MODE : IN std_logic ; -- 0 : cipher , 1 : d e c i p h e r
RST_b : IN std_logic ;
59 CLK : IN std_logic ;
Ki : OUT s t d _ l o g i c _ v e c to r (0 to 47));
61 end component ;
63 begin
65 process ( CLK , RST_b )

begin
67 if RST_b = ’0 ’ then
-- reset all r e g i s t e r s
69 TEXT_OUT_reg <= ( others = > ’1 ’);
r o un d _ c o u n t e r _ r e g <= ( others = > ’0 ’);
71 L_reg <= ( others = > ’0 ’);
R_reg <= ( others = > ’0 ’);
73 K_i_reg <= ( others = > ’0 ’);
state_reg <= state_idle ;
75 elsif rising_edge ( CLK ) then
L_reg <= L_next ;
77 R_reg <= R_next ;
TEXT_OUT_reg <= TEXT_OUT_next ;

79 r o u n d _ c o u n t e r _ r e g <= r o u n d _ c o u n t e r _ n e x t ;
K_i_reg <= K_i_next ;
81
state_reg <= state_next ;
83 end if ;
end process ;
85
87 process ( state_reg , L_reg , R_reg , TEXT_OUT_reg , START , round_counter_reg ,

Initial_permutation_out , Final_Permutation_out , Ffunction_out )
89 begin
91 L_next <= L_reg ;

R_next <= R_reg ;
93 state_next <= state_reg ;
TEXT_OUT_next <= TEXT_OUT_reg ;
95 r o u n d _ c o u n t e r _ n e x t <= r o un d _ c o u n t e r _ r e g ;
start_ks <= ’0 ’;
97
TEXT_OUT <= TEXT_OUT_reg ;
99
case state_reg is
101
when state_idle = > r o u n d _ c o u n t e r _ n e x t <= ( others = > ’0 ’);
103 if START = ’1 ’ then
start_ks <= ’1 ’; -- starts K e y S c h e d u l i n g
105
state_next <= state_init ;
107 end if ;
109 when state_init = > start_ks <= ’0 ’;

-- Initial p e r m u t a t i o n for round 1
111 L_next <= unsigned ( I n i t i a l _ p e r m u t a t i o n _ o u t (0 to 31));
R_next <= unsigned ( I n i t i a l _ p e r m u t a t i o n _ o u t (32 to 63));
113
state_next <= sta te_wait _key ;
115
when s tate_wa it_key = > state_next <= state_op ;
117
when state_op = > if std_match ( s t d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 1111 " ) then
119
state_next <= state_print ;
121 end if ;
123 L_next <= R_reg ;

R_next <= L_reg xor unsigned ( Ffunction_out );
125
r o u n d _ c o u n t e r _ n e x t <= r o u n d _ c o u n t e r _ r e g + " 0001 " ;

127
when state_print = > TEXT_OUT_next <= F i n a l _ P e r m u t a t i o n _ o u t ;
129
state_next <= state_idle ;
131 end case ;
end process ;
133
135 I n i t i a l _ P e r m u t a t i o n _ i n <= TEXT_IN ;

F i n a l _ P e r m u t a t i o n _ i n <= s t d _ l o g i c _ v e c t o r ( R_reg ) & s t d _ lo g i c _ v e c t o r ( L_reg );
137
Ffunction_in <= s t d _ l o g i c _ v e ct o r ( R_reg );
139
I N I T I A L _ P E R M U T A T I O N : I n i t i a l P e r m u t a t i o n port map ( Initial_Permutation_in ,
141 I n i t i a l _ p e r m u t a t i o n _ o u t );
143 KEY_ SCHEDULI NG : KeyScheduling port map ( KEY , start_ks , MODE ,

RST_b , CLK , K_i_next );
145
F_FUNCTION : Ffunction port map ( Ffunction_in , K_i_reg ,
147 Ffunction_out );
149 F I N A L _ P E R M U T A T I O N : Fi n a l P e r m u t a t i o n port map ( Final_Permutation_in ,

F i n a l _ P e r m u t a t i o n _ o u t );
151
end architecture ;
Code/DES.vhd
library ieee ;
2 use ieee . std_lo gic_1164 . all ;
use ieee . numeric_std . all ;
4
entity KeyScheduling is
6 port (
KEY : IN s t d _ l o g i c _ v e c t o r (1 to 64);
8 START : IN std_logic ;
MODE : IN std_logic ; -- 0 : cipher , 1 : d e c i p h e r
10 RST_b : IN std_logic ;
CLK : IN std_logic ;
12
Ki : OUT s t d _ l o g i c _ v e c to r (0 to 47)
14 );
end entity ;
16
architecture rtl of KeyScheduling is
18
type state_type is ( state_idle , state_cipher , s tate_de cipher );

20 signal state_reg , state_next : state_type ;
22 signal C_reg , C_next , D_reg , D_next : unsigned (0 to 27);

signal C_perm , D_perm : s t d _ l o g i c _ v e c t o r (0 to 27);
24 signal Ki_reg , Ki_next , K_perm : s t d _ l o g i c _ v e c t o r (0 to 47);
signal round_counter_reg , ro u n d _ c o u n t e r _ n e x t : unsigned (3 downto 0);
26
signal C_D : s t d _l o g i c _ v e c t o r (1 to 56);
28
30 component PC1
port (
C : out s t d _ l o g i c _ v e c to r (0 to 27);
34 D : out s t d _ l o g i c _ v e c t o r (0 to 27));
end component ;
36
component PC2
38 port (
Input : in s t d _ l o g i c _ v e c t o r (0 to 55);
40 Output : out s t d _l o g i c _ v e c t o r (0 to 47));
end component ;
42
begin
44
process ( CLK , RST_b )
46 begin
if RST_b = ’0 ’ then
48 C_reg <= ( others = > ’0 ’);
D_reg <= ( others = > ’0 ’);
50 r o u n d _ c o u n t e r _ r e g <= ( others = > ’0 ’);
Ki_reg <= ( others = > ’0 ’);
52 state_reg <= state_idle ;
elsif rising_edge ( CLK ) then
54 C_reg <= C_next ;
D_reg <= D_next ;
56 r o u n d _ c o u n t e r _ r e g <= r o u n d _ c o u n t e r _ n e x t ;
Ki_reg <= Ki_next ;
58
state_reg <= state_next ;
60 end if ;
end process ;
62
process ( START , MODE , C_reg , D_reg , state_reg , C_perm , D_perm ,
64 round_counter_reg , Ki_reg , K_perm )
66 begin
C_next <= C_reg ;

68 D_next <= D_reg ;
state_next <= state_reg ;
70 r o u n d _ c o u n t e r _ n e x t <= r o u n d _ c o u n t e r _ r e g ;
Ki_next <= Ki_reg ;
72
Ki <= Ki_reg ;
74
76 case state_reg is
78 when state_idle = > if START = ’1 ’ then

r o u n d _ c o u n t e r _ n e x t <= ( others = > ’0 ’);
80 Ki_next <= K_perm ;
82 if MODE = ’0 ’ then -- cipher

C_next <= unsigned ( C_perm ) rol 1;
84 D_next <= unsigned ( D_perm ) rol 1;
86 state_next <= state_cipher ;

else -- d e c i p h e r
88 C_next <= unsigned ( C_perm );
D_next <= unsigned ( D_perm );
90
state_next <= sta te_decip her ;
92 end if ;
else
94 C_next <= ( others = > ’0 ’);
D_next <= ( others = > ’0 ’);
96 end if ;
98 when state_cipher = > if std_match ( s t d _ l o g i c _ v e c t or ( r o u n d _ c o u n t e r _ r e g ) , " 1111 " ) then

100 r o u n d _ c o u n t e r _ n e x t <= ( others = > ’0 ’);
end if ;
102
if std_match ( s t d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 0000 " ) or
104 std_match ( st d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 0111 " ) or
std_match ( st d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 1110 " ) or
106 std_match ( st d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 1111 " ) then
C_next <= C_reg rol 1;
108 D_next <= D_reg rol 1;
110 else
C_next <= C_reg rol 2;
112 D_next <= D_reg rol 2;
end if ;
114 Ki_next <= K_perm ;
116 r o u n d _ c o u n t e r _ n e x t <= r o u n d _ c o u n t e r _ r e g + " 0001 " ;
118 when state_de cipher = > if std_match ( s t d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 1111 " ) then
120 r o u n d _ c o u n t e r _ n e x t <= ( others = > ’0 ’);
end if ;
122
if std_match ( s t d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 0000 " ) or
124 std_match ( st d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 0111 " ) or
std_match ( st d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 1110 " ) or
126 std_match ( st d _ l o g i c _ v e c t o r ( r o u n d _ c o u n t e r _ r e g ) , " 1111 " ) then
C_next <= C_reg ror 1;
128 D_next <= D_reg ror 1;
130 else
C_next <= C_reg ror 2;
132 D_next <= D_reg ror 2;
end if ;
134
Ki_next <= K_perm ;
136 r o u n d _ c o u n t e r _ n e x t <= r o u n d _ c o u n t e r _ r e g + " 0001 " ;
end case ;
138 end process ;
140 C_D <= s t d _ l o g i c _ v e c t o r ( unsigned ( C_reg ) & unsigned ( D_reg ));
142 -- P e r m u t a t i o n PC1
PERMUTATION_1 : PC1 port map ( KEY , C_perm , D_perm );
144
-- P e r m u t a t i o n PC2
146 PERMUTATION_2 : PC2 port map ( C_D , K_perm );
148 end architecture ;
Code/KeyScheduling.vhd
library ieee ;
2 use ieee . std_lo gic_1164 . all ;
use ieee . numeric_std . all ;
4
entity Ffunction is
6 port (
R : IN s t d _ l o g i c _ v e c t o r (0 to 31); -- input to cipher
8 K : IN s t d _ l o g i c _ v e c t o r (0 to 47); -- key
Y : OUT s t d _ l o g i c _ v e c t o r (0 to 31) -- c i p h e r e d output
10 );
end entity ;
12
architecture arch of Ffunction is
14 signal R_expanded : s t d _ l o g i c _ v e c t o r (0 to 47);
signal xor_out : s t d _ l o g i c _ v e c t o r (0 to 47);
16 signal sbox_out : s t d _ l og i c _ v e c t o r (0 to 31);
18 -- C o m p o n e n t s
component Expansion
20 port (
22 Output : out s t d _ l o g i c _ v e c t o r (0 to 47));
end component ;
24
component DESSbox1
26 port (
InputSbox : in s td _ l o g i c _ v e c t o r (0 TO 5);
28 OutputSbox : out s t d _ l o g i c _ v e c to r (0 TO 3));
end component ;
30
component DESSbox2
32 port (
end component ;
36
component DESSbox3
38 port (
end component ;
42
component DESSbox4
44 port (
end component ;
48
component DESSbox5
50 port (
end component ;
54
component DESSbox6
56 port (
InputSbox : in st d _ l o g i c _ v e c t o r (0 TO 5);
end component ;
60
component DESSbox7
62 port (
InputSbox : in s t d _ l o g i c _ v e c t o r (0 TO 5);
64 OutputSbox : out s t d _ l o g i c _ v e c t or (0 TO 3));
end component ;
66
component DESSbox8
68 port (
end component ;
72
component PermutationP
74 port (
end component ;
78
begin
80
-- Input e x p a n s i o n
82 EXP : Expansion port map (R , R_expanded );
84 -- R _ e x p a n d e d xor K
xor_out <= R_expanded xor K ;
86
-- Sbox routing
88 SBOX1 : DESSbox1 port map ( xor_out (0 to 5) , sbox_out (0 to 3));
SBOX2 : DESSbox2 port map ( xor_out (6 to 11) , sbox_out (4 to 7));
96
-- Output p e r m u t a t i o n
98 PERMUTATION : PermutationP port map ( sbox_out , Y );
100 end architecture ;
Code/Ffunction.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 15:05:04 11/02/2012

-- Design Name :
7 -- Module Name : InitialPermutation - Behavioral
-- Project Name :
9 -- Target Devices :
-- Tool v e rs i o n s :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
-- R e v i s i o n 0.01 - File Created
17 -- A d d i t i o n a l C o m m e n t s :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;
21 use IEEE . STD_LOG IC_1164 . ALL ;
23 -- U n c o m m e n t the f o l l o w i n g library d e c l a r a t i o n if using

-- a r i t h m e t i c f u n c t i o n s with Signed or U n s i g n e d values
25 -- use IEEE . N U M E R I C _ S T D . ALL ;
27 -- U n c o m m e n t the f o l l o w i n g library d e c l a r a t i o n if i n s t a n t i a t i n g
-- any Xilinx p r i m i t i v e s in this code .
29 -- library UNISIM ;
-- use UNISIM . V C o m p o n e n t s . all ;
31
entity I n i t i a l P e r m u t a t i o n is
33 Port ( Input : in s t d _ l o g i c _v e c t o r (1 to 64);
35 end I n i t i a lP e r m u t a t i o n ;
37 architecture Behavioral of I n i t i a l P e r m u t a t i o n is
39 begin
41 Output (0) <= Input (58);

Output (1) <= Input (50);
43 Output (2) <= Input (42);
45 Output (4) <= Input (26);
47 Output (6) <= Input (10);
49
51 Output (9) <= Input (52);
53 Output (11) <= Input (36);

55 Output (13) <= Input (20);
57 Output (15) <= Input (4);
59 Output (16) <= Input (62);

61 Output (18) <= Input (46);
63 Output (20) <= Input (30);
65 Output (22) <= Input (14);
67
69 Output (25) <= Input (56);
71 Output (27) <= Input (40);
73 Output (29) <= Input (24);
75 Output (31) <= Input (8);
77 Output (32) <= Input (57);

79 Output (34) <= Input (41);
81 Output (36) <= Input (25);
83 Output (38) <= Input (9);
85
87 Output (41) <= Input (51);
89 Output (43) <= Input (35);
91 Output (45) <= Input (19);
93 Output (47) <= Input (3);
95 Output (48) <= Input (61);

97 Output (50) <= Input (45);
99 Output (52) <= Input (29);
101 Output (54) <= Input (13);

103
105 Output (57) <= Input (55);
107 Output (59) <= Input (39);
109 Output (61) <= Input (23);
111 Output (63) <= Input (7);
113 end Behavioral ;
Code/InitialPermutation.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
-- E n g i n e e r :
4 --
-- Create Date : 12:31:02 15/4/2013
6 -- Design Name :
-- Module Name : Expansion - Behavioral
8 -- Project Name :
-- Target Devices :
10 -- Tool v e r s i o n s :
-- D e s c r i p t i o n :
12 --
-- D e p e n d e n c i e s :
14 --
-- R e v i s i o n :
16 -- R e v i s i o n 0.01 - File Created
-- A d d i t i o n a l C o m m e n t s :
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
use IEEE . STD_LOG IC_1164 . ALL ;
22
-- U n c o m m e n t the f o l l o w i n g library d e c l a r a t i o n if using
24 -- a r i t h m e t i c f u n c t i o n s with Signed or U n s i g n e d values
-- use IEEE . N U M E R I C _ S T D . ALL ;
26
-- U n c o m m e n t the f o l l o w i n g library d e c l a r a t i o n if i n s t a n t i a t i n g
28 -- any Xilinx p r i m i t i v e s in this code .
-- library UNISIM ;
30 -- use UNISIM . V C o m p o n e n t s . all ;
32 entity Expansion is
Port ( Input : in s t d _ l o g i c _v e c t o r (1 to 32);

end Expansion ;
36
architecture Behavioral of Expansion is
38
begin
40
42 Output (1) <= Input (1);

52 Output (10) <= Input (8);
54
56 Output (13) <= Input (9);
58 Output (15) <= Input (11);
60 Output (17) <= Input (13);
62 Output (18) <= Input (12);

64 Output (20) <= Input (14);
66 Output (22) <= Input (16);
68
70 Output (25) <= Input (17);
72 Output (27) <= Input (19);
74 Output (29) <= Input (21);
76 Output (30) <= Input (20);

78 Output (32) <= Input (22);
80 Output (34) <= Input (24);

82
84 Output (37) <= Input (25);
86 Output (39) <= Input (27);
88 Output (41) <= Input (29);
90 Output (42) <= Input (28);

92 Output (44) <= Input (30);
94 Output (46) <= Input (32);
96
end Behavioral ;
Code/Expansion.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 15:05:04 11/02/2012
-- Design Name :
7 -- Module Name : FinalPermutation - Behavioral
-- Project Name :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;

31
entity F i n a l P er m u t a t i o n is
35 end F i n a l P e r m u t a t i o n ;
37 architecture Behavioral of F in a l P e r m u t a t i o n is
39 begin
41 Output (0) <= Input (40);

43 Output (2) <= Input (48);
45 Output (4) <= Input (56);
47 Output (6) <= Input (64);
49
53 Output (11) <= Input (15);
55 Output (13) <= Input (23);
57 Output (15) <= Input (31);
59 Output (16) <= Input (38);

61 Output (18) <= Input (46);
63 Output (20) <= Input (54);
65 Output (22) <= Input (62);
67
69 Output (25) <= Input (5);
71 Output (27) <= Input (13);
73 Output (29) <= Input (21);
75 Output (31) <= Input (29);
77 Output (32) <= Input (36);

79 Output (34) <= Input (44);
81 Output (36) <= Input (52);
83 Output (38) <= Input (60);
85
87 Output (41) <= Input (3);
89 Output (43) <= Input (11);
91 Output (45) <= Input (19);
93 Output (47) <= Input (27);
95 Output (48) <= Input (34);

97 Output (50) <= Input (42);
99 Output (52) <= Input (50);
101 Output (54) <= Input (58);
103
105 Output (57) <= Input (1);
107 Output (59) <= Input (9);
109 Output (61) <= Input (17);
111 Output (63) <= Input (25);
Code/FinalPermutation.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
4 --
-- Create Date : 15:05:04 4/15/2013
6 -- Design Name :
-- Module Name : PC1 - B e h a v i o r a l
8 -- Project Name :
-- Target Devices :
12 --
14 --
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
22
26
-- library UNISIM ;
32 entity PC1 is
Port ( Input : in s t d _ l o g i c _v e c t o r (1 to 64);
34 C : out s t d _ l o g i c _ v e c t or (0 to 27);
D : out s t d _ l o g i c _ v e c t o r (0 to 27));
36 end PC1 ;
38 architecture Behavioral of PC1 is
40 begin
C (0) <= Input (57);
42 C (1) <= Input (49);
C (2) <= Input (41);
44 C (3) <= Input (33);
C (4) <= Input (25);
46 C (5) <= Input (17);
C (6) <= Input (9);
48
C (7) <= Input (1);
50 C (8) <= Input (58);
C (9) <= Input (50);
52 C (10) <= Input (42);
C (11) <= Input (34);
54 C (12) <= Input (26);
C (13) <= Input (18);
56
C (14) <= Input (10);

58 C (15) <= Input (2);
C (16) <= Input (59);
60 C (17) <= Input (51);
C (18) <= Input (43);
62 C (19) <= Input (35);
C (20) <= Input (27);
64
C (21) <= Input (19);
66 C (22) <= Input (11);
C (23) <= Input (3);
68 C (24) <= Input (60);
C (25) <= Input (52);
70 C (26) <= Input (44);
C (27) <= Input (36);
72
74 D (0) <= Input (63);

D (1) <= Input (55);
76 D (2) <= Input (47);
D (3) <= Input (39);
78 D (4) <= Input (31);
D (5) <= Input (23);
80 D (6) <= Input (15);
82 D (7) <= Input (7);

D (8) <= Input (62);
84 D (9) <= Input (54);
D (10) <= Input (46);
86 D (11) <= Input (38);
D (12) <= Input (30);
88 D (13) <= Input (22);
90 D (14) <= Input (14);

D (15) <= Input (6);
92 D (16) <= Input (61);
D (17) <= Input (53);
94 D (18) <= Input (45);
D (19) <= Input (37);
96 D (20) <= Input (29);
98 D (21) <= Input (21);

D (22) <= Input (13);
100 D (23) <= Input (5);
D (24) <= Input (28);
102 D (25) <= Input (20);
D (26) <= Input (12);
104 D (27) <= Input (4);
Code/PC1.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 15:05:04 4/15/2013
-- Design Name :
7 -- Module Name : PC2 - B e h a v i o r a l
-- Project Name :
-- Tool v e r s i o n s :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;

31
entity PC2 is
Output : out s t d _ lo g i c _ v e c t o r (0 to 47));
35 end PC2 ;
37 architecture Behavioral of PC2 is
39 begin
41 Output (1) <= Input (17);
43 Output (3) <= Input (24);

47 Output (7) <= Input (28);
49 Output (8) <= Input (15);

51 Output (10) <= Input (21);
53 Output (12) <= Input (23);
55 Output (14) <= Input (12);
57
59 Output (17) <= Input (8);
61 Output (19) <= Input (7);
63 Output (21) <= Input (20);
65 Output (23) <= Input (2);
67 Output (24) <= Input (41);

69 Output (26) <= Input (31);
71 Output (28) <= Input (47);
73 Output (30) <= Input (30);
75
77 Output (33) <= Input (45);
79 Output (35) <= Input (48);
81 Output (37) <= Input (49);
83 Output (39) <= Input (56);
85 Output (40) <= Input (34);

87 Output (42) <= Input (46);
89 Output (44) <= Input (50);
91 Output (46) <= Input (29);

93
end Behavioral ;
Code/PC2.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 18:35:54 11/02/2012
-- Design Name :
7 -- Module Name : PermutationP - Behavioral
-- Project Name :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;

31
entity PermutationP is
35 end PermutationP ;
37 architecture Behavioral of PermutationP is
39 begin
41 Output (0) <= Input (16);

43 Output (2) <= Input (20);

45 Output (4) <= Input (29);
47 Output (6) <= Input (28);
49
51 Output (9) <= Input (15);
53 Output (11) <= Input (26);
55 Output (13) <= Input (18);
57 Output (15) <= Input (10);
59 Output (16) <= Input (2);

61 Output (18) <= Input (24);
63 Output (20) <= Input (32);
65 Output (22) <= Input (3);
67
69 Output (25) <= Input (13);
71 Output (27) <= Input (6);
73 Output (29) <= Input (11);
75 Output (31) <= Input (25);
77
end Behavioral ;
Code/PermutationP.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 15:18:14 10/25/2012
-- Design Name :
7 -- Module Name : DESSbox1 - Behavioral
-- Project Name :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;

31
33 ENTITY DESSbox1 IS PORT (

InputSbox : in st d _ l o g i c _ v e c t o r (0 TO 5); -- 6 e n t r e s
35 OutputSbox : out s t d _ l o g i c _ v e ct o r (0 TO 3)); -- 4 sorties
END DESSbox1 ;
37
architecture Behavioral of DESSbox1 is
39
begin
41
PROCESS ( InputSbox ) BEGIN
43 CASE InputSbox is -- style case when
45 -- First line : Bit 0=0 and bit 5 = 0
47 WHEN " 000000 " = > OutputSbox <= " 1110 " ;
WHEN " 000010 " = > OutputSbox <= " 0100 " ;
49 WHEN " 000100 " = > OutputSbox <= " 1101 " ;
WHEN " 000110 " = > OutputSbox <= " 0001 " ;
51 WHEN " 001000 " = > OutputSbox <= " 0010 " ;
WHEN " 001010 " = > OutputSbox <= " 1111 " ;
53 WHEN " 001100 " = > OutputSbox <= " 1011 " ;
WHEN " 001110 " = > OutputSbox <= " 1000 " ;
55 WHEN " 010000 " = > OutputSbox <= " 0011 " ;
WHEN " 010010 " = > OutputSbox <= " 1010 " ;
57 WHEN " 010100 " = > OutputSbox <= " 0110 " ;
WHEN " 010110 " = > OutputSbox <= " 1100 " ;
59 WHEN " 011000 " = > OutputSbox <= " 0101 " ;
WHEN " 011010 " = > OutputSbox <= " 1001 " ;
61 WHEN " 011100 " = > OutputSbox <= " 0000 " ;
WHEN " 011110 " = > OutputSbox <= " 0111 " ;
63
-- second line : Bit 0=0 and bit 5 = 1
65
WHEN " 000001 " = > OutputSbox <= " 0000 " ;
67 WHEN " 000011 " = > OutputSbox <= " 1111 " ;
WHEN " 000101 " = > OutputSbox <= " 0111 " ;
69 WHEN " 000111 " = > OutputSbox <= " 0100 " ;
WHEN " 001001 " = > OutputSbox <= " 1110 " ;
71 WHEN " 001011 " = > OutputSbox <= " 0010 " ;
WHEN " 001101 " = > OutputSbox <= " 1101 " ;
73 WHEN " 001111 " = > OutputSbox <= " 0001 " ;
WHEN " 010001 " = > OutputSbox <= " 1010 " ;
75 WHEN " 010011 " = > OutputSbox <= " 0110 " ;
WHEN " 010101 " = > OutputSbox <= " 1100 " ;
77 WHEN " 010111 " = > OutputSbox <= " 1011 " ;
WHEN " 011001 " = > OutputSbox <= " 1001 " ;
79 WHEN " 011011 " = > OutputSbox <= " 0101 " ;
WHEN " 011101 " = > OutputSbox <= " 0011 " ;
81 WHEN " 011111 " = > OutputSbox <= " 1000 " ;
83 -- third line : Bit 0=1 and bit 5 = 0
85 WHEN " 100000 " = > OutputSbox <= " 0100 " ;
WHEN " 100010 " = > OutputSbox <= " 0001 " ;
87 WHEN " 100100 " = > OutputSbox <= " 1110 " ;
WHEN " 100110 " = > OutputSbox <= " 1000 " ;
89 WHEN " 101000 " = > OutputSbox <= " 1101 " ;
WHEN " 101010 " = > OutputSbox <= " 0110 " ;
91 WHEN " 101100 " = > OutputSbox <= " 0010 " ;
WHEN " 101110 " = > OutputSbox <= " 1011 " ;
93 WHEN " 110000 " = > OutputSbox <= " 1111 " ;
WHEN " 110010 " = > OutputSbox <= " 1100 " ;
95 WHEN " 110100 " = > OutputSbox <= " 1001 " ;
WHEN " 110110 " = > OutputSbox <= " 0111 " ;
97 WHEN " 111000 " = > OutputSbox <= " 0011 " ;
WHEN " 111010 " = > OutputSbox <= " 1010 " ;
99 WHEN " 111100 " = > OutputSbox <= " 0101 " ;
WHEN " 111110 " = > OutputSbox <= " 0000 " ;
101
-- fourth line : Bit 0=1 and bit 5 = 1
103
WHEN " 100001 " = > OutputSbox <= " 1111 " ;
105 WHEN " 100011 " = > OutputSbox <= " 1100 " ;
WHEN " 100101 " = > OutputSbox <= " 1000 " ;
107 WHEN " 100111 " = > OutputSbox <= " 0010 " ;
WHEN " 101001 " = > OutputSbox <= " 0100 " ;
109 WHEN " 101011 " = > OutputSbox <= " 1001 " ;
WHEN " 101101 " = > OutputSbox <= " 0001 " ;
111 WHEN " 101111 " = > OutputSbox <= " 0111 " ;
WHEN " 110001 " = > OutputSbox <= " 0101 " ;
113 WHEN " 110011 " = > OutputSbox <= " 1011 " ;
WHEN " 110101 " = > OutputSbox <= " 0011 " ;
115 WHEN " 110111 " = > OutputSbox <= " 1110 " ;
WHEN " 111001 " = > OutputSbox <= " 1010 " ;
117 WHEN " 111011 " = > OutputSbox <= " 0000 " ;
WHEN " 111101 " = > OutputSbox <= " 0110 " ;
119 WHEN " 111111 " = > OutputSbox <= " 1101 " ;
121 WHEN OTHERS = > OutputSbox <= " 1010 " ; -- Should never happen
123 END CASE ;

END PROCESS ;
125
127
end Behavioral ;
Code/DESSbox1.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 0 9 : 1 5 : 2 9 1 0 / 2 6 / 2 0 1 2
-- Design Name :
7 -- Module Name : D E S S b o x 2 - B e h a v i o r a l
-- Project Name :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;

31

35 OutputSbox : out s t d _ l o g i c _ v e c to r (0 TO 3)); -- 4 sorties
END DESSbox2 ;
37
39 architecture Behavioral of DESSbox2 is
41 begin
43 PROCESS ( InputSbox ) BEGIN

CASE InputSbox is -- style case when
45
-- First line : Bit 0=0 and bit 5 = 0
47
WHEN " 000000 " = > OutputSbox <= " 1111 " ;
49 WHEN " 000010 " = > OutputSbox <= " 0001 " ;
WHEN " 000100 " = > OutputSbox <= " 1000 " ;
51 WHEN " 000110 " = > OutputSbox <= " 1110 " ;
WHEN " 001000 " = > OutputSbox <= " 0110 " ;
53 WHEN " 001010 " = > OutputSbox <= " 1011 " ;
WHEN " 001100 " = > OutputSbox <= " 0011 " ;
55 WHEN " 001110 " = > OutputSbox <= " 0100 " ;
WHEN " 010000 " = > OutputSbox <= " 1001 " ;
57 WHEN " 010010 " = > OutputSbox <= " 0111 " ;
WHEN " 010100 " = > OutputSbox <= " 0010 " ;
59 WHEN " 010110 " = > OutputSbox <= " 1101 " ;
WHEN " 011000 " = > OutputSbox <= " 1100 " ;
61 WHEN " 011010 " = > OutputSbox <= " 0000 " ;
WHEN " 011100 " = > OutputSbox <= " 0101 " ;
63 WHEN " 011110 " = > OutputSbox <= " 1010 " ;
65 -- second line : Bit 0=0 and bit 5 = 1

WHEN " 000001 " = > OutputSbox <= " 0011 " ;
67 WHEN " 000011 " = > OutputSbox <= " 1101 " ;
WHEN " 000101 " = > OutputSbox <= " 0100 " ;
69 WHEN " 000111 " = > OutputSbox <= " 0111 " ;
WHEN " 001001 " = > OutputSbox <= " 1111 " ;
71 WHEN " 001011 " = > OutputSbox <= " 0010 " ;
WHEN " 001101 " = > OutputSbox <= " 1000 " ;
73 WHEN " 001111 " = > OutputSbox <= " 1110 " ;
WHEN " 010001 " = > OutputSbox <= " 1100 " ;
75 WHEN " 010011 " = > OutputSbox <= " 0000 " ;
WHEN " 010101 " = > OutputSbox <= " 0001 " ;
77 WHEN " 010111 " = > OutputSbox <= " 1010 " ;
WHEN " 011001 " = > OutputSbox <= " 0110 " ;
79 WHEN " 011011 " = > OutputSbox <= " 1001 " ;
WHEN " 011101 " = > OutputSbox <= " 1011 " ;
81 WHEN " 011111 " = > OutputSbox <= " 0101 " ;
85 WHEN " 100000 " = > OutputSbox <= " 0000 " ;
WHEN " 100010 " = > OutputSbox <= " 1110 " ;
87 WHEN " 100100 " = > OutputSbox <= " 0111 " ;
WHEN " 100110 " = > OutputSbox <= " 1011 " ;
89 WHEN " 101000 " = > OutputSbox <= " 1010 " ;
WHEN " 101010 " = > OutputSbox <= " 0100 " ;
91 WHEN " 101100 " = > OutputSbox <= " 1101 " ;
WHEN " 101110 " = > OutputSbox <= " 0001 " ;
93 WHEN " 110000 " = > OutputSbox <= " 0101 " ;
WHEN " 110010 " = > OutputSbox <= " 1000 " ;
95 WHEN " 110100 " = > OutputSbox <= " 1100 " ;
WHEN " 110110 " = > OutputSbox <= " 0110 " ;
97 WHEN " 111000 " = > OutputSbox <= " 1001 " ;
WHEN " 111010 " = > OutputSbox <= " 0011 " ;
99 WHEN " 111100 " = > OutputSbox <= " 0010 " ;
WHEN " 111110 " = > OutputSbox <= " 1111 " ;
101
103
WHEN " 100001 " = > OutputSbox <= " 1101 " ;
105 WHEN " 100011 " = > OutputSbox <= " 1000 " ;
WHEN " 100101 " = > OutputSbox <= " 1010 " ;
107 WHEN " 100111 " = > OutputSbox <= " 0001 " ;
WHEN " 101001 " = > OutputSbox <= " 0011 " ;
109 WHEN " 101011 " = > OutputSbox <= " 1111 " ;
WHEN " 101101 " = > OutputSbox <= " 0100 " ;
111 WHEN " 101111 " = > OutputSbox <= " 0010 " ;
WHEN " 110001 " = > OutputSbox <= " 1011 " ;
113 WHEN " 110011 " = > OutputSbox <= " 0110 " ;
WHEN " 110101 " = > OutputSbox <= " 0111 " ;
115 WHEN " 110111 " = > OutputSbox <= " 1100 " ;
WHEN " 111001 " = > OutputSbox <= " 0000 " ;
117 WHEN " 111011 " = > OutputSbox <= " 0101 " ;
WHEN " 111101 " = > OutputSbox <= " 1110 " ;
119 WHEN " 111111 " = > OutputSbox <= " 1001 " ;
END CASE ;
123 END PROCESS ;
125
Code/DESSbox2.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
4 --
-- Create Date : 0 9 : 3 3 : 5 8 1 1 / 0 2 / 2 0 1 2
6 -- Design Name :
-- Module Name : D E S S b o x 3 - B e h a v i o r a l
8 -- Project Name :
-- Target Devices :
12 --
14 --
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
22
26
-- library UNISIM ;
32
ENTITY DESSbox3 IS PORT (
34 InputSbox : in st d _ l o g i c _ v e c t o r (0 TO 5); -- 6 e n t r e s
OutputSbox : out s t d _ l o g i c _ v e ct o r (0 TO 3)); -- 4 sorties
36 END DESSbox3 ;
38
40
begin
42
44 CASE InputSbox is -- style c a s e W H E N
48 WHEN " 000000 " = > OutputSbox <= " 1010 " ;
WHEN " 000010 " = > OutputSbox <= " 0000 " ;
50 WHEN " 000100 " = > OutputSbox <= " 1001 " ;
WHEN " 000110 " = > OutputSbox <= " 1110 " ;
52 WHEN " 001000 " = > OutputSbox <= " 0110 " ;
WHEN " 001010 " = > OutputSbox <= " 0011 " ;
54 WHEN " 001100 " = > OutputSbox <= " 1111 " ;
WHEN " 001110 " = > OutputSbox <= " 0101 " ;
56 WHEN " 010000 " = > OutputSbox <= " 0001 " ;
WHEN " 010010 " = > OutputSbox <= " 1101 " ;
58 WHEN " 010100 " = > OutputSbox <= " 1100 " ;
WHEN " 010110 " = > OutputSbox <= " 0111 " ;
60 WHEN " 011000 " = > OutputSbox <= " 1011 " ;
WHEN " 011010 " = > OutputSbox <= " 0100 " ;
62 WHEN " 011100 " = > OutputSbox <= " 0010 " ;
WHEN " 011110 " = > OutputSbox <= " 1000 " ;
64
66
WHEN " 000001 " = > OutputSbox <= " 1101 " ;
68 WHEN " 000011 " = > OutputSbox <= " 0111 " ;
WHEN " 000101 " = > OutputSbox <= " 0000 " ;
70 WHEN " 000111 " = > OutputSbox <= " 1001 " ;
WHEN " 001001 " = > OutputSbox <= " 0011 " ;
72 WHEN " 001011 " = > OutputSbox <= " 0100 " ;
WHEN " 001101 " = > OutputSbox <= " 0110 " ;
74 WHEN " 001111 " = > OutputSbox <= " 1010 " ;
WHEN " 010001 " = > OutputSbox <= " 0010 " ;
76 WHEN " 010011 " = > OutputSbox <= " 1000 " ;
WHEN " 010101 " = > OutputSbox <= " 0101 " ;
78 WHEN " 010111 " = > OutputSbox <= " 1110 " ;
WHEN " 011001 " = > OutputSbox <= " 1100 " ;
80 WHEN " 011011 " = > OutputSbox <= " 1011 " ;
WHEN " 011101 " = > OutputSbox <= " 1111 " ;
82 WHEN " 011111 " = > OutputSbox <= " 0001 " ;

86 WHEN " 100000 " = > OutputSbox <= " 1101 " ;
WHEN " 100010 " = > OutputSbox <= " 0110 " ;
88 WHEN " 100100 " = > OutputSbox <= " 0100 " ;
WHEN " 100110 " = > OutputSbox <= " 1001 " ;
90 WHEN " 101000 " = > OutputSbox <= " 1000 " ;
WHEN " 101010 " = > OutputSbox <= " 1111 " ;
92 WHEN " 101100 " = > OutputSbox <= " 0011 " ;
WHEN " 101110 " = > OutputSbox <= " 0000 " ;
94 WHEN " 110000 " = > OutputSbox <= " 1011 " ;
WHEN " 110010 " = > OutputSbox <= " 0001 " ;
96 WHEN " 110100 " = > OutputSbox <= " 0010 " ;
WHEN " 110110 " = > OutputSbox <= " 1100 " ;
98 WHEN " 111000 " = > OutputSbox <= " 0101 " ;
WHEN " 111010 " = > OutputSbox <= " 1010 " ;
100 WHEN " 111100 " = > OutputSbox <= " 1110 " ;
WHEN " 111110 " = > OutputSbox <= " 0111 " ;
102
104
WHEN " 100001 " = > OutputSbox <= " 0001 " ;
106 WHEN " 100011 " = > OutputSbox <= " 1010 " ;
WHEN " 100101 " = > OutputSbox <= " 1101 " ;
108 WHEN " 100111 " = > OutputSbox <= " 0000 " ;
WHEN " 101001 " = > OutputSbox <= " 0110 " ;
110 WHEN " 101011 " = > OutputSbox <= " 1001 " ;
WHEN " 101101 " = > OutputSbox <= " 1000 " ;
112 WHEN " 101111 " = > OutputSbox <= " 0111 " ;
WHEN " 110001 " = > OutputSbox <= " 0100 " ;
114 WHEN " 110011 " = > OutputSbox <= " 1111 " ;
WHEN " 110101 " = > OutputSbox <= " 1110 " ;
116 WHEN " 110111 " = > OutputSbox <= " 0011 " ;
WHEN " 111001 " = > OutputSbox <= " 1011 " ;
118 WHEN " 111011 " = > OutputSbox <= " 0101 " ;
WHEN " 111101 " = > OutputSbox <= " 0010 " ;
120 WHEN " 111111 " = > OutputSbox <= " 1100 " ;
124 END CASE ;

END PROCESS ;
126
128
end Behavioral ;
Code/DESSbox3.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
4 --
-- Create Date : 0 9 : 4 7 : 5 0 1 1 / 0 2 / 2 0 1 2
6 -- Design Name :
8 -- Project Name :
-- Target Devices :
12 --
14 --
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
22
26
-- library UNISIM ;
32
36 END DESSbox4 ;
38
40
begin
42
44 CASE InputSbox is -- style c a s e W H E n

48 WHEN " 000000 " = > OutputSbox <= " 0111 " ;
WHEN " 000010 " = > OutputSbox <= " 1101 " ;
50 WHEN " 000100 " = > OutputSbox <= " 1110 " ;
WHEN " 000110 " = > OutputSbox <= " 0011 " ;
52 WHEN " 001000 " = > OutputSbox <= " 0000 " ;
WHEN " 001010 " = > OutputSbox <= " 0110 " ;
54 WHEN " 001100 " = > OutputSbox <= " 1001 " ;
WHEN " 001110 " = > OutputSbox <= " 1010 " ;
56 WHEN " 010000 " = > OutputSbox <= " 0001 " ;
WHEN " 010010 " = > OutputSbox <= " 0010 " ;
58 WHEN " 010100 " = > OutputSbox <= " 1000 " ;
WHEN " 010110 " = > OutputSbox <= " 0101 " ;
60 WHEN " 011000 " = > OutputSbox <= " 1011 " ;
WHEN " 011010 " = > OutputSbox <= " 1100 " ;
62 WHEN " 011100 " = > OutputSbox <= " 0100 " ;
WHEN " 011110 " = > OutputSbox <= " 1111 " ;
64
66
WHEN " 000001 " = > OutputSbox <= " 1101 " ;
68 WHEN " 000011 " = > OutputSbox <= " 1000 " ;
WHEN " 000101 " = > OutputSbox <= " 1011 " ;
70 WHEN " 000111 " = > OutputSbox <= " 0101 " ;
WHEN " 001001 " = > OutputSbox <= " 0110 " ;
72 WHEN " 001011 " = > OutputSbox <= " 1111 " ;
WHEN " 001101 " = > OutputSbox <= " 0000 " ;
74 WHEN " 001111 " = > OutputSbox <= " 0011 " ;
WHEN " 010001 " = > OutputSbox <= " 0100 " ;
76 WHEN " 010011 " = > OutputSbox <= " 0111 " ;
WHEN " 010101 " = > OutputSbox <= " 0010 " ;
78 WHEN " 010111 " = > OutputSbox <= " 1100 " ;
WHEN " 011001 " = > OutputSbox <= " 0001 " ;
80 WHEN " 011011 " = > OutputSbox <= " 1010 " ;
WHEN " 011101 " = > OutputSbox <= " 1110 " ;
82 WHEN " 011111 " = > OutputSbox <= " 1001 " ;
86 WHEN " 100000 " = > OutputSbox <= " 1010 " ;
WHEN " 100010 " = > OutputSbox <= " 0110 " ;
88 WHEN " 100100 " = > OutputSbox <= " 1001 " ;
WHEN " 100110 " = > OutputSbox <= " 0000 " ;
90 WHEN " 101000 " = > OutputSbox <= " 1100 " ;
WHEN " 101010 " = > OutputSbox <= " 1011 " ;
92 WHEN " 101100 " = > OutputSbox <= " 0111 " ;
WHEN " 101110 " = > OutputSbox <= " 1101 " ;
94 WHEN " 110000 " = > OutputSbox <= " 1111 " ;
WHEN " 110010 " = > OutputSbox <= " 0001 " ;
96 WHEN " 110100 " = > OutputSbox <= " 0011 " ;
WHEN " 110110 " = > OutputSbox <= " 1110 " ;
98 WHEN " 111000 " = > OutputSbox <= " 0101 " ;
WHEN " 111010 " = > OutputSbox <= " 0010 " ;
100 WHEN " 111100 " = > OutputSbox <= " 1000 " ;
WHEN " 111110 " = > OutputSbox <= " 0100 " ;
102
104
WHEN " 100001 " = > OutputSbox <= " 0011 " ;
106 WHEN " 100011 " = > OutputSbox <= " 1111 " ;
WHEN " 100101 " = > OutputSbox <= " 0000 " ;
108 WHEN " 100111 " = > OutputSbox <= " 0110 " ;
WHEN " 101001 " = > OutputSbox <= " 1010 " ;
110 WHEN " 101011 " = > OutputSbox <= " 0001 " ;
WHEN " 101101 " = > OutputSbox <= " 1101 " ;
112 WHEN " 101111 " = > OutputSbox <= " 1000 " ;
WHEN " 110001 " = > OutputSbox <= " 1001 " ;
114 WHEN " 110011 " = > OutputSbox <= " 0100 " ;
WHEN " 110101 " = > OutputSbox <= " 0101 " ;
116 WHEN " 110111 " = > OutputSbox <= " 1011 " ;
WHEN " 111001 " = > OutputSbox <= " 1100 " ;
118 WHEN " 111011 " = > OutputSbox <= " 0111 " ;
WHEN " 111101 " = > OutputSbox <= " 0010 " ;
120 WHEN " 111111 " = > OutputSbox <= " 1110 " ;
122
WHEN OTHERS = > OutputSbox <= " 1010 " ; -- Should never happen
124 END CASE ;
END PROCESS ;
126
128
end Behavioral ;
Code/DESSbox4.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
4 --
-- Create Date : 0 9 : 5 8 : 5 8 1 1 / 0 2 / 2 0 1 2
6 -- Design Name :
8 -- Project Name :
-- Target Devices :
12 --
14 --
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
22
26
-- library UNISIM ;
32
36 END DESSbox5 ;
38
40
begin
42
44 CASE InputSbox is -- style c a s e W H E n
48 WHEN " 000000 " = > OutputSbox <= " 0010 " ;
WHEN " 000010 " = > OutputSbox <= " 1100 " ;
50 WHEN " 000100 " = > OutputSbox <= " 0100 " ;
WHEN " 000110 " = > OutputSbox <= " 0001 " ;
52 WHEN " 001000 " = > OutputSbox <= " 0111 " ;
WHEN " 001010 " = > OutputSbox <= " 1010 " ;
54 WHEN " 001100 " = > OutputSbox <= " 1011 " ;
WHEN " 001110 " = > OutputSbox <= " 0110 " ;
56 WHEN " 010000 " = > OutputSbox <= " 1000 " ;
WHEN " 010010 " = > OutputSbox <= " 0101 " ;
58 WHEN " 010100 " = > OutputSbox <= " 0011 " ;
WHEN " 010110 " = > OutputSbox <= " 1111 " ;
60 WHEN " 011000 " = > OutputSbox <= " 1101 " ;
WHEN " 011010 " = > OutputSbox <= " 0000 " ;
62 WHEN " 011100 " = > OutputSbox <= " 1110 " ;
WHEN " 011110 " = > OutputSbox <= " 1001 " ;
64
66
WHEN " 000001 " = > OutputSbox <= " 1110 " ;
68 WHEN " 000011 " = > OutputSbox <= " 1011 " ;
WHEN " 000101 " = > OutputSbox <= " 0010 " ;
70 WHEN " 000111 " = > OutputSbox <= " 1100 " ;
WHEN " 001001 " = > OutputSbox <= " 0100 " ;
72 WHEN " 001011 " = > OutputSbox <= " 0111 " ;
WHEN " 001101 " = > OutputSbox <= " 1101 " ;
74 WHEN " 001111 " = > OutputSbox <= " 0001 " ;
WHEN " 010001 " = > OutputSbox <= " 0101 " ;
76 WHEN " 010011 " = > OutputSbox <= " 0000 " ;
WHEN " 010101 " = > OutputSbox <= " 1111 " ;
78 WHEN " 010111 " = > OutputSbox <= " 1010 " ;
WHEN " 011001 " = > OutputSbox <= " 0011 " ;
80 WHEN " 011011 " = > OutputSbox <= " 1001 " ;
WHEN " 011101 " = > OutputSbox <= " 1000 " ;
82 WHEN " 011111 " = > OutputSbox <= " 0110 " ;
86 WHEN " 100000 " = > OutputSbox <= " 0100 " ;
WHEN " 100010 " = > OutputSbox <= " 0010 " ;
88 WHEN " 100100 " = > OutputSbox <= " 0001 " ;
WHEN " 100110 " = > OutputSbox <= " 1011 " ;
90 WHEN " 101000 " = > OutputSbox <= " 1010 " ;
WHEN " 101010 " = > OutputSbox <= " 1101 " ;
92 WHEN " 101100 " = > OutputSbox <= " 0111 " ;
WHEN " 101110 " = > OutputSbox <= " 1000 " ;
94 WHEN " 110000 " = > OutputSbox <= " 1111 " ;
WHEN " 110010 " = > OutputSbox <= " 1001 " ;
96 WHEN " 110100 " = > OutputSbox <= " 1100 " ;
WHEN " 110110 " = > OutputSbox <= " 0101 " ;
98 WHEN " 111000 " = > OutputSbox <= " 0110 " ;
WHEN " 111010 " = > OutputSbox <= " 0011 " ;
100 WHEN " 111100 " = > OutputSbox <= " 0000 " ;
WHEN " 111110 " = > OutputSbox <= " 1110 " ;
102
104
WHEN " 100001 " = > OutputSbox <= " 1011 " ;
106 WHEN " 100011 " = > OutputSbox <= " 1000 " ;
WHEN " 100101 " = > OutputSbox <= " 1100 " ;
108 WHEN " 100111 " = > OutputSbox <= " 0111 " ;
WHEN " 101001 " = > OutputSbox <= " 0001 " ;
110 WHEN " 101011 " = > OutputSbox <= " 1110 " ;
WHEN " 101101 " = > OutputSbox <= " 0010 " ;
112 WHEN " 101111 " = > OutputSbox <= " 1101 " ;
WHEN " 110001 " = > OutputSbox <= " 0110 " ;
114 WHEN " 110011 " = > OutputSbox <= " 1111 " ;
WHEN " 110101 " = > OutputSbox <= " 0000 " ;
116 WHEN " 110111 " = > OutputSbox <= " 1001 " ;
WHEN " 111001 " = > OutputSbox <= " 1010 " ;
118 WHEN " 111011 " = > OutputSbox <= " 0100 " ;
WHEN " 111101 " = > OutputSbox <= " 0101 " ;
120 WHEN " 111111 " = > OutputSbox <= " 0011 " ;
122
124
END CASE ;
126 END PROCESS ;
128
Code/DESSbox5.vhd
1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- Company :
3 -- E n g i n e e r :
--
5 -- Create Date : 1 1 : 2 3 : 5 6 1 1 / 0 2 / 2 0 1 2
-- Design Name :
7 -- Module Name : D E S S b o x 6 - B e h a v i o r a l
-- Project Name :
11 -- D e s c r i p t i o n :
--
13 -- D e p e n d e n c i e s :
--
15 -- R e v i s i o n :
--
19 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
library IEEE ;

31
33
OutputSbox : out s t d _ l o g i c _ v e c to r (0 TO 3)); -- 4 sorties
37 END DESSbox6 ;
39
41
begin
43
45 CASE InputSbox is -- style c a s e W H E N
49 WHEN " 000000 " = > OutputSbox <= " 1100 " ;
WHEN " 000010 " = > OutputSbox <= " 0001 " ;
51 WHEN " 000100 " = > OutputSbox <= " 1010 " ;
WHEN " 000110 " = > OutputSbox <= " 1111 " ;
53 WHEN " 001000 " = > OutputSbox <= " 1001 " ;
WHEN " 001010 " = > OutputSbox <= " 0010 " ;
55 WHEN " 001100 " = > OutputSbox <= " 0110 " ;
WHEN " 001110 " = > OutputSbox <= " 1000 " ;
57 WHEN " 010000 " = > OutputSbox <= " 0000 " ;
WHEN " 010010 " = > OutputSbox <= " 1101 " ;
59 WHEN " 010100 " = > OutputSbox <= " 0011 " ;
WHEN " 010110 " = > OutputSbox <= " 0100 " ;
61 WHEN " 011000 " = > OutputSbox <= " 1110 " ;
WHEN " 011010 " = > OutputSbox <= " 0111 " ;
63 WHEN " 011100 " = > OutputSbox <= " 0101 " ;
WHEN " 011110 " = > OutputSbox <= " 1011 " ;
65
67
WHEN " 000001 " = > OutputSbox <= " 1010 " ;
69 WHEN " 000011 " = > OutputSbox <= " 1111 " ;
WHEN " 000101 " = > OutputSbox <= " 0100 " ;
71 WHEN " 000111 " = > OutputSbox <= " 0010 " ;
WHEN " 001001 " = > OutputSbox <= " 0111 " ;
73 WHEN " 001011 " = > OutputSbox <= " 1100 " ;
WHEN " 001101 " = > OutputSbox <= " 1001 " ;
75 WHEN " 001111 " = > OutputSbox <= " 0101 " ;
WHEN " 010001 " = > OutputSbox <= " 0110 " ;
77 WHEN " 010011 " = > OutputSbox <= " 0001 " ;
WHEN " 010101 " = > OutputSbox <= " 1101 " ;
79 WHEN " 010111 " = > OutputSbox <= " 1110 " ;
WHEN " 011001 " = > OutputSbox <= " 0000 " ;
81 WHEN " 011011 " = > OutputSbox <= " 1011 " ;
WHEN " 011101 " = > OutputSbox <= " 0011 " ;
83 WHEN " 011111 " = > OutputSbox <= " 1000 " ;
87 WHEN " 100000 " = > OutputSbox <= " 1001 " ;
WHEN " 100010 " = > OutputSbox <= " 1110 " ;
89 WHEN " 100100 " = > OutputSbox <= " 1111 " ;
WHEN " 100110 " = > OutputSbox <= " 0101 " ;
91 WHEN " 101000 " = > OutputSbox <= " 0010 " ;
WHEN " 101010 " = > OutputSbox <= " 1000 " ;
93 WHEN " 101100 " = > OutputSbox <= " 1100 " ;
WHEN " 101110 " = > OutputSbox <= " 0011 " ;
95 WHEN " 110000 " = > OutputSbox <= " 0111 " ;
WHEN " 110010 " = > OutputSbox <= " 0000 " ;
97 WHEN " 110100 " = > OutputSbox <= " 0100 " ;
WHEN " 110110 " = > OutputSbox <= " 1010 " ;
99 WHEN " 111000 " = > OutputSbox <= " 0001 " ;
WHEN " 111010 " = > OutputSbox <= " 1101 " ;
101 WHEN " 111100 " = > OutputSbox <= " 1011 " ;
WHEN " 111110 " = > OutputSbox <= " 0110 " ;
103
105
WHEN " 100001 " = > OutputSbox <= " 0100 " ;
107 WHEN " 100011 " = > OutputSbox <= " 0011 " ;
WHEN " 100101 " = > OutputSbox <= " 0010 " ;
109 WHEN " 100111 " = > OutputSbox <= " 1100 " ;
WHEN " 101001 " = > OutputSbox <= " 1001 " ;
111 WHEN " 101011 " = > OutputSbox <= " 0101 " ;
WHEN " 101101 " = > OutputSbox <= " 1111 " ;
113 WHEN " 101111 " = > OutputSbox <= " 1010 " ;
WHEN " 110001 " = > OutputSbox <= " 1011 " ;
115 WHEN " 110011 " = > OutputSbox <= " 1110 " ;
WHEN " 110101 " = > OutputSbox <= " 0001 " ;
117 WHEN " 110111 " = > OutputSbox <= " 0111 " ;
WHEN " 111001 " = > OutputSbox <= " 0110 " ;
119 WHEN " 111011 " = > OutputSbox <= " 0000 " ;
WHEN " 111101 " = > OutputSbox <= " 1000 " ;
121 WHEN " 111111 " = > OutputSbox <= " 1101 " ;
123
125
END CASE ;
127 END PROCESS ;
129
Code/DESSbox6.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
4 --
-- Create Date : 1 1 : 3 3 : 0 3 1 1 / 0 2 / 2 0 1 2
6 -- Design Name :
8 -- Project Name :
-- Target Devices :
12 --
14 --
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
22
26
-- library UNISIM ;
32

36 OutputSbox : out s t d _ l o g i c _ v e c to r (0 TO 3)); -- 4 sorties
END DESSbox7 ;
38
42 begin

CASE InputSbox is -- style c a s e W H E N
46
48
WHEN " 000000 " = > OutputSbox <= " 0100 " ;
50 WHEN " 000010 " = > OutputSbox <= " 1011 " ;
WHEN " 000100 " = > OutputSbox <= " 0010 " ;
52 WHEN " 000110 " = > OutputSbox <= " 1110 " ;
WHEN " 001000 " = > OutputSbox <= " 1111 " ;
54 WHEN " 001010 " = > OutputSbox <= " 0000 " ;
WHEN " 001100 " = > OutputSbox <= " 1000 " ;
56 WHEN " 001110 " = > OutputSbox <= " 1101 " ;
WHEN " 010000 " = > OutputSbox <= " 0011 " ;
58 WHEN " 010010 " = > OutputSbox <= " 1100 " ;
WHEN " 010100 " = > OutputSbox <= " 1001 " ;
60 WHEN " 010110 " = > OutputSbox <= " 0111 " ;
WHEN " 011000 " = > OutputSbox <= " 0101 " ;
62 WHEN " 011010 " = > OutputSbox <= " 1010 " ;
WHEN " 011100 " = > OutputSbox <= " 0110 " ;
64 WHEN " 011110 " = > OutputSbox <= " 0001 " ;
68 WHEN " 000001 " = > OutputSbox <= " 1101 " ;
WHEN " 000011 " = > OutputSbox <= " 0000 " ;
70 WHEN " 000101 " = > OutputSbox <= " 1011 " ;
WHEN " 000111 " = > OutputSbox <= " 0111 " ;
72 WHEN " 001001 " = > OutputSbox <= " 0100 " ;
WHEN " 001011 " = > OutputSbox <= " 1001 " ;
74 WHEN " 001101 " = > OutputSbox <= " 0001 " ;
WHEN " 001111 " = > OutputSbox <= " 1010 " ;
76 WHEN " 010001 " = > OutputSbox <= " 1110 " ;
WHEN " 010011 " = > OutputSbox <= " 0011 " ;
78 WHEN " 010101 " = > OutputSbox <= " 0101 " ;
WHEN " 010111 " = > OutputSbox <= " 1100 " ;
80 WHEN " 011001 " = > OutputSbox <= " 0010 " ;
WHEN " 011011 " = > OutputSbox <= " 1111 " ;
82 WHEN " 011101 " = > OutputSbox <= " 1000 " ;
WHEN " 011111 " = > OutputSbox <= " 0110 " ;
84
-- third line : Bit 0=1 and bit 5 = 0
86
WHEN " 100000 " = > OutputSbox <= " 0001 " ;
88 WHEN " 100010 " = > OutputSbox <= " 0100 " ;
WHEN " 100100 " = > OutputSbox <= " 1011 " ;
90 WHEN " 100110 " = > OutputSbox <= " 1101 " ;
WHEN " 101000 " = > OutputSbox <= " 1100 " ;
92 WHEN " 101010 " = > OutputSbox <= " 0011 " ;
WHEN " 101100 " = > OutputSbox <= " 0111 " ;
94 WHEN " 101110 " = > OutputSbox <= " 1110 " ;
WHEN " 110000 " = > OutputSbox <= " 1010 " ;
96 WHEN " 110010 " = > OutputSbox <= " 1111 " ;
WHEN " 110100 " = > OutputSbox <= " 0110 " ;
98 WHEN " 110110 " = > OutputSbox <= " 1000 " ;
WHEN " 111000 " = > OutputSbox <= " 0000 " ;
100 WHEN " 111010 " = > OutputSbox <= " 0101 " ;
WHEN " 111100 " = > OutputSbox <= " 1001 " ;
102 WHEN " 111110 " = > OutputSbox <= " 0010 " ;
104 -- fourth line : Bit 0=1 and bit 5 = 1
106 WHEN " 100001 " = > OutputSbox <= " 0110 " ;
WHEN " 100011 " = > OutputSbox <= " 1011 " ;
108 WHEN " 100101 " = > OutputSbox <= " 1101 " ;
WHEN " 100111 " = > OutputSbox <= " 1000 " ;
110 WHEN " 101001 " = > OutputSbox <= " 0001 " ;
WHEN " 101011 " = > OutputSbox <= " 0100 " ;
112 WHEN " 101101 " = > OutputSbox <= " 1010 " ;
WHEN " 101111 " = > OutputSbox <= " 0111 " ;
114 WHEN " 110001 " = > OutputSbox <= " 1001 " ;
WHEN " 110011 " = > OutputSbox <= " 0101 " ;
116 WHEN " 110101 " = > OutputSbox <= " 0000 " ;
WHEN " 110111 " = > OutputSbox <= " 1111 " ;
118 WHEN " 111001 " = > OutputSbox <= " 1110 " ;
WHEN " 111011 " = > OutputSbox <= " 0010 " ;
120 WHEN " 111101 " = > OutputSbox <= " 0011 " ;
WHEN " 111111 " = > OutputSbox <= " 1100 " ;
122
126 END CASE ;

END PROCESS ;
128
130
end Behavioral ;
Code/DESSbox7.vhd
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 -- Company :
4 --
-- Create Date : 1 1 : 4 7 : 5 6 1 1 / 0 2 / 2 0 1 2
6 -- Design Name :
8 -- Project Name :
-- Target Devices :
12 --
14 --
18 --
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
20 library IEEE ;
22
26
-- library UNISIM ;
32

36 OutputSbox : out s t d _ l o g i c _ v e ct o r (0 TO 3)); -- 4 sorties
END DESSbox8 ;
38
42 begin

CASE InputSbox is -- style c a s e W H E N
46
48
WHEN " 000000 " = > OutputSbox <= " 1101 " ;
50 WHEN " 000010 " = > OutputSbox <= " 0010 " ;
WHEN " 000100 " = > OutputSbox <= " 1000 " ;
52 WHEN " 000110 " = > OutputSbox <= " 0100 " ;
WHEN " 001000 " = > OutputSbox <= " 0110 " ;
54 WHEN " 001010 " = > OutputSbox <= " 1111 " ;
WHEN " 001100 " = > OutputSbox <= " 1011 " ;
56 WHEN " 001110 " = > OutputSbox <= " 0001 " ;
WHEN " 010000 " = > OutputSbox <= " 1010 " ;
58 WHEN " 010010 " = > OutputSbox <= " 1001 " ;
WHEN " 010100 " = > OutputSbox <= " 0011 " ;
60 WHEN " 010110 " = > OutputSbox <= " 1110 " ;
WHEN " 011000 " = > OutputSbox <= " 0101 " ;
62 WHEN " 011010 " = > OutputSbox <= " 0000 " ;
WHEN " 011100 " = > OutputSbox <= " 1100 " ;
64 WHEN " 011110 " = > OutputSbox <= " 0111 " ;
68 WHEN " 000001 " = > OutputSbox <= " 0001 " ;
WHEN " 000011 " = > OutputSbox <= " 1111 " ;
70 WHEN " 000101 " = > OutputSbox <= " 1101 " ;
WHEN " 000111 " = > OutputSbox <= " 1000 " ;
72 WHEN " 001001 " = > OutputSbox <= " 1010 " ;
WHEN " 001011 " = > OutputSbox <= " 0011 " ;
74 WHEN " 001101 " = > OutputSbox <= " 0111 " ;
WHEN " 001111 " = > OutputSbox <= " 0100 " ;
76 WHEN " 010001 " = > OutputSbox <= " 1100 " ;
WHEN " 010011 " = > OutputSbox <= " 0101 " ;
78 WHEN " 010101 " = > OutputSbox <= " 0110 " ;
WHEN " 010111 " = > OutputSbox <= " 1011 " ;
80 WHEN " 011001 " = > OutputSbox <= " 0000 " ;
WHEN " 011011 " = > OutputSbox <= " 1110 " ;
82 WHEN " 011101 " = > OutputSbox <= " 1001 " ;
WHEN " 011111 " = > OutputSbox <= " 0010 " ;
84
-- third line : Bit 0=1 and bit 5 = 0
86
WHEN " 100000 " = > OutputSbox <= " 0111 " ;
88 WHEN " 100010 " = > OutputSbox <= " 1011 " ;
WHEN " 100100 " = > OutputSbox <= " 0100 " ;
90 WHEN " 100110 " = > OutputSbox <= " 0001 " ;
WHEN " 101000 " = > OutputSbox <= " 1001 " ;
92 WHEN " 101010 " = > OutputSbox <= " 1100 " ;
WHEN " 101100 " = > OutputSbox <= " 1110 " ;
94 WHEN " 101110 " = > OutputSbox <= " 0010 " ;
WHEN " 110000 " = > OutputSbox <= " 0000 " ;
96 WHEN " 110010 " = > OutputSbox <= " 0110 " ;
WHEN " 110100 " = > OutputSbox <= " 1010 " ;
98 WHEN " 110110 " = > OutputSbox <= " 1101 " ;
WHEN " 111000 " = > OutputSbox <= " 1111 " ;
100 WHEN " 111010 " = > OutputSbox <= " 0011 " ;
WHEN " 111100 " = > OutputSbox <= " 0101 " ;
102 WHEN " 111110 " = > OutputSbox <= " 1000 " ;
104 -- fourth line : Bit 0=1 and bit 5 = 1
106 WHEN " 100001 " = > OutputSbox <= " 0010 " ;
WHEN " 100011 " = > OutputSbox <= " 0001 " ;
108 WHEN " 100101 " = > OutputSbox <= " 1110 " ;
WHEN " 100111 " = > OutputSbox <= " 0111 " ;
110 WHEN " 101001 " = > OutputSbox <= " 0100 " ;
WHEN " 101011 " = > OutputSbox <= " 1010 " ;
112 WHEN " 101101 " = > OutputSbox <= " 1000 " ;
WHEN " 101111 " = > OutputSbox <= " 1101 " ;
114 WHEN " 110001 " = > OutputSbox <= " 1111 " ;
WHEN " 110011 " = > OutputSbox <= " 1100 " ;
116 WHEN " 110101 " = > OutputSbox <= " 1001 " ;
WHEN " 110111 " = > OutputSbox <= " 0000 " ;
118 WHEN " 111001 " = > OutputSbox <= " 0011 " ;
WHEN " 111011 " = > OutputSbox <= " 0101 " ;
120 WHEN " 111101 " = > OutputSbox <= " 0110 " ;
WHEN " 111111 " = > OutputSbox <= " 1011 " ;
122
124
END CASE ;
126 END PROCESS ;
128
Code/DESSbox8.vhd
Bibliography
[1] Alain Vachoux ‘Top-Down Digital Design Flow’ EDATP Course material (version
7.0, October 2012)
[2] US department of commerce / National Institute of Standards and Technology

‘Data Encryption Standard (DES)’ United States (October 25, 1999)
[3] A. Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz ‘Subthreshold Source-Coupled

Logic Circuits for Ultra Low Power Applications’ IEEE Journal of Solid-State Cir-
cuits, vol. 43, num. 7, p. 1699 - 1710 (2008)
[4] A. Tajalli, M. Alioto and Y. Leblebici ‘Improving Power-Delay Performance of

Ultra Low-Power Subthreshold SCL Circuits’ in IEEE Transaction on Circuits and
Systems-II, vol. 56, num. 2, p. 127-131 (2009)
[5] A. Tajalli, M. Alioto, E. Brauer and Y. Leblebici ‘Improving the power-delay per-
formance in subthreshold source-coupled logic circuits’ International Workshop on
Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon,
Portugal, Integrated Circuit and System Design (2008)
[6] A. Tajalli, E. Brauer and Y. Leblebici ‘Ultra-Low Power 32-bit Pipelined Adder
Using Subthreshold Source-Coupled Logic with 5fJ/stage PDP’ in Microelectronics
Journal, vol. 40, num. 6, p. 973-978 (2009)
[7] A. Tajalli, Y. Leblebici, E. Vittoz and E. J. Brauer ‘Ultra Low Power Subthresh-
old MOS Current Mode Logic Circuits Using a Novel Load Device Concept’ 33rd
European Solid-State Circuits Conference (ESSCIRC), Munich, Germany (2007)
[8] M. Beikahmadi, A. Tajalli and Y. Leblebici ‘A Subthreshold SCL Based Pipelined

Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC’ NORCHIP, Tallinn,
Estonia, THESIS (2008)
85
Bibliography 86
[9] A. Tajalli, F. K. Gurkaynak, Y. Leblebici, M. Alioto and E. J. Brauer ‘Improving

the Power-Delay Product in SCL Circuits Using Source Follower Output Stage’
International Symposum on Circuits and Systems (ISCAS), Seattle, Washington,
USA, THESIS (2008)
[10] A. Tajalli and Y. Leblebici ‘Ultra-Low Power Mixed-Signal Design Platform Us-
ing Subthreshold Source-Coupled Circuits’ Design, Automation, & Test in Europe
(DATE), Dresden, Germany (2010)
[11] A. Tajalli and Y. Leblebici ‘Subthreshold Leakage Reduction: A Comparative Study

of SCL and CMOS Design’ IEEE International Symposium on Circuits and Systems
(ISCAS), Taipei, Taiwan (2009)
[12] Stphane Badel (Advisor: Yusuf Leblebici) ‘MOS current-mode logic standard cells
for high-speed low-noise applications’ EPFL, Lausanne (2008)
[13] Mohammad Beikahmadi ‘Developing a Standard Cell Library for Subthreshold

Source-Coupled Logic’ EPFL, Lausanne (2009)
[14] Michael Schwander ‘Fine-grain Power Gating for MCML Circuits’ EPFL, Lausanne
(2009)
[15] Matthew Fischer ‘How to implement the Data Encryption Standard (DES)’
http://www.utdallas.edu/~edsha/OS2000/des-algorithm-details.txt Uni-
versity of Texas at Dallas (1995)
[16] Eugene Styer ‘DES’ http://people.eku.edu/styere/Encrypt/JS-DES.html

Eastern Kentucky University (Unknown)
[17] Dupenloup, Guy ‘Automatic synthesis script generation for synopsys design
compiler’ http://www.freepatentsonline.com/6836877.html Marly-le-Roi, FR
(2004)

A Practical Approach To CML Technology Design Flow and Implementation

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A practical approach to CML technology

design flow and implementation

Alex Unnervik alex.unnervik@epfl.ch

Demirci Tugba tugba.demirci@epfl.ch

List of Figures vii

3 Semi-custom design flow for CML 9

4 DES algorithm top-down design with CML and CMOS logic 21

A Semi-custom design directories architecture 39

B VHDL implementation of DES algorithm 41

2.1 General CML topology. See [14]. . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 Overview of the primary loop in the DES. See [16] . . . . . . . . . . . . . 22

4.1 CMOS synthesized DES performances . . . . . . . . . . . . . . . . . . . . 30

API Application Programmable Interface

1.2 Report organization

2.1 Working principle

Figure 2.1: General CML topology. See [14].

2.2 CML Circuits

Semi-custom design flow for CML

3.1 Standard cells library creation and characterization

3.1.1 Standard cells library creation

Figure 3.2: Fat pins and wires placement. See [14].

3.1.2 Library characterization flow

3.1.2.1 Logical views creation

3.1.2.2 SPICE netlists extraction

• Their type and reference (e.g. C1)

• The component value in simple case (e.g. 1KΩ for a resistor)

• Possibly the model used

• Possibly a parameters list allowing modification of the model

3.1.2.3 LEF file creation

3.1.2.4 GDS files creation

3.1.2.5 Milkyway files creation

3.1.2.6 Library characterization

Remark: this script has not been successfully debugged.

3.1.2.7 Library compilation

3.1.2.8 Verilog library compilation

In order to be able to do post-synthesis and post-P&R simulations, we need to compile

3.2 Top-down design

Figure 3.4: Top-down design flow. See [1].

3.2.1 HDL model design

Once the model is described, it has to be validated with a pre-synthesis simulation to

Figure 3.5: Synthesis flow. See [17].

3.2.3 Placement and routing

DES algorithm top-down design

4.1 DES working principle

We chose an encryption algorithm because CML has an advantage to be used in cryp-

• A bloc named the F-function

• A two input 32bits XOR gate

• A key scheduler (i.e. a key generator)

• An initial permutation block

• An Inverse initial permutation block

The blocks are connected together as seen in figure 4.1.

Figure 4.2: Initial permutation block. See [15]

Figure 4.3: Inverse initial permutation block. See [15]

• A two input 48bits XOR gate

Figure 4.4: Details of the F-function schematic. See [16]

Figure 4.5: Details of the expansion block. See [15]

The key scheduler contains the following parts: