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    Assignment 5 Unit 5

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    Maharshi Sanand Yadav T
    5 UNIT –V 5.1 Subsystem Design: 5.1.1 Shifters, 5.1.2 Carry skip adder, 5.1.3 carry select adder, 5.1.4 Booth Multiplier, 5.2 Memory Elements: 5.2.1 6T SRAM cell, 5.2.2 1T DRAM cell. 5.3 Sequential Logic Design: 5.3.1 Behaviour of Bi-stable elements, 5.3.2 CMOS D latch and 5.3.3 Edge triggered Flip flops.

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    Assignment 5 Unit 5

    Uploaded by

    Maharshi Sanand Yadav T
    115 views1 page
    5 UNIT –V 5.1 Subsystem Design: 5.1.1 Shifters, 5.1.2 Carry skip adder, 5.1.3 carry select adder, 5.1.4 Booth Multiplier, 5.2 Memory Elements: 5.2.1 6T SRAM cell, 5.2.2 1T DRAM cell. 5.3 Sequential Logic Design: 5.3.1 Behaviour of Bi-stable elements, 5.3.2 CMOS D latch and 5.3.3 Edge triggered Flip flops.

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    5. Assignment 5 Unit 5

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    5 UNIT –V 5.1 Subsystem Design: 5.1.1 Shifters, 5.1.2 Carry skip adder, 5.1.3 carry select adder, 5.1.4 Booth Multiplier, 5.2 Memory Elements: 5.2.1 6T SRAM cell, 5.2.2 1T DRAM cell. 5.3 Sequential Logic Design: 5.3.1 Behaviour of Bi-stable elements, 5.3.2 CMOS D latch and 5.3.3 Edge triggered Flip flops.

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    © All Rights Reserved
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    115 views1 page

    Assignment 5 Unit 5

    Uploaded by

    Maharshi Sanand Yadav T
    5 UNIT –V 5.1 Subsystem Design: 5.1.1 Shifters, 5.1.2 Carry skip adder, 5.1.3 carry select adder, 5.1.4 Booth Multiplier, 5.2 Memory Elements: 5.2.1 6T SRAM cell, 5.2.2 1T DRAM cell. 5.3 Sequential Logic Design: 5.3.1 Behaviour of Bi-stable elements, 5.3.2 CMOS D latch and 5.3.3 Edge triggered Flip flops.

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    UNIT-5

    SUB SYSTEM DESIGN


    UNIT-5
    1. Design a 4-bit carry select adder. Explain its operation with example
    2. Design a 4-bit carry skip adder. Explain its operation with example
    3. Write about Multipliers
    a. Array Multiplier
    b. Booth Multiplier
    4. What is Shifter? Draw and explain the operation of 4-bit barrel shifter?
    5. Draw the schematic diagram of 6T SRAM cell and explain in detail its operation? Explain its
    Read and Write cycle?
    6. Write short note on Draw 1T DRAM cell and explain the write and read operation
    7. Write short note on Draw 3T DRAM cell and explain the write and read operation
    8. Differentiate between SRAM and DRAM
    9. Implement SR-NAND based Latch using CMOS Logic and explain the working
    10. Implement SR-NOR based Latch using CMOS Logic and explain the working
    11. Implement SR-FF using NAND based Latch using CMOS Logic and explain the working
    12. Implement SR-FF using NOR based Latch using CMOS Logic and explain the working
    13. Implement D-FF using NAND based Latch using CMOS Logic and explain the working
    14. Implement D-FF using NOR based Latch using CMOS Logic and explain the working
    15. Implement JK-FF using NAND based Latch using CMOS Logic and explain the working
    16. Implement JK-FF using NOR based Latch using CMOS Logic and explain the working
    17. Implement T-FF using NAND based Latch using CMOS Logic and explain the working
    18. Implement T-FF using NOR based Latch using CMOS Logic and explain the working
    19. Explain Master Slave SR-FF Operation
    20. Explain Master Slave D-FF Operation
    21. Explain Master Slave JK-FF Operation
    22. Explain Master Slave T-FF Operation
    23. Implement D-Latch with enable using CMOS Logic + Transmission Gates

    6 t h SEM ECE-VLSI Design-OU Unit-5 T Maharshi Sanand Yadav

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