2.

Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Module 2
Architecture of 8086 Microprocessor
 Major features of 8086 processor.
 8086 CPU Architecture and the
pipelined operation.
 Programmer’s Model.
 Memory Segmentation.

Approximate Weightage – 15 Marks

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Features of 8086
 Basic features of 8086
 16-bit processor
 16 bit ALU
 16 bit registers and internal data bus
 16-bit external data bus
 Three versions based on the basis of frequency of operation
 8086 – 5 MHZ
 8086-2 – 8 MHZ
 8086-1 – 10 MHZ
 20-bit address lines to access memory
 2^20 = 1MB memory locations
 16-bit address lines to access I/O devices
 It can access 2^16 = 64K I/O locations
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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Features of 8086
 Special features of 8086
 Pipelined processor
 2 stage pipeline (Fetch stage and Execute stage)
 Improves the performance
 Operate in 2 modes
 Minimum mode – A system with only 1 processor i.e. 8086
 Maximum mode – A system with 8086 and other processor like
8087 (Math Co-processor), 8089 (IO processor) or multiple
8086 processor
 Uses memory banks
 Entire data is not stored sequentially within a single memory of
1 MB but divided into two banks of 512 KB each.
 16-bit data can be accessed in an single access even though the
memory chip can store only 8-bit at a location.
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Features of 8086
 Special features of 8086
 Uses memory segmentation
 16-bit address in an instruction can access a memory
location however 8086 has 20 address lines.

 Memory is divided into segments of capacity of 2^16 =

65536 B each called as Code, Stack, Data and Extra
Segment.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Features of 8086
 Miscellaneous features of 8086
 256 vectored interrupts

 14, 16-bit registers

 Powerful instruction set, that supports MULTIPLY and

DIVIDE operations

 8086 can perform operations on bit, byte, word or a string.

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Architecture

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Architecture
 8086 CPU is divided into two units
 The bus interfacing unit (BIU)
 The execution unit (EU)

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Architecture
8086 CPU
Tasks of BIU Tasks of EU

It sends out addresses It tells the BIU, from where to fetch the
instruction or data.
It fetches instructions from memory It decodes the fetched instructions.

It reads data from memory and ports. It It executes the decoded instructions.
also writes data to memory and ports.
BIU takes care of all the address and data EU takes care of performing operations
transfer on the buses. on the data.

It is called as external world interface of EU is called as the heart of the processor.

the processor.
It works in synchronous with machine It works in synchronous with t-state
cycles.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Execution Unit (EU)

 Arithmetic Logic Unit (ALU)
 Flag Register
 General purpose Registers
 Control Unit
 Decoder
 Pointer and Index Registers.

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Arithmetic Logic Unit (ALU)

 It is a 16-bit unit.

 Performs arithmetic and logic operations such as add,

subtract, Multiply, Divide, AND, OR, NOT, EX-OR,
increment, decrement, shift on 8-bit or 16-bit data.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Flag Register
 A flag is a flipflop.

 Part of EU.

 It indicates some condition produced by the execution of an

instruction.

 It can control certain operations of EU.

 There are 9 active flags out of 16.

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Flag Register

Overflow Carry flag

Direction Parity flag

Interrupt enable Auxiliary flag

Trap Zero

Sign
6 status flags
3 control flags

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Flag Register
 Three control flags
 The trap flag (TF)
 Puts the processor into single step mode for debugging.
 In single stepping mode microprocessor executes a
instruction and enters into single step ISR.
 User can check registers or memory contents.
 This utility is to debug the program.
 If TF = 1, the CPU automatically generates an internal
interrupt after each instruction .
 It allows a program to be inspected as it executes
instruction by instruction.

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Flag Register
 Three control flags
 The interrupt flag (IF)
 CPU will recognize external (maskable) interrupt
requests.
 Clearing IF disables these interrupts.
 It has no effect on either non-maskable external or
internally generated interrupt.
 It is used to allow or prohibit the interruption of a
program.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Flag Register
 Three control flags
 The direction flag (DF)
 Specifically used for string instructions.
 SI = Source Index, DI = Destination Index.
 It controls direction of SI and DI pointers.
 If DF = 1, the string instructions will automatically
decrement the pointers (SI & DI).
 If DF = 0, the string instructions will automatically
increment the pointers (SI & DI).

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Flag Register
 Six Conditional (status) flags
 Parity flag
 Zero flag
 Sign flag
 Auxiliary carry flag
 Carry flag
 Overflow flag

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

General Purpose Registers (GPRs)

 EU has 4 general purpose 16-bit registers.

 Used for temporary storage of 8-bit data, 16-bit data or 32-bit

data.

 8-bit registers – AH, AL, BH, BL, CH, CL, DH, DL.

 16-bit registers – AX, BX, CX, DX, SI, DI, SP, BP.

 32 Bit registers – DX:AX together can be used for 32-bit

operand.

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Special functions of general purpose registers

 Register AX
 AX - 16-bit accumulator
 AL – 8-bit accumulator
 Used for multiplication and division.
 Used for I/O access (IN and OUT)
 Used in string instructions.

 Register BX – “base” register.

 MOV [BX], AX – Indirect addressing.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Special functions of general purpose registers

 Register CX – default “count” register.
 Looping instructions (LOOP, LOOPE and LOOPNE) to
indicate number of iterations.

 Shift and Rotate instructions (RCL, RCR, ROR, ROR,

SHL, SHR and SAR) to indicate number of shift or
rotations.

 String instructions (REP, REPE and REPNE) to indicate

size of the string block.

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Special functions of general purpose registers

 Register DX – “data” register.
 Used together with AX for the word-size MUL and DIV
operations, when the operand size is greater than the register
AX i.e. Operand is 32-bit.

 It also holds the port number for the IN and OUT

instructions for 16-bit I/O ports.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Control Circuitry
 Part of EU
 Used for directing the internal operations.

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Decoder
 Decoding - Process of translation from instructions into
action.

 Decode in the EU is used for translating the instructions

fetched from the memory into series of actions.

 The EU will actually carry out these actions.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Pointers and Index Registers

 EU contain four 16-bit registers.

 These registers can be used as general purpose 16-bit registers.

 But mainly they are used to hold the 16-bit offset of data word
in one of the segments.
 Base Pointer (BP) register.
 It holds 16 bit offset relative to the stack segment (SS)
register.
 Used whenever we pass a parameter by way of stack.
 Used as an offset register in base addressing mode.

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Pointers and Index Registers

 Stack Pointer (SP) register.
 It holds 16 bit offset relative to the stack segment (SS)
register.
 Used for sequential access of stack segment
 It always points to the top of stack.
 PUSH, POP, CALL, RETURN etc.
 Source Index (SI) register.
 Used for holding the offset of a data word in the data
segment (DS).
 Destination Index (DI) register.
 Used for holding the 16 bit offset of a data word in the
extra segment (ES).
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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

BUS Interfacing Unit (BIU)

 It performs all the activities related to BUS.
 BIU has the following functions
 Instruction fetching (reading) from primary memory.
 R/W of data operand from/to primary memory
 I/O of data from/to peripheral ports.
 Address generation for memory reference.
 Instruction queuing in an instruction queue.

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BUS Interfacing Unit (BIU)

 In order to carry out its functions BIU has the following
modules
 Instruction queue.
 Segment registers.
 An Instruction pointer register (IP).
 Address generation and bus control.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

The instruction Queue

 Prefetched bytes are stored in first-in-first-out (FIFO) register
set, which is called as a “queue”.

 Significance of queue

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The instruction Queue

 As shown in the above figure, while the EU is busy in decoding the
instruction corresponding to memory location 100F0, the BIU
fetches the next six instruction bytes from locations 100F1 to 100F6
numbered as 1 to 6.

 These instruction bytes are stored in the 6 byte queue on the first in
first out (FIFO) basis.

 When EU completes the execution of the existing instruction and

becomes ready for the next instruction, it simply reads the
instruction bytes in the sequence 1, 2…. from the Queue.

 Thus the Queue will always hold the instruction bytes of the next
instructions to be executed by the EU.
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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

The instruction Queue

 Pipelining
 Process of fetching the next instruction, when the present
instruction is being executed.
 Pipelining has become possible due to the use of queue.
 BIU fills in the queue, until the entire queue is full.

 Advantage of pipelining
 Eliminates the waiting time of EU and speeds up the
processing.
 8086 BIU will not initiate a fetch unless and until there are two
empty bytes in its queue.

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The instruction Queue

 Behaviour of queue in JMP and CALL instructions.
 All the existing instruction bytes in the queue are flushed
out and queue is made empty.

 Then it is reloaded with the new instruction bytes which

correspond to the new locations mentioned in the JMP or
CALL instructions.

 The refilling of the queue then continues from the new

locations corresponding to the main program.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

The instruction Queue

 Why is the Queue only six byte long?
 Because longest instruction in 8086 is 6 byte long.
 The queue of 8088 is however 4 byte long.

 Three cases that cause EU to enter a wait state

 Instruction require access to memory location not in the queue.
 When branching instruction is executed
 When executing instructions, that are slow to execute.

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Why Segmentation is required in 8086?

 In 8086 all registers including IP are 16-bit in size.

 But to access 1 MB of external memory, 20-bit address must

be generated by 8086 on the address bus.

 It is impossible to locate or generate 20-bit address using 16-

bit register like IP.

 So the concept Segmentation is introduced in 8086.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

What is Segmentation?
 1MB of external memory is virtually or logically divided into
16 equal segments.

 Size of the 1 segment is 64KB.

 To access 64KB of memory, 16-bit address can be easily

generated by registers of 8086.

 And by using memory address generation technique, 20-bit

physical address can be easily generated using logical address
(segment base:offset).

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Segment Registers (Segmentation in 8086)

 BIU contains four special purpose registers called as segment
registers.
 Code segment (CS) register.
 Stack segment (SS) register.
 Extra segment (ES) register.
 Data segment (DS) register.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Memory Address Generation

The BIU has a dedicated adder for determining

physical memory addresses
Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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Segment Registers (Segmentation in 8086)

Segment Starting address is
segment register value MEMORY Address
shifted 4 place to the left. 000000H

CODE

64K Data
Segment
STACK

DATA

EXTRA  CS:0
64K Code
Segment
Segment
Registers

0FFFFFH

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Segment Registers (Segmentation in 8086)

Memory Segments
Segment 000000H
Registers
20000H
DS: 2000H DATA
2FFFFH

SS: 5000H STACK 50000H

5FFFFH
ES: 7000H 70000H
EXTRA
7FFFFH
CS: 3000H
CODE 30000H
3FFFFH
Segments are < or = 64K and can overlap.
Note that the Code segment is < 64K since 7FFFFH is the
highest address.
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The Code Segment

000000H

4000H
CS: 0400H
4056H
IP 0056H CS:IP = 400:56
Left-shift 4 Logical Address
bits Memory
Segment Register 0400 0
+ 0056
Offset 0FFFFFH

04056H
Physical or
Absolute Address
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The physical address is also called the absolute address

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

The Stack Segment

000000
H
0A000H
SS: 0A00
0A100H
SP 0100 SS:SP

Memory
0A00 0
Segment Register
+ 010 0
Offset
0FFFFFH
0A100H
Physical Address
The offset is given by the SP register.
The stack is always referenced with respect to the stack segment register.
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POP - post-increment the SP

The Data Segment

000000H

05C00H
DS: 05C0
05C50H
EA 0050 DS:EA

Memory
Segment Register 05C0 0
+ 0050
Offset
0FFFFFH
05C50H
Physical Address
Data is usually fetched with respect to the DS register.
The effective address (EA) is the offset.
The EA depends on the addressing mode.
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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Segment Registers associated with offset

Segment Registers Offset

CS IP

DS SI

ES DI

SS SP or BP

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Advantages of Segmentation
 Provides powerful memory management mechanism.

 It allows two processes to easily share data

 It allows you to extend the address ability of a processor.

 It makes it possible to separate the memory areas from stack,

code and data.

 It is possible to increase the memory size of code, data or

stack segments beyond 64 kbytes by allotting more than one
segment for each area.
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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

Rules for Segmentation

 In non-overlapping, there can be 16 segment each of 64KB.

 Segments can overlap each other.

 A segment can begin at any location i.e. multiple of 10.

 At any given time 4 segments and hence a maximum of 256KB can be

accessed.

 Addresses generated crosses 1 MB limit, it accesses the location at the top

00000H.(e.g. CS = FFFF & IP = 0010, physical address = 100000 but
location accessed will be 00000).

 In an instruction only the offset address is mentioned, the segment register is

fixed for each of the pointer register.
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Instruction Pointer
 Special purpose register in the BIU.

 It holds the 16 bit address or offset of the next code byte

within the code segment.

 It always holds 16-bit offset associated with code segment to

generate physical address.

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

8086 Programmer’s Model

ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS

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M&P University Questions

 May-2015
1) Explain what is the need and advantages of memory segmentation in 8086 microprocessor.
(05 Marks)

 Dec-2016
2) Discuss the functions of general purpose registers of 8086. Explain the function of each
register and instruction support for these functions. (10 Marks)

 May-2017
3) Explain memory segmentation of 8086. (05 Marks)

 Dec-2017
4) Explain advantages of memory segmentation. (05 Marks)

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2. Architecture of 8086 Microprocessor (Module2) TE EXTC, SEM-V

M&P University Questions

 May-2018
5) Explain memory segmentation of 8086 and its advantages. (05 Marks)
6) Discuss the functions of general purpose registers of 8086. Explain the function of each
register and instruction support for these functions. (10 Marks)

 Dec-2018
7) Draw and Explain the Flag register of 8086 microprocessor. (05 Marks)

 May-2019
8) What is memory segmentation of 8086? Explain in brief. (05 Marks)
9) If (CS) = 5000H, (DS) = 6000H, (SS) = 7000H and (ES) = 8000, draw the memory map
8086 cpu with starting and end physical address of each segment. (05 Marks)

 Dec-2019
10) Explain the instruction pipelining features of 8086. Give its advantages and disadvantages.
(05 Marks)

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