Received August 30, 2018, accepted October 2, 2018, date of publication October 12, 2018, date of current version

November 9, 2018.
Digital Object Identifier 10.1109/ACCESS.2018.2875764

A Low-Power Wideband dB-Linear Variable Gain

Amplifier With DC-Offset Cancellation
for 60-GHz Receiver
LONG HE 1 , LIANMING LI 1,2 , (Member, IEEE), XU WU1 ,
AND ZHIGONG WANG 1 , (Senior Member, IEEE)
1 School of Information Science and Engineering, Southeast University, Nanjing, 210096, China
2 National Mobile Communication Research Laboratory, Southeast University, Nanjing, 210096, China
Corresponding authors: Lianming Li (lianming.li@seu.edu.cn) and Zhigong Wang (zgwang@seu.edu.cn)
This work was supported in part by the National High-Tech Project (863 Project) of China under Grant 2011AA010201 and Grant
2011AA010202, in part by the National Nature Science Foundation of China under Grant 61306030, and Grant 61674037, and in part by
the National Key R&D Program of China under Grant 2016YFC0800400.

ABSTRACT This paper presents a two-channel (I+Q) variable gain amplifier (VGA) for low power
60-GHz wireless receiver. The VGA consists of four-stage gain cells, an efficient DC-offset cancelling
circuit and an output buffer for test purposes. To achieve wide bandwidth and low power consumption, a
modified Cherry—Hooper amplifier gain cell is used. With a tunable transistor and its parasitic capacitance,
a dB-linear characteristic and a flat gain response are achieved without any additional exponential circuit.
The DC-offset is cancelled effectively with two proposed feedback loops. The measurement results show
that the VGA achieves a gain range of 6 to 44 dB, an OP1dB of 1 dBm, and a 3-dB bandwidth of over
1 GHz with an excellent flat gain response. Fabricated in a 65-nm CMOS technology, the two-channel
VGA core occupies a silicon area of only 0.055 mm2 and consumes only 10 mA from a 1.2 V power
supply.

INDEX TERMS Variable gain amplifier (VGA), low power, CMOS, broadband, gain flatness, dB-linear,
DC-offset cancellation.

I. INTRODUCTION
With the wide bandwidth and license-free characteristics, the
60-GHz wireless communication has been widely considered
as a promising solution for future high data-rate communica-
tion applications. As shown in Fig. 1, as an essential front-end
building block, the VGA is used to maximize the receiver
dynamic range and maintain sufficient signal-to-noise ratio
(SNR) for baseband circuits [1]–[6].
For 60-GHz applications, with the target of wide band-
FIGURE 1. Block diagram of the 60-GHz receiver.
width, low power, wide gain-tuning range and low DC-offset,
the VGA faces several design challenges. For the IEEE
802.11ad standard, the VGA’s 3-dB bandwidth should be In this paper, a two-channel (I+Q) variable gain amplifier
larger than 1 GHz. Moreover, to increase the receiver dynamic (VGA) is presented. To achieve wide bandwidth and low
range and SNR, the VGA gain range should be larger power consumption, a modified Cherry-Hooper amplifier
than 35 dB and its output swing larger than 500 mVpp . gain cell is employed. The dB-linear characteristic and flat
To avoid output swing reduction, the DC-offset voltage must gain response are achieved with a tunable transistor and its
be cancelled efficiently. In addition, the VGA should have parasitic capacitance. The DC-offset is cancelled effectively
a dB-linear gain control characteristic and flat gain response, by two properly connected negative feedback loops.
so that 60 GHz system requirements on constant settling time This paper is organized as follows. Section II presents
and flat in-band group delay can be ensured [7]. the design details of the VGA circuits. Section III describes
2169-3536
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L. He et al.: Low-Power Wideband dB-Linear VGA With DC-Offset Cancellation for 60-GHz Receiver

the measurement results and performance comparison. The

conclusions are drawn in Section IV.

II. VGA TOPLOGY AND DESIGN

As shown in Fig. 2, the proposed VGA consists of a high pass
filter (HPF), four-stage gain cells, an output buffer and a DC-
offset cancelling circuit. The resistor Rin in front of the HPF
provides a good broadband input match, and the amplifier
gain can be measured precisely. The HPF is used to elimi-
nate the input DC-offset generated by the receiver frontend.
Considering the system bit error rate (BER) requirement, its
corner frequency is set to be 2 MHz, which is much lower
than one hundredth of the bandwidth. For good linearity
performance, the size ratio of four gain cells is 2:1:1:2. The
DC-offset from VGA itself is removed by two DC-offset
cancelling feedback loops to ensure that the circuit is not
saturated.

FIGURE 2. Block diagram of the VGA circuit for the 60-GHz receiver.
A. WIDEBAND VGA GAIN CELL WITH A FLAT
GAIN RESPONSE
Assuming the 3-dB bandwidth of each gain cell is BWC ,
the total bandwidth BWtot of a four-stage VGA can be
calculated as follows:
p
m
BWtot = BWc 21/n − 1 (1)
where m equals to 2 and 4 for the first-order and second-
order gain cells, respectively. n is the number of identical gain
cell stage. To achieve a BWtot of over 1 GHz with four gain
cells (n = 4), the cell bandwidth BWC must exceed 2.3 and
1.5 GHz when m equals to 2 and 4, respectively [8].
As shown in Fig. 3 (a), to meet above bandwidth
requirement, the VGA gain cell is realized using a modified
Cherry-Hooper amplifier, which not only reduces the Miller
capacitance, but also increases the stage bandwidth and pro-
duces a second-order stage response [9]–[11]. To achieve
low supply operation, R1 and R2 are employed to allow the
current of M1 and M2 to flow through them rather than R3 and
R4 . Transistors M5 -M8 are added to bypass the current flow
through R1 -R4 , thus increasing the equivalent impedances
at nodes A, B, C and D with the same voltage and cur-
rent. In this way, the amplifier gain and bandwidth perfor-
mance are improved. Moreover, with transistors M5 -M8 and
resistors R1 -R4 , the amplifier DC operating points at nodes A
and B are well defined, avoiding the complex common-mode
FIGURE 3. The structure of the VGA gain cell. (a) schematic, (b) equivalent
small-signal circuit of half gain cell.
feedback circuits. In addition, the voltages of nodes A and B
are raised, making it easy to employ an active resistor Rf .
The gain tuning resistor Rf is achieved with a tunable PMOS
transistor Mf , which is controlled by a tuning voltage Vc .
The modified Cherry-Hooper amplifier gain cell can be
viewed as the cascade of the transconductance (Gm ) stage and
transimpedance (TI) stage. From the equivalent small-signal
half circuit shown in Fig. 3(b), the DC gain of the Gm and
TI stage are defined by
RA (RB + Rf )
Av0,Gm = gm1 · (2)
RA + RB + Rf + gm3 · RA · RB
and
gm3 · Rf − 1
Av0,TI = (3)
1 + Rf /RB
where gm1 and gm3 are the transconductance of transistors
M1 and M3 , respectively. RA and RB are the equivalent
resistances at nodes A and B, respectively. The equivalent
impedances of nodes A and B can be calculated in (4)
and (5), as shown at the bottom of the next page, where
CA and CB are the parasitic capacitances at nodes A and B,
respectively. Note Eq. (4) and Eq. (5), are valid if
RB ||(1/sCB ) >> 1, RA ||(1/sCA ) >> 1 and (RB ||(1/sCB )) ×
(RA ||(1/sCA )) >> Rf ||1/sCf . Assuming RB >> Rf and

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 L. He et al.: Low-Power Wideband dB-Linear VGA With DC-Offset Cancellation for 60-GHz Receiver

RA >> Rf , the poles at nodes A and B will be gm3 /CA given as follows:
and gm3 /CB , respectively. In this design, the 1/gm3 is set 1 sCf Rf
(1 − gm3 ·Rf ) 1− gm3 Rf −1
be 10 times smaller than RA and RB , and the frequency of Av (s) = gm1 Rf · · (6)
RA +RB +Rf as2 + bs + 1
these two poles can be higher. In this way, a wide bandwidth 1+ gm3 ·RA ·RB
can be achieved. These two equations also indicate that the
where a and b, as shown at the bottom of the next page.
equivalent resistances of nodes A and B are not constant
Clearly, with the feedback capacitor Cf , a positive zero
but positive correlation functions of Rf , so the bandwidth
(gm3 Rf -1)/(Rf Cf ) is introduced, which can be used to improve
would be increased with the decrease of the gain. In order
the amplifier gain flatness and stability. Fig. 5 (a) and (b)
to achieve a relatively stable bandwidth in the whole gain
show the frequency response of the Gm and combination
variation range, transistors M5 -M8 are added to increase the
of Gm and TI stage, with and without Cf . Clearly, with an
value of RA and RB and minimize the impact of variable
optimized Cf , a maximally flat frequency response with-
resistor Rf on the bandwidth.
out peaking is achieved. Fig. 6 shows the simulated pulse
As the input of a negative feedback amplifier [12], node
response at the amplifier output with and without Cf . With the
A has an inductive impedance zA , which leads to a peak
feedback capacitorCf , the ringing in the output is suppressed,
in the gain frequency response of the Gm stage. As shown
and the amplifier stability is ensured. For the implementation,
in Fig. 4, with appropriate design efforts, this peak can be
the Cf is realized by proper sizing of transistor Mf length and
used to compensate the TI stage gain roll off and increase
width.
the total bandwidth of the gain cell. In order to achieve
a trade-off among gain, bandwidth and linearity, the main
circuit equivalent components are optimized. Both gm1 and
gm3 equal to 2.6 mS, and Rf equals to 3 k. With those values,
the gain of Gm and TI stage are 3 and 11 dB, respectively.

FIGURE 5. Frequency response with and without Cf . (a) Gm stage,

(b) combination of the Gm and TI stage.

B. DB-LINEAR REALIZATION
From Eq. (2) and Eq. (3), the DC gain of the Cherry-Hooper
amplifier gain cell Av0 is given by:
1
(1 − gm3 ·Rf )
Av0 = Av0,Gm · Av0,TI = gm1 Rf · RA +RB +Rf
. (7)
1+ gm3 ·RA ·RB

FIGURE 4. Gain frequency response of the Gm , TI stage and combination
of the Gm and TI stage.
However, the inductive impedance will typically introduce
a gain ripple, worsening the time domain performance. In this
design, a capacitive-compensated bandwidth enhancement
technology is used to suppress the gain ripple [13]. As shown
in Fig. 3(b), with a parallel capacitor Cf and Rf , the transfer
function of the Cherry-Hooper amplifier gain cell Av (s) is
Assuming gm3 Rf >> 1, this expression can be simpli-
fied as Av0 ≈ gm1 Rf Av0 ≈gm1 Rf . Therefore, the dB-linear
characteristic can be achieved if the tuning resistor Rf has an
exponential behavior. As mentioned above, the Rf is realized
with a PMOS transistor Mf operating in the linear region
(shown in Fig. 3(a)), and its value is given by:
1 1
Rf = · (8)
W V
µCox /L (Vs − |VTH |) 1 − /(Vs − |VTH |)
c

(RA ||1/sCA ) · (RB ||1/sCB + Rf ||1/sCf )

zA =
RA ||1/sCA + RB ||1/sCB + Rf ||1/sCf + gm3 (RA ||1/sCA ) · (RB ||1/sCB )
 
1 Rf ||1/sCf
≈ 1+ (4)
gm3 RB ||1/sCB
(RB ||1/sCB ) · (RA ||1/sCA + Rf ||1/sCf )
zB =
RA ||1/sCA + RB ||1/sCB + Rf ||1/sCf + gm3 (RA ||1/sCA ) · (RB ||1/sCB )
 
1 Rf ||1/sCf
≈ 1+ (5)
gm3 RA ||1/sCA

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L. He et al.: Low-Power Wideband dB-Linear VGA With DC-Offset Cancellation for 60-GHz Receiver

FIGURE 6. Output pulse response of the gain cell, (a) without Cf ,

(b) with Cf .

where Vc and Vs are the voltages of gate and source terminals,

respectively. FIGURE 7. Simulated PMOS resistor Rf vs. gate control voltage Vc .
By Taylor expansion, when | x|<<1, exp(x) ≈ 1/(1 − x),
and Eq. (8) can be expressed as follows:
1 Vc
Rf = · exp( ). (9)
W
µCox /L (Vs − |VTH |) V s − |VTH |
On a decibel scale, Eq. (9) can be expressed as:
Rf (dB) = K1 + K2 · Vc (10)
where
1
K1 = 20 · log10
W
µCox /L (Vs − |VTH |)
20 · log10 e
K2 = .
Vs − |VTH |
FIGURE 8. Half circuit of DC-offset cancellation feedback loop connection.
Clearly, K1 and K2 are constant in this design, and Rf is
linear in decibel with respect to gate voltage Vc , as shown
in Fig. 7. Same as before, by optimizing the transistor length voltages are from VGA1 and VGA3, the feedback loops are
and width, a dB-linear range of 8.7 dB is achieved with closed at the input of these two stages.
a control voltage Vc increasing from 0 to 250 mV. With Different from [14], in this design, the DC feedback loop
four gain cells, a total gain tuning range of 34.8 dB can be is connected to the Gm stage output instead of the TIA stage
achieved. As to be shown shortly in Section III, such value output. Simulations and calculations prove that the DC-offset
fits very well with the measured gain range. is cancelled more effectively with the same power consump-
tion. The half circuit of DC-offset feedback loop 1 can be
C. DC-OFFSET CANCELLATION simplified as shown in Fig. 8. Clearly, the Gm stage output
node A of VGA1 is connected to the feedback loop 1, and the
Typically, caused by process variation and asymmetry of
DC-offset output voltage Vo,os (A) can be calculated as :
circuit design, there are DC-offset voltage and I/Q gain mis-
match in the VGA. The DC-offset voltage will saturate the gm1 gm1
following VGA gain cells if its gain is large, worsening Vo,os (A) = · Vi,os ≈ · Vi,os (11)
1
gmf1 + /AV2,3,4 · rA gmf1
linearity and I/Q mismatch performance. Considering VGA
requirements on the bandwidth, the chip area and the power
consumption, as shown in Fig. 2, two DC-offset feedback where Vi,os is the input offset voltage of the first gain cell
loops with the same structure and feedback mechanism are VGA1, Av2,3,4 is the cascading gain of VGA2, VGA3, VGA4,
introduced in this design. The offset voltage is sensed at rA is the equivalent small-signal resistance of node A.
the VGA output by a low pass filter (LPF), sent back and If the feedback loop 1 is connected to node B of VGA1,
compensated at the VGA input. As the dominant DC-offset the DC-offset output voltage Vo,os (B) can be calculated as

RA RB Rf (CA Cf + CB Cf + CA CB )
a=
RA + RB + Rf + gm3 RA RB
gm3 RA RB Rf Cf + Rf RB (CB + Cf ) + Rf RA (CA + Cf ) + RA RB (CA + CB )
b=
RA + RB + Rf + gm3 RA RB

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 L. He et al.: Low-Power Wideband dB-Linear VGA With DC-Offset Cancellation for 60-GHz Receiver

follows:
AV1 · AV2,3,4
Vo,os (B) = · Vi,os
1 + gmf1 · rB · AV2,3,4
gm1
≈ · gm3 · Rf · Vi,os (12)
gmf1
where AV1 is the gain of VGA1, gm3 is the transconductance
of M3 , rB is the equivalent small-signal resistance of node B.
From Eqs. (11) and (12), it can be clearly seen that with the
same gm1 and gmf , Vo,os (A) is much smaller than Vo,os (B) by
gm3 × Rf times. The same principles apply to DC-offset feed-
back loop 2 and the output DC-offset voltage from VGA3 can
be also minimized effectively. Assuming the input offset
voltage of each stage equals to +10 mV, Fig. 9 shows the
simulated output DC-offset with different feedback nodes.
Clearly, when the feedback circuit is connected to node A,
the output DC-offset is much smaller than the case when
node B is connected.
FIGURE 10. The chip micrograph of two-channel VGAs.

FIGURE 9. Output DC-offset voltage vs. gain for different feedback nodes.

III. MEASUREMENT RESULTS FIGURE 11. The simulated and measured gain frequency response with
Fig. 10 shows the chip micrograph of the two channel (I+Q) different control voltages.

VGA chip. Fabricated in a 65-nm CMOS process, the VGA

core area is only 0.055 mm2 , and it consumes only 10mA
from a 1.2 V power supply.
The VGA measurements were performed with Agilent
N5247A Network Analyzer and a digital phosphor oscil-
loscope 70604C. Fig. 11 shows the simulated and mea-
sured results of frequency response of VGA. The amplifier
bandwidth is larger than 1 GHz and in-band flatness is excel-
lent. As shown in Fig. 12 (a), in the whole gain tuning range
the VGA bandwidth only varies from 1 to 1.65 GHz. Clearly,
the above measured results agree very well with the simulated
results. In particular, due to underestimated parasitic parame- FIGURE 12. (a) the simulated and measured bandwidth vs. gain variation,
ters, the measured bandwidth is little lower than the simulated (b) simulated and measured gain vs. control voltage Vc .
results. Characterized at 500 MHz, Fig. 12 (b) shows VGA
simulated and measured gain tuning performance. With a
control voltage Vc from 0 to 264 mV, the measured gain can be The amplifier simulated and measured input and output
tuned from 6 to 44 dB, and it has a dB-linear characteristic. 1 dB compression point (IP1dB and OP1dB) versus gain
In particular, with a control voltage Vc from 0 to 264 mV, performance is shown in Fig. 13. Same as other results,
the simulated gain range is from 5.5 to 43 dB, which is the measured results are in good agreement with the simu-
consistent with above calculation results. lated results. With the minimum and maximum gain settings,

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L. He et al.: Low-Power Wideband dB-Linear VGA With DC-Offset Cancellation for 60-GHz Receiver
FIGURE 13. Measured and simulated P1dB vs. gain.
the VGA OP1dB is −4 and 1 dBm, respectively. This ensures
that the output signal amplitude is larger than 500 mVpp .
Fig. 14 shows the transient response of the output when a
−30 dBm 500 MHz sinusoid signal is applied. Clearly, due
to power-efficient DC-offset cancelling circuits and excel-
lent layout matching, well balanced I/Q transient response is
achieved.
FIGURE 14. Transient response of output with −30 dBm 500 MHz input.
Table 1 summarizes the performances comparison of the
VGA with other reported VGA circuits. Here, for fair compar-
ison, single-channel VGA performance is used. The proposed
design achieves a 3-dB bandwidth of over 1 GHz and 38 dB
gain tuning range with an accurate dB-linear characteris-
tic. Typically, to make a performance comparison further,
a widely used VGA figure of merit (FoM) can be used,
as shown below:
BW(GHz) × Gain Range(dB)
FoM = . (13)
Power(mW) × Core Area(mm2 )
Taking into account noise performance, based on low noise
amplifier International technology roadmap for semiconduc-
tors (ITRS) FoM [21], a modified FoM1 including gain range
VOLUME 6, 2018
TABLE 1. Performance summary and comparison.
can be used, as shown below:
BW [GHz] · Gain[lin] · Gain range[dB]
FoM1 = . (14)
PDC (mW) · (NF[lin] -1)
Using 40 nm CMOS process, [16] realized 1.1 GHz band-
width and OP1dB of 1.4 dBm and its power consumption
is about 15 ∼ 21 mW. With 180 nm CMOS process, [18]
and [19] realized very large gain range and relatively lower
bandwidth. [15], [17], [20] and this work are all realized
with 65 nm CMOS process. In [20], a 4 GHz single-channel
VGA with gain tuning range of 60 dB is realized, achieving
an output P1dB of −11 dBm. Regarding typical 60 GHz
applications, [15] and [17] realized a bandwidth of about
1 GHz and gain tuning range of about 30 dB. In this
work, due to the modified wi- deband Cheery-Hooper ampli-
fier, capacitive-compensated bandwidth enhancement and
power-efficient DC-offset cancellation techniques, this VGA
exhibits very good gain, gain tuning range, bandwidth and
linearity performance. To be specific, the proposed design
achieves a 3-dB bandwidth of over 1 GHz and 38 dB gain tun-
ing range with an accurate dB-linear characteristic. In addi-
tion, its OP1dB is from −3 to 1 dBm across the tuning range.
Clearly, because of above mentioned proposed techniques,
this VGA achieved a good FoM result.
IV. CONCLUSION
This paper presents a wideband VGA for 60 GHz wireless
receiver. The VGA achieves excellent dB-linear and in-band
flatness performance with a tunable transistor and capacitive-
compensated bandwidth enhancement techniques. The pro-
posed technique for DC-offset cancellation is proven to be
much more efficient with the same power consumption. The
VGA achieves a gain range from 6 to 44 dB with dB-linear
characteristic, a 3-dB bandwidth of over 1 GHz, an OP1dB of
from −4 to 1 dBm. The VGA core occupies only 0.055 mm2
silicon area and consumes only 10 mA from a 1.2 V power
supply.
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 L. He et al.: Low-Power Wideband dB-Linear VGA With DC-Offset Cancellation for 60-GHz Receiver
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61832
LONG HE received the B.S. degree in commu-
nication engineering from Zhengzhou University,
Zhengzhou, in 2011, and the M.S. degree in inte-
grated circuit design from Southeast University,
Nanjing, in 2014, where he is currently pursuing
the Ph.D. degree. In 2012, he joined the Integrated
Communication Circuits Research Group, South-
east University. His research interests focus on
baseband circuits and system design for wireless
communication.
LIANMING LI (S’06–M’11) was born in Runan,
Henan, China, in 1978. He received the B.S.
degree in physics, and the M.S. degree in electri-
cal engineering from Southeast University, Nan-
jing, China, in 2001 and 2004, respectively, and
the Ph.D. degree from the Katholieke Universiteit
Leuven, Leuven, Belgium, in 2011.
From 2006 to 2011, he was a Research Assis-
tant with ESAT-MICAS, Katholieke Universiteit
Leuven, where he was involved in the mmWave
CMOS design. Since 2011, he has been with the School of Information
Science and Engineering, Southeast University, as an Associate Professor.
His current research interests focus on mmWave circuits and system design,
antenna and packaging design, and the frequency generation circuits design.
XU WU was born in Hebei, China, in 1983.
She received the degree from the Huazhong Uni-
versity of Science and Technology in 2001, the
M.S. degree in industrial engineering in electron-
ics (Industrieel Ingenieur Electronica) from the
Groep T, Belgium, in 2005, and the Ph.D. degree in
electronics from the Katholieke Universiteit Leu-
ven (KU Leuven), Heverlee, Belgium, in 2012.
She was a Research Assistant with the Laboratory
ESAT, MICAS Group, KU Leuven.
From 2011 to 2017, she was with CMOSIS, Belgium, as a Senior Design
Engineer and a Technique Lead. Her main target was to develop advanced
high-speed CMOS image sensors. Since 2017, she has been a Faculty Mem-
ber with Southeast University, China. Her current research interests are in
RF transceivers, and high-performance and high-frequency analog integrated
circuits for telecommunication systems.
ZHIGONG WANG (M’91–SM’93) was born in
Henan, China. He received the M.-Eng. degree in
radio engineering from the Nanjing Institute of
Technology (now Southeast University), Nanjing,
China, in 1981, and the Dr.-Ing. degree in elec-
tronic engineering from Ruhr University Bochum,
Germany, in 1990. From 1977 to 1981, he was
with the Nanjing Institute of Technology, where he
was involved in radio communication techniques
and computer-aided circuit designs. From 1982 to
1984, he was a Lecturer on semiconductor circuit techniques with Tongji
University, Shanghai. From 1985 to 1990, he was with Ruhr University
Bochum, where was involved in high-speed silicon bipolar circuit designs.
From 1990 to 1997, he was with the Fraunhofer Institute of Applied Solid
State Physics, Freiburg, Germany, where he was involved in high-speed
GaAs ICs. Since 1997, he has been serving as a full-time Professor with
Southeast University, Nanjing. He has authored or co-authored over 20 books
and over 500 SCI/EI/ISTP-indexed papers and an inventor of over 80 patents
in China, Germany, Europe, USA, and Japan. Recently, he was involved in IC
design for optic-fiber transmission systems, for RF wireless, microwave, and
millimeter-wave applications and in microelectronic systems for biomedical
applications. He is a fellow of the Chinese Institute of Electronics.
VOLUME 6, 2018