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Sony Mbx-165 Ms90 - Power Sequence
Sony Mbx-165 Ms90 - Power Sequence
D 20 18 CPU_PWRGD D
CPU
CPU_RST#
19 PLT_RST#
PWROK
ICH8 15-1 CLK_PWRGD
Crestline VRMPWRGD
SB CK_PWRGD
NB
SLP_S3#
SLP_S4#
SLP_S5#
PM_RSMRST#
PWROK
PWRBTN#
VRMPWRGD
8 7 6 5 4
C
17 C
IMVP_PWRGD 99ms
PWRSW# 3
16 IMVP_OK EC SW
14 IMVP_VR_ON 99ms
15
EC_CLK_EN#IMVP6 13-2 13-1 13 12 11 10 9 2 1
RUN_PWRGD
SUS_ON
ALW_PWRGD 3/5VALW
ALW_ON
RUN_ON2
RUN_ON1
RUN_ON
SUS_PWRGD_10MS
DDR2_PWRGD
11/17:
Check if it's ok to use IMVP_OK to replace
EC_CLK_EN#, it can save one inverter
1_5VRUN
1_25VRUN
1_05VRUN
2_5VRUN
3/5VRUN
1_8VRUN
NV_VDD
PEX_VDD
0_9VSUS
1_8VSUS
1_25VSUS
1_05VSUS
3/5VSUS
CK505
B B
CK_PWRGD/PD#
TI 8402's GRST#
A A
5 4 3 2 1
5 4 3 2 1
PLT_RST# NB to CPU
IMVP_OK IMVP6 to EC
VHCORE
T08(Min=5ms )
C RUN_ON2 EC output C
T09(Min=15ms )
+1_8VRUN
PEX_VDD/NV_VDD
T11(Min=10ms )
RUN_ON EC output
RUN_PWRGD Input EC
T12(Min=10ms )
SUS_PWRGD_10MS EC output
T13(Min=10ms )
SUS_ON EC output
B B
DDR2_PWRGD Input EC
+3VSUS/ +5VSUS/+1_8VSUS/+0.9VSUS
(S5 to G3)
DC_IN
DCBATOUT
ALW_PWRGD
PM_RSMRST#
+5VALW/ +3VALW
T14: RSMRST# falling edge must transition to 0.8V or less before VccSus3_3 drops to 2.1V (Please refer 21762 T312 page 317)
ALW_ON
+ECVCC
PWRSW#
A A
+ECRST#
T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14
1 - 2 1 - 2 1 - 2 Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. *1
RTCCLK RTCCLK RTCCLK 0ms 15ms 0ms 20ns 5ms 15ms 10ms 10ms 10ms 10ms
*1 RSMRST# falling edge must transition to 0.8V or less before VccSus3_3 drops to 2.1V
5 4 3 2 1
5 4 3 2 1
DC_IN+
MS90 Power On Sequence Timing
DCBATOUT
Version : 0.5
+ECVCC
ECRST# T00
ALW_Power ON when AC in or Batt in only
NOTE : ( EC KB3910 Min. response time is 1ms)
ALW_ON T01 (EC output)
D D
+1_8VRUN
T20 T00 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10
IMVP_PWRGD (From EC to NB's PWROK & SB's PWROK) R/C delay 1 - 2
A T19 (47K/ Min. Min. Min. Min. Max. RTCCLK Min. Min. Min. A
5 ms 10 ms 40ms 50ms 110ms (Checking) 25 ms 1ms 5ms 99ms
0.1uF)
STPCLK# T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
T11
Max. Min. Min Min TBD Min : 5.5ms Max Min Min : 99ms Min :1s
BCLK, SRCCLK, PCICLK T17 50ns 150ms 700ms 5ms Max : 8.1ms 1.8ms 1ms
Running
5 4 3 2 1
5 4 3 2 1
D Change List D
[V0.2]
1. STPCLK#, CPUSLP#, STP_CPU#/PCI# --> STPCLK#
2. Correct T11 from "IMVP_OK to STPCLK#" --> "IMVP_PWRGD to STPCLK#" (Refer ICH8M EDS T215)
3. Correct down side table T09 from 10ms to 5ms.
4. Correct T18 from "IMVP_OK to PLT_RST#" --> "IMVP_PWRGD to PLT_RST#" (Refer ICH8M ESD)
5. Correct H_CPURST to H_CPURST#
6. Add ICH8M's CK_PWRGD to enable CK505's PWRGD
7. Update CLK_EN# to EC_CLK_EN#
[V0.3]
C C
1. Correct: PWRSW# is driven by EC, not ICH8M
2. Add note: Check if it's ok to use IMVP_OK to replace EC_CLK_EN#, it can save one inverter
[V0.4]
1. Add power off sequence
[V0.5]
1. Correct T12 from min:400ms to 150ms
This modify already phase in MS90-DVT stage.
B B
A A
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