module fullAdder(input a,b,cin,

output reg sum,cout);

always @ (a or b or cin) begin
{cout,sum} <= a+b+cin;
end
endmodule

module add4bit(input [3:0]a,

input [3:0]b,
input cin,
output [3:0]s,aled,bled,cinled,
output cout);
wire [2:0] c;
fullAdder fa1(a[0],b[0],cin,s[0],c[0]);
fullAdder fa2(a[1],b[1],c[0],s[1],c[1]);
fullAdder fa3(a[2],b[2],c[1],s[2],c[2]);
fullAdder fa4(a[3],b[3],c[2],s[3],cout);
assign aled = a;
assign bled = b;
assign cled = c;
endmodule

module testBench();
reg [3:0]a;
reg [3:0]b;
reg cin;
wire [3:0] sum;
wire cout;
add4bit add(a,b,cin,sum,cout);
initial begin
a<=4'b1010;
b<=4'b0001;
cin<=0;
#10;
a<=4'b1111;
b<=4'b1111;
cin<=0;
#10;
end
endmodule