MEENAKSHI RAMASWAMY ENGINEERING COLLEGE, b Explain about hazards and its types in detail C203.

THATHANUR – 621804. 13 K2
4
CYCLE TEST-II
14 a Design an asynchronous sequential circuit with two
Department of Electronics and Communication Engineering inputs X and Y with one output Z. Whenever Y is 1, C203.
EC3352– DIGITAL SYSTEM DESIGN input Y=0, the output does not change for any change 13
4
K6
in X.
Year & Semester: II & III Date: 09.11.2022 (Or)
Duration: 3.00 Hours Total Marks: 100 b Explain pulse mode and fundamental mode circuit. 13 C203. K2
write the steps involved in the design of pulse mode 4
Answer ALL Questions Part A: 10 X 2 = 20 Marks
circuit.
What is sequential circuit and what are the classification of 15 a Derive the flow table for the given circuit.
01 2 C203.3 K1
sequential circuit?
C203.3
02 Difference between Mealy model and Moore model. 2 K1
C203.3
03 Why state reduction is necessary? 2 K1 C203.
13 K6
04 Write the characteristic equation of JK & SR flip-flop. 2 C203.3 K1 4
05 Construct the state diagram of Mod-10 counter. 2 C203.3 K6
06 How does the operation of an asynchronous input differ from 2 C203.4
K1
that of a synchronous input?
07 What is fundamental mode asynchronous sequential circuit? 2 C203.4 K1 (Or)
08 What is a cycle? 2 C203.4 K1 b Derive the transition table and output map for the
09 What are hazards and what are the types of hazards? 2 C203.4 K1 given circuit.

10 What are races? 2 C203.4 K1 C203.

13 K6
4

Part B: 5 X 13 = 65 Marks
11 a (i)How will you convert D flip-flop into JK flip-flop? C203.
10 K1
3
(ii)Explain level and edge triggering. 5 C203. K2
3
(Or) Part C: 1 X 15 = 15 Marks
b (i)Realize SR flip-flop using JK flip-flop. C203. 16 a Design a sequential circuit using JK flip-flop for the state C203.3 K6
10 K3 diagram shown below.
3
(ii)Difference between latch and flip-flop. 3 C203. K1
12 a Design a 3-bit binary counter using T flip-flop that has 3
C203. 15
a repeated sequence of six states 000-001-010-100- 13 K6
3
101-110.give the state table, state diagram & logic
diagram. (Or)
b Describe the operation of universal shift register. 13 C203. K2
3
13 a Design a synchronous counter with states 0,1,2,3,0,1, C203.
…. using JK flip-flop. 13 K6
3 (Or)
(Or)
 b Design an asynchronous sequential circuit that has 15 C203.4 K6
two inputs X2 and X1 and one output Z. when X1=0,
the output Z is 0. The first change in X2 will cause
output Z to be 1. The output Z will remain 1 until X1
returns to 0.

Prepared By Approved By

(S.G. PRAVEENA, AP/ECE)