Designing Silicon Carbide (SiC) based DC Fast Charging System:

Key Challenges, Design Considerations, and Building Validation

Session 3

Gate Driver & Thermal Design & Auxiliary Supply

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Content

• Past session :
− Session 1(June 1): Project and 6-Pack Boost Active Front End AC-DC analysis
− Session 2 (June 8): Dual Active Bridge DC-DC analysis and Control Architecture
• Session 3 :
− Thermal approach and Mechanical design,
− Gate driver schematic and layout,
− Auxiliary supply.
• Next to come :
− Session 4 (June 29): Measurement Results

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Thermal Design and Mechanical Assembly

How to Extract Losses form SiC Modules

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 Modules’ Losses for 6-Pack Boost and the Dual Active Bridge
• 6-Pack PIMs • DAB Primary PIMs • DAB Secondary PIMs
Ultrafast charger PFC: overall PIMs losses Dual Active Bridge: Power loss - primary PIMs Dual Active Bridge: Power loss - secondary PIMs
PFC inductor 245 µH / 6.6 mΩ, output capacitor 4 × 470 µF / 91 mΩ 1.2:1, Lm 720µH, Ls 12µH, Lr 10µH (P»S) 1.2:1, Lm 720µH, Ls 12µH, Lr 10µH (P»S)
PFC inductor 180 µH / 11.3 mΩ, output capacitor 130 µF / 1.3 mΩ 1.4:1, Lm 720µH, Ls 12µH, Lr 10µH (P»S) 1.4:1, Lm 720µH, Ls 12µH, Lr 10µH (P»S)
PFC inductor 130 µH / 10 mΩ, output capacitor 130 µF / 1.3 mΩ 1.0:1, Lm 720µH, Ls 12µH, Lr 6.3µH (P»S) 1.0:1, Lm 720µH, Ls 12µH, Lr 6.3µH (P»S)
250 400
350

350

300
240
300

250
250

Power loss [W]

Power loss [W]

230
Power loss [W]

200
200

220 150
150

100
100
210

50 50

200 0 0
205 210 215 220 225 230 235 240 245 250 255 200 300 400 500 600 700 800 900 1000 200 300 400 500 600 700 800 900 1000
Phase to Neutral voltage [VRMS] Secondary side voltage [V] Secondary side voltage [V]
POUT = 26.5 kW, UOUT = 800 V, 50 Hz, SVM
Core losses of PFC inductor not included Stefan Kosterec, 25. Feb 2021 POUT = 25 kW (USEC ≥ 500 V), IOUT = 50 A (USEC < 500 V) Stefan Kosterec, 19. Jan 2021 POUT = 25 kW (USEC ≥ 500 V), IOUT = 50 A (USEC < 500 V) Stefan Kosterec, 19. Jan 2021

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Electromechanical Design Comparison
• Discrete assembly • Module assembly

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Electromechanical Design Comparison

• If we compare the same die in discrete (TO247) and Module (F1),

using the previous slide models, we get :
NTH4L020N120SC1 NXH020F120MNF1PTG
(Discrete SiC) (SiC Module)
EON EOFF EON EOFF
0.49 mJ 0.39 mJ 0.24 mJ 0.24 mJ
RthJC RthJH RthJC RthJH
Min 1 °C/W
0.80 °C/W
0.3 °C/W 3.3 °C/W 0.45 °C/W
with 5kV isolation
with 5kV isolation
PON (75 kHz / 100 kHz) POFF (75 kHz / 100 kHz) PON (75 kHz / 100 kHz) POFF (75 kHz / 100 kHz)
37 W / 49 W 29 W / 39 W 18 W / 24 W 18 W / 24 W
∆TJC ∆TJH ∆TJC ∆TJH
66 °C / 88 °C
20 °C / 26 °C 16 °C / 22 °C 29 °C / 38 °C
218 °C / 290 °C
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Mechanical Assembly

Modules (or PIMs) with (Heatsink and Fan) on top

Modules (or PIMs) with (Heatsink and Fan) on top

Air Flow cooling Boost Inductors

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Fan Speed Feedback Control Principle

• Using the NTC included in the module, we sense the die temperature
• The control board process this information and define fan speed using a PWM signal
• The PWM signal is used in a Buck stage to provide the fans supply voltage.

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NTC impedance Curve Simulation Model

• In the data sheet,

we find the following values :

• Here is the simulation

model results
(Nominal & +3% error)

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NTC Frontend Amplifier & Filter Principle

• We use a parallel + series resistor divider to linearize the NTC curve :

− The goal is to increase measurement accuracy at low temperature
when NTC varies in the range of Ohms per Degree Celsius.
• To avoid Common Mode noise, we use two resistors to measure the NTC.
• Then, we amplify by a factor of 10
• And we inverse the Output vs Temperature slope
− Now, when temperature increases, output amplifier voltage increases also
• Finally, we add a low pass filter to reject switching frequency

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NTC Frontend Amplifier & Filter Schematic

Inverter
Low Pass
Filter
Gain 10

Resistor Divider network

NTC Model

CM

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NTC Frontend Amplifier & Filter Results
NTC Curves Amplifiers’ Outputs

Low Pass Filter

Frequency Response

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Fan Control Principle

• The Fan can operate for zero rpm at 6.6 Vdc to full rpm at 12.7 Vdc
• We will drive the Buck stage that feed the Fan with a PWM signal coming from the
Control DSP as shown below :

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Fan Control Schematic
We need to stabilize the Buck stage loop with Fans that are large inductive loads.

Buck stage

Fans

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Fan Control Buck Stage Loop Response with Large Inductive Loads

In all cases, Phase Margin > 70°

& Gain Margin > 20 dB

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Gate drivers for Module SiC MOSFET

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Drivers Selection for the 25kW Power Stage

• The NCD57000 was selected because it offers the following features :

− 50 ns Propagation delay and 10 ns delay mismatch
− Low output internal impedance
− +4 A / -6 A capability
− 25 V output range
− 100 V/ns Immunity
− Active Miller Clamp
− DESAT protection
− 5-kVrms isolation
− 8-mm creepage

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Gate Driver Operation

• Turn-on current paths • Turn-off current paths

Internal Driver Impedance + External Gate Resistor +

Internal SiC MOSFET Gate Impedance are all limiting gate current

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Gate Driver Simulation Model

• We use a current source using a table to reflect the driver output impedance
VDD2

VDD2

B_SOURCE
B_SRC_ENA
R1 100 I = V(SRC_ENA)*SGN(V(VDD2,OUT))*TABLE(ABS(V(VDD2,OUT)),
+ 0, 0,
INP IN_POS SRC_ENA + 0.05, 50u,
+ 0.3, 200m,
+ 0.8, 1.0,
INN IN_NEG V=LIMIT((V(IN_POS,IN_NEG) - 0.55)/0.2,0,1) + 20.0, 7.8)
R2 100
+ +
C1 C2
390p IC=0 390p IC=0

OUT

GND1

GND1 B_SINK
B_SNK_ENA
I = V(SNK_ENA)* SGN(V(OUT,VEE2))*TABLE(ABS(V(OUT,VEE2)),
+ 0, 0,
SNK_ENA + 0.05, 50u,
+ 0.1, 200m,
VEE2 + 0.5, 1.0,
V= 1-LIMIT((V(IN_POS,IN_NEG) - 0.1)/0.35,0,1) + 15.9, 7.1)

VEE2

GND2 GND2

• The goal is to study turn-on and turn-off speed to limit EMI

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Drain Voltage Slope with 1.8 Ω External Resistor (PFC Example)

• At turn-on : Slope > 66 V/ns • At turn-off : Slope up to 40 V/ns

Ultrafast charger PFC: Low side A SiC MOSFET turn ON speed Ultrafast charger PFC: Low side A SiC MOSFET turn OFF speed
PFC inductor 245 µH / 6.6 mΩ, output capacitor 4 × 470 µF / 91 mΩ PFC inductor 245 µH / 6.6 mΩ, output capacitor 4 × 470 µF / 91 mΩ PFC inductor 180 µH / 11.3 mΩ, output capacitor 130 µF / 1.3 mΩ
PFC inductor 180 µH / 11.3 mΩ, output capacitor 130 µF / 1.3 mΩ
PFC inductor 130 µH / 10 mΩ, output capacitor 130 µF / 1.3 mΩ PFC inductor 130 µH / 10 mΩ, output capacitor 130 µF / 1.3 mΩ
69 43

42

68 41

40
Transition speed [V/ns]

Transition speed [V/ns]

67 39

38

66 37

36

65 35
205 210 215 220 225 230 235 240 245 250 255 205 210 215 220 225 230 235 240 245 250 255
Phase to Neutral voltage [VRMS] Phase to Neutral voltage [VRMS]
POUT = 26.5 kW, UOUT = 800 V, 50 Hz, SVM POUT = 26.5 kW, UOUT = 800 V, 50 Hz, SVM
Core losses of PFC inductor not included Stefan Kosterec, 25. Feb 2021 Core losses of PFC inductor not included Stefan Kosterec, 25. Feb 2021

To limit slope below 25 V/ns : To limit slope below 25 V/ns :

ON external resistance range = 2.5 Ω to 4.7 Ω ON external resistance range = 3.3 Ω

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Gate Driver Implementation
Using NCD57000/01 or new NCD57100/01

NCD57000
DESAT sensing

Charging & Discharging

Resistors

Gate Miller CLAMP

SiC MOSFETs Module

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Gate Driver Implementation
Using NCD57000/01 or new NCD57100/01

Active Miller
Sink Clamp VEE decoupling
Source resistor Capacitors
VEE
resistor Clamp (Bottom layer) Clamp
Sink Sink
VDD
Source Source
GND GND

Isolated Isolated
Gate Driver Gate Driver
Kelvin Emitter NCD57000 VDD decoupling
NCD57000
SiC Gate Capacitors (Top layer)
DESAT Sense

Layout Example

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 Auxiliary Supplies

Internal Power Distribution

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Auxiliary Supplies Need

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Auxiliary Supply Design : SECO-HVDCDC1362-40W-GEVB

• Follows IEC61851-1 guidelines

− 1000-V working voltage => 2.75 kVrms isolation voltage
• Topology : 40 W - 15 V / 2.6 A Flyback boundary conduction mode + ZCD clamp
− PWM : NCP1362 driving SiC MOSFET with 0 V - 12 V gate drive
 (no external dedicated SiC MOSFET driver helps saving cost)
− Main Switch : 1200 V, 160mΩ NTHL160N120SC1 SiC MOSFET
− ZCD clamp : US1FM1 Super Fast diode / 160V TVS
− Secondary rectifier diode : FFSP0665B

• We keep 100 V headroom for the SiC MOSFET

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SECO-HVDCDC1362-40W-GEVB Block Diagram

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Active Frontend Auxiliary Voltages Distribution
5V

NCV890100MWTXG UCB (PFGA controller)

`
3V3

NCV890100MWTXG Gate drivers primary side logic Vcc

`
20V/-5V
15V
800V SECO-HVDCDC1362- SECO-LVDCDC3064- SiC modules Gate driving

`
DC Link SiC-GEVB
`

40W-GEVB

6.6V-12.7V

NCV890100MWTXG PWM controlled FAN Vcc

`
5V
SECO-LVDCDC3064- Voltages and currents measurement

`
SiC-GEVB

5V
SECO-LVDCDC3064- PFC/DCDC stage HW interlock

`
SiC-GEVB
Isolated
5V
DC-DC SECO-LVDCDC3064- CAN bus interface

`
SiC-GEVB

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Dual Active Bridge Auxiliary Voltages Distribution
Disable signal based on power flow direction

5V
NCV890100MWTXG UCB (PFGA controller)

`
3V3
NCV890100MWTXG Gate drivers primary side logic Vcc

`
20V/-5V
800V SECO- 15V SECO-
DCDC stage HVDCDC1362- LVDCDC3064-SiC- SiC modules Gate driving

`
`
40W-GEVB GEVB
primary side
6.6V-12.7V
NCV890100MWTXG PWM controlled FAN Vcc

`
900V 5V
SECO- 15V SECO-
DCDC stage HVDCDC1362- LVDCDC3064-SiC- Phase to Phase voltage measurement

`
`

40W-GEVB GEVB
secondary side
5V
SECO-
LVDCDC3064-SiC- Output voltage and current measurement

`
GEVB

5V
SECO-
PFC/DCDC stage HW interlock
Isolated LVDCDC3064-SiC-

`
GEVB

DC-DC SECO-
5V
LVDCDC3064-SiC- CAN bus interface

`
GEVB

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 Conclusion

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Conclusion

• During this session, we have seen :

− Thermal Mechanical assembly analysis and why using modules makes sense
− Fan speed feedback control implementation was presented
− Critical components’ (gate driver and external gate resistor) effects were analyzed
− Isolated main auxiliary power design was explained
− Power distribution for each power stage was shown

• Next to come :
− Session 4 (June 29): Measurement Results

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