Bitfile : \\ggnnas1.ggn.is.keysight.

com\Corvette\FPGA\CXL\Bitfiles\30
09 Jul 23 June 2023
Sr No. Testcase Description Status Build->
https://artifactorysgp.it.keysight.com/artifactory/generic-local-corvette/SW/
Builds/develop/schooner/106_1e995d55d/
1 GUI Launch on HW Passed
Check for different device types ( type 1,
2 Link up at Gen 3,4,5 & hardware status Passed
type2 type 3 )
3 LTSSM basic gen3 & Gen 4 Check TX RX Bits in LTSSM and vLSM Passed
4 LTSSM high speed gen3 ->4 Passed
5 LTSSM low speed speed gen4 ->3 Passed
checking overall gui by opening each tab and
6 GUI overview checking Passed
and respective controls updating
7 Pcie Decoder Passed
Check for Different values of HDM Decoder
8 HDM Decoder Settings Testing and DVSEC Decoder and Check by changing Passed
Values from Config Space also
9 DVSEC Decoder Settings Testing Passed
10 Data Memory PCIE Passed
11 Data Memory Mem write data & reload data Passed
12 Hot Access data memory Not Executed Not released in this build.

Traffic CXL. IO packet -> Si tranaction -IO write read, set pcie decoder , send packet , check the
13 Passed
Def Write , ATS , PM VDM credits & completion packets

Traffic CXL. IO packet -> single Mode tranaction -IO set pcie decoder , send packet , check the
14 Passed
write read, Def Write , ATS , PM VDM credits & completion packets

Traffic CXL. IO Si Packet -> Request behaviour -IO

15 Passed
write read, Def Write , ATS , PM VDM
Traffic CXL. IO packet -> Cont. Mode tranaction -IO set pcie decoder , send packet , check the
16 Passed
write read, Def Write , ATS , PM VDM credits & completion packets

Traffic CXL. IO packet,IO Block -> Request behaviour

17 Passed
-IO write read, Def Write , ATS , PM VDM

Traffic CXL. IO packet -> completion behaviour -IO

18 Passed
write read, Def Write , ATS , PM VDM
Traffic CXL.Mem packet -> Si tranaction : both M2S & set decoder , send packet , check credits and
19 Passed
S2M packets completion packets
Traffic CXL.Mem packet -> Single Mode tranaction :
20 set decoder , send packet , check credits Passed
both M2S packets

Traffic CXL.Mem packet -> Cont. Mode tranaction :

21 set decoder , send packet , check credits Passed
both M2S packets

set decoder , send packet , check credits and

Traffic CXL.Mem packet -> Request behaviour check respective protocol cheker
22 Passed Si and Block: Checked with Corrupt flit crc and corrupt protocol id
tranaction : both M2S packets 1. Si transaction
2. Block transaction

set decoder , send packet , check credits and

Traffic CXL.Mem packet -> completion behaviour
23 check respective protocol cheker Passed
tranaction : both M2S packets
SI AND BLOCK

1. set decoder , send 1packet write packet

with data generation in block , check data
memory on other side
Traffic CXL.Mem packet -> Algorithmic Data 2. overwrite garbage data on data memory ,
24 Passed
generation send packet read packet with data
comparator in block , check algorithmic
comparator

Traffic CXL.Mem packet -> Algorithmic data

25 Passed
comparator

Check Single Packet by Adding Multiple Lines Mem

26 Passed
Packet
Check Block Request and Request Behave for
27 Passed
Multiple Lines Mem packet

Traffic CXL.Cache packet -> Si tranaction : D2H & send packet , check credits and completion
28 Passed
H2D packets packets
Traffic CXL.Cache packet -> Single Mode tranaction : send packet , check credits and completion
29 Passed
D2H & H2D packets packets , check data memory
Traffic CXL.Cache packet -> Cont. Mode tranaction : send packet , check credits and completion
30 Passed
D2H & H2D packets packets , check data memory
Traffic CXL.Cache packet -> Request behaviour : D2H send packet , check credits and check
31 Passed
& H2D packets respective protocol cheker
Traffic CXL.Cache packet -> Completion behaviour : send packet , check credits and check
32 Passed Tested with correctable id protocol
D2H & H2D packets respective protocol cheker
 Bitfile : \\ggnnas1.ggn.is.keysight.com\Corvette\FPGA\CXL\Bitfiles\30
09 Jul 23 June 2023
Sr No. Testcase Description Status Build->
https://artifactorysgp.it.keysight.com/artifactory/generic-local-corvette/SW/
Builds/develop/schooner/106_1e995d55d/
configure config setting , send packet with
compliance algorithm , check compliance
33 Traffic CXL.Cache packet -> compliance algorithm Passed
algorithm status in function status tab located
at hw status
D2H WRINv packet in Block single mode
34 Multi Data Header (MDH ) settings byte enable all 1 Passed
credit consumed -> in mutiple of 4
Check Single Packet by Adding Multiple Lines Cache
35 Passed
Packet
Check Block Request and Request Behave for
36 Passed
Multiple Lines Cache packet
37 Own PCIE Config space Passed
38 Own CXL Config space Passed
39 Own CXL RCRB Config space Passed
40 Own CXL component Config space Passed
scan dut , udpate config space and check
41 DUT PCIE Config space Passed
update value at own cofig space
scan dut , udpate config space and check
42 DUT CXL Config space Passed
update value at own cofig space
scan dut , udpate config space and check
43 DUT CXL RCRB Config space Passed
update value at own cofig space
scan dut , udpate config space and check
44 DUT CXL component Config space Passed
update value at own cofig space
write almp request packet and check the
45 ALMP packets Passed
status at other side exerciser.
start link layer insertion and check protocol
46 CXL Link layer insertion Passed
checker for respective error
set pattern matcher (mem ) and trigger out in
one exerciser and send packet from another
47 Pattern matcher Passed
exerciser and check trigger out at 1st
exerciser
apply setting in config space, power
48 Power Managment Passed
mangment , check vlsm state , retrain link
discover DOE , send opcode with custom
49 DOE Failed
payload , check the return status
send opcode with custom payload , check the
50 Mailbox Failed
return status
Change Credit Settings from GUI and Verify
51 Credit Control Setting Passed
using status
52 Credit Status Passed
Send Different types of Packets and check
53 Flit Counter Statistics Passed
the status
have to apply setting and check on upstream
54 Load Manager Failed
only
55 Function A, B, mem packet Passed
56 Function A, B Cache packet Passed
57 Save and Load Passed