Development of A Satellite Radiation Experiment For Evaluating SDRAM Memories in Harsh Environments

FEDERAL UNIVERSITY OF SANTA CATARINA
TECHNOLOGICAL CENTER
ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT
Development of a satellite radiation experiment for

evaluating SDRAM memories in harsh environments
Undergraduate Dissertation presented to the Federal University of Santa

Catarina as a requisite for the bachelor degree of Electronics Engineering
André Martins Pio de Mattos
Supervisor: Eduardo Augusto Bezerra, Ph.D.

Co-Supervisor: Luigi Dilillo, Dr.
Florianópolis, 2021
ANDRÉ MARTINS PIO DE MATTOS
DEVELOPMENT OF A SATELLITE RADIATION

EXPERIMENT FOR EVALUATING SDRAM
MEMORIES IN HARSH ENVIRONMENTS
Undergraduate Dissertation pre-

sented to the Federal University of
Santa Catarina as a requisite for
the bachelor degree of Electronics
Engineering. Supervisor: Eduardo
Augusto Bezerra. Co-Supervisor:
Luigi Dilillo.
FLORIANÓPOLIS
2021
Ficha de identificação da obra elaborada pelo autor,
através do Programa de Geração Automática da Biblioteca Universitária da UFSC.
Mattos, André Martins Pio de

Development of a satellite radiation experiment for
evaluating SDRAM memories in harsh environments / André
Martins Pio de Mattos ; orientador, Eduardo Augusto
Bezerra, coorientador, Luigi Dilillo, 2021.
100 p.
Trabalho de Conclusão de Curso (graduação) -

Universidade Federal de Santa Catarina, Centro Tecnológico,
Graduação em Engenharia Eletrônica, Florianópolis, 2021.
Inclui referências.
1. Engenharia Eletrônica. 2. Sistemas embarcados. 3.

Experimentos espaciais. 4. Ensaios de radiação. 5.
Satélites. I. Bezerra, Eduardo Augusto. II. Dilillo,
Luigi. III. Universidade Federal de Santa Catarina.
Graduação em Engenharia Eletrônica. IV. Título.
André Martins Pio de Mattos
DEVELOPMENT OF A SATELLITE RADIATION

EXPERIMENT FOR EVALUATING SDRAM MEMORIES IN
HARSH ENVIRONMENTS
Este Trabalho de Conclusão de Curso foi julgado adequado para a

obtenção do tı́tulo de Bacharel em Engenharia Eletrônica e aprovado em
sua forma final pela Banca Examinadora.
Florianópolis, 24 de setembro de 2021

Acknowledgments
This work is dedicated to everyone that allowed me to accomplish my
journey up to this point in life. I am grateful for all the support from
my family, my girlfriend, and friends. Also, for the opportunity that my
supervisor gave me to develop this work in a great international partner-
ship environment. I wish to extend a huge thank you to my laboratory
colleagues for the insightful discussions and learning experiences, the insti-
tutions that I have developed my research, and my internship supervisor
that supported this work.
Abstract
Electronics in the context of space applications require attention to per-

formance and reliability under harsh radiation conditions. This work pro-
poses the development of a platform capable of evaluating the radiation ef-
fects in three different generations of a same synchronous dynamic random-
access memory in test facilities and in a real space mission. The results are
interesting to characterize this devices for future space applications and
the platform could be used as a radiation sensor in future missions.
Keywords: satellite, CubeSat, radiation, payload, SDRAM, critical
applications, harsh environments, space, experiment, embedded systems.
Resumo
Sistemas eletrônicos no contexto de aplicações espaciais requerem es-

forços adicionais quanto ao desempenho e confiabilidade em ambientes com
alta radiação. Este trabalho propõe o desenvolvimento de uma plataforma
capaz de avaliar os efeitos da radiação em três gerações diferentes de uma
mesma memória dinâmica sı́ncrona de acesso aleatório em laboratórios de
teste e em missões espaciais reais. Os resultados são interessantes para
caracterizar esses dispositivos para futuras aplicações espaciais e também
a plataforma pode ser reutilizada como um sensor de radiação em futuras
missões.
Palavras-chave: satélite, CubeSat, radiação, carga útil, SDRAM, apli-
cações crı́ticas, espaço, experimento, sistemas embarcados.
Resumo Estendido
O crescente mercado de pequenos satélites [1] está liderando uma rápida

evolução da tecnologia e empurrando os limites de tamanho, consumo de
energia, confiabilidade e recursos dos sistemas embarcados. O CubeSat, um
padrão de satélite, e suas variantes estão surgindo como modelos promis-
sores para diversas aplicações em sensoriamento remoto, telecomunicações,
observação da Terra e até exploração espacial.
Comparando com os outros padrões e satélites de grande porte, que
usam componentes customizados para o uso espacial e requerem um es-
forço considerável no desenvolvimento e lançamento, o CubeSats tem uma
vantagem devido ao uso de componentes comercialmente disponı́veis para
outros setores (COTS) e a reduzida logı́stica envolvida que impacta dire-
tamente no custo da missão.
Apesar destas vantagens, as missões com CubeSats ainda não atingem
todas as aplicações do setor espacial, devido ao escopo ou mesmo a uma in-
viabilidade tecnológica, reforçando que as missões convencionais ainda têm
relevância e importância no assunto. Este cenário traz um novo horizonte
para os avanços tecnológicos e incentiva o uso generalizado de pequenos
satélites para resolver problemas desafiadores e melhorar a compreensão
do espaço.
O ambiente enfrentado nessas missões espaciais é hostil devido às dramáti-
cas variações de temperatura, vácuo, doses de radiação e estresse mecânico
durante o lançamento. Esses parâmetros atingem nı́veis crı́ticos ao consid-
erar missões de longo prazo ou órbitas de altitude mais elevada. A maioria
das missões de CubeSat são lançadas em perfis de órbita de baixa alti-
tude, onde as condições são menos exigentes, mas ainda assim perigosas e
onerosas para o desenvolvimento. Além disso, a utilização de componentes
COTS sem cautela e análise prévia pode levar a falhas catastróficas como
consequência da criação de pontos de falha e imprevisibilidade no sistema.
Por esse motivo, diversos estudos estão sendo realizados para identificar e
quantificar as vulnerabilidades desses componentes no ambiente espacial.
A condição mais desafiadora a superar é a quantidade significativa de
radiação na qual esses sistemas são expostos fora da proteção do campo
magnético terrestre. Desde o lançamento, o satélite está exposto a um am-
plo espectro de interações de radiação aleatórias com diversas magnitudes
e consequências [2]. Para minimizar esses efeitos, diferentes abordagens
são adotadas em várias camadas, desde a própria arquitetura de hardware
até complexas técnicas de correção de erros e redundâncias de software.
Undergraduate Dissertation
Assim, avaliar a vulnerabilidade desses componentes devido à exposição à

radiação e caracterizar os limiares de falha crı́tica são essenciais para de-
terminar os esforços que devem ser aplicados durante o desenvolvimento.
As memórias de circuito integrado, em uma ampla variedade de tecnolo-
gias e caracterı́sticas operacionais, são um dos componentes crı́ticos mais
afetados pelas altas doses de radiação [3].
Os esforços deste trabalho se concentram no desenvolvimento de uma
plataforma capaz de realizar a caracterização da radiação de diferentes
memórias SDRAM em condições espaciais. Esta plataforma testará estes
chips no ambiente espacial, participando da missão FloripaSat-2. As memó-
rias utilizadas foram previamente caracterizadas em experimentos de lab-
oratório, então, ao expor esses dispositivos a ambientes reais e executar
as mesmas rotinas de teste, não apenas será possı́vel gerar mais resulta-
dos para análise, mas também fornecerá uma oportunidade para avaliar as
próprias metodologias de teste. Além disso, após coletar dados suficientes
para serem analisados, essa carga útil poderá ser usada para fornecer um
status da missão, no que diz respeito às doses de radiação a que o satélite
foi exposto.
A arquitetura de carga útil consiste nos seguintes módulos: um subsis-
tema de controle e gerenciamento do experimento, operado por um System-
On-a-Chip (SoC); conversores de energia para fornecimento dos nı́veis de
tensão adequados; monitores de curto-circuito; barramentos e interface de
comunicação; e os chips de memória SDRAM em análise.
O trabalho está estruturado nas seguintes seções: contextualização (back-
ground), fornecendo uma explicação simplificada dos principais tópicos
abordados neste trabalho; análise da missão (mission analysis), descrevendo
o contexto em que o experimento é realizado e definindo os requisitos para o
desenvolvimento deste trabalho; desenvolvimento (development), apresen-
tando todos os sistemas desenvolvidos e integrados para criar a plataforma
e discutindo suas motivações, estratégias e diretrizes; resultados (results),
descrevendo os testes executados e seus resultados para validar o funciona-
mento da plataforma; e conclusão (conclusion), apresentando as consider-
ações finais. O corpo do trabalho será descrito ao longo das seções do texto
original no idioma inglês.
14
Acronyms
Acronyms
General Nomenclature
CAD Computer-Aided Design.
COTS Commercial Of-The-Shelf.
ESA European Space Agency.
FPGA Field-Programmable Gate Array.
HDL Hardware Description Language.
IC Integrated Circuit.
LEO Low-Earth Orbit.
LIRMM Laboratory of Computer Science, Robotics and Microelec-
tronics of Montpellier.
OBC On-Board Computer.
OBDH On-Board Data Handling.
PCB Printed Circuit Board.
RADEF RADiation Effects Facility.
RTOS Real-Time Operating System.
SAA South Atlantic Anomaly.
SoC System-On-A-Chip.
SpaceLab Space Technology Research Laboratory.
VESPER Very energetic Electron facility for Space Planetary Explo-
ration missions in harsh Radiative environments.
Memory Technologies
DDR Double Data Rate.
eNVM Embedded Non-Volatile Memory.
eSRAM Embedded Static Random-Access Memory.
Flash Flash is a non-volatile memory.
FRAM Ferroelectric Random-Access Memory.
MRAM Magnetoresistive Random-Access Memory.
NOR Flash Flash based on NOR logic gates.
SDRAM Synchronous Dynamic Random-Access Memory.
SDR Single Data Rate.
Radiation Effects
DD Displacement Damage.
MBU Multiple-Bit Upset.
MCU Multiple-Cell Upset.
SBU Single-Bit Upset.
SEB Single Event Burnout.
i
SEE Single Event Effect.

SEFI Single Event Functional Interruption.
SEGR Single Event Gate Rupture.
SEL Single Event Latch-up.
SET Single Event Transient.
TID Total Ionizing Dose.
Communication Protocols
AHB Advanced High-performance Bus.
AMBA ARM Advanced Microcontroller Bus Architecture.
AXI Advanced eXtensible Interface.
FSP FloripaSat Protocol.
I2C Inter-Integrated Circuit.
JTAG Joint Test Action Group.
SPI Serial Peripheral Interface.
UART Universal Asynchronous Receiver-Transmitter.
Error Mitigation Techniques
CRC Cyclic Redundancy Check.
SECDED Single Error Correction, Double Error Detection.
Specific Nomenclature
BFM Bus Functional Model.
BGA Ball Grid Array.
GPIO General Purpose Input and Output.
MSS Microcontroller SubSystem.
SMC Soft Memory Controller.
TSOP Thin Small Outline Package.
ii
List of Figures
List of Figures
3.1 Conceptual exploded view of a CubeSat (FloripaSat-2). . . . 7
3.2 Simplified FPGA internal architecture. . . . . . . . . . . . . 10
3.3 Conceptual PCB board. . . . . . . . . . . . . . . . . . . . . 12
4.1 A preview of the satellite simulated groundtrack. . . . . . . 14
4.2 Schematic overview of the Van Allen radiation belts. . . . . 14
4.3 Simplified preview of the radiation vulnerable regions. . . . . 15
4.4 Inside view of the SDRAM memory chip (IS42S16320F). . . 16
5.1 Preview of the developed payload. . . . . . . . . . . . . . . . 19
5.2 Development board used during the prototype phase. . . . . 21
5.3 Simplified engineering model architecture. . . . . . . . . . . 22
5.4 Conceptual payload model integrated with the FloripaSat-2
OBDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 Payload model integrated with FloripaSat-2 OBDH. . . . . . 23
5.6 FPGA die overview. . . . . . . . . . . . . . . . . . . . . . . 24
5.7 Internal architecture diagram overview. . . . . . . . . . . . . 26
5.8 Memory controller interfaces overview. . . . . . . . . . . . . 27
5.9 Core SDR wrapped for an AXI interface architecture. . . . . 28
5.10 Core SDR Address scheme overview. . . . . . . . . . . . . . 28
5.11 Core SDR architecture diagram overview. . . . . . . . . . . . 29
5.12 eSRAM memory scheme. . . . . . . . . . . . . . . . . . . . . 30
5.13 System abstraction layers diagram. . . . . . . . . . . . . . . 34
5.14 Simplified system execution flow diagram. . . . . . . . . . . 35
5.15 System architecture diagram. . . . . . . . . . . . . . . . . . 36
5.16 Experiment architecture diagram. . . . . . . . . . . . . . . . 38
5.17 Communication interrupt and task architecture diagram. . . 39
5.18 Board stackup planning. . . . . . . . . . . . . . . . . . . . . 46
5.19 FPGA pinout usage. . . . . . . . . . . . . . . . . . . . . . . 47
5.20 Top Mid-layer routing with focus on the memory address
signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.21 Bottom Mid-layer routing with focus on the memory address
signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.22 Hardware architecture overview. . . . . . . . . . . . . . . . . 49
5.23 Power architecture overview. . . . . . . . . . . . . . . . . . . 50
5.24 PCB 3D rendering overview. . . . . . . . . . . . . . . . . . . 50
5.25 PCB manufactured overview. . . . . . . . . . . . . . . . . . 51
5.26 FPGA fanout dog-bone pattern and decoupling capacitors
implementation. . . . . . . . . . . . . . . . . . . . . . . . . . 51
iii
6.1 Memory controller simulation flow. . . . . . . . . . . . . . . 55

6.2 Memory controller simulation results: log output. . . . . . . 56
6.3 Memory controller simulation results: signal waveforms. . . . 57
6.4 Hardware test results: fully operational board. . . . . . . . . 58
6.5 Hardware test results: average power consumption. . . . . . 58
6.6 Example of a firmware log message. . . . . . . . . . . . . . . 59
6.7 Experiment radiation parameters. . . . . . . . . . . . . . . . 60
6.8 Radiation experiment setup diagram. . . . . . . . . . . . . . 61
6.9 Payload board in red fixed inside the beam area in blue. . . 61
6.10 Radiation cross section results according with the SDRAM
memories technology scaling (models B, D, and F). . . . . . 62
6.11 Integration setup with FloripaSat-1 OBDH engineering model 63
6.12 Engineering model payload integrated with the FloripaSat-2
OBDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.13 Example SPI command communication signals from the OBC
to the payload using the FSP protocol. . . . . . . . . . . . . 64
6.14 Example SPI acknowledgement answer communication sig-
nals from the OBC to the payload using the FSP protocol. . 65
6.15 Flight model payload model integrated with FloripaSat-2
platform in the FlatSat. . . . . . . . . . . . . . . . . . . . . 66
6.16 Flight model payload model integrated with FloripaSat-2
platform (payload highlighted). . . . . . . . . . . . . . . . . 67
iv
List of Tables
List of Tables
5.1 Project phase progress according to the specifications. . . . . 20
5.2 FSPv0.2 package fields. . . . . . . . . . . . . . . . . . . . . . 39
5.3 FSPv0.2 adresses. . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4 FSPv0.2 package types. . . . . . . . . . . . . . . . . . . . . . 40
5.5 FSPv0.2 commands. . . . . . . . . . . . . . . . . . . . . . . 40
5.6 Summary of ESA guidelines. . . . . . . . . . . . . . . . . . . 42
v
Contents
Acronyms i
List of Figures iii
List of Tables v
1 Introduction 1
1.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Work Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Methodology 4
2.1 Experimental setup . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Hardware development . . . . . . . . . . . . . . . . . . . . . 5
2.3 Firmware development . . . . . . . . . . . . . . . . . . . . . 5
2.4 SoC FPGA development . . . . . . . . . . . . . . . . . . . . 5
2.5 Project management . . . . . . . . . . . . . . . . . . . . . . 6
3 Background 7
3.1 CubeSat Standard . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Radiation Effects . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 SDRAM Memories . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 FPGA Devices . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 PCB Principles . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Mission Analysis 13
4.1 Environmental Parameters . . . . . . . . . . . . . . . . . . . 13
4.2 Memory Experiment Analysis . . . . . . . . . . . . . . . . . 16
4.3 Payload Specification . . . . . . . . . . . . . . . . . . . . . . 17
5 Development 19
5.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 Prototype . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2 Engineering Model . . . . . . . . . . . . . . . . . . . 21
5.1.3 Flight Model . . . . . . . . . . . . . . . . . . . . . . 23
5.2 SoC FPGA Architecture . . . . . . . . . . . . . . . . . . . . 24
5.2.1 Design Overview . . . . . . . . . . . . . . . . . . . . 25
5.3 Firmware Architecture . . . . . . . . . . . . . . . . . . . . . 32
5.3.1 Design Guidelines . . . . . . . . . . . . . . . . . . . . 32
vi
Contents
5.3.2 Design Overview . . . . . . . . . . . . . . . . . . . . 34

5.3.3 Memory Fault Detection Algorithms . . . . . . . . . 40
5.4 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . 42
5.4.1 Design Guidelines . . . . . . . . . . . . . . . . . . . . 42
5.4.2 Preliminary Design Analysis . . . . . . . . . . . . . . 46
5.4.3 Design Overview . . . . . . . . . . . . . . . . . . . . 49
6 Results 55
6.1 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2 Hardware Tests . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 Firmware Tests . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4 Radiation Tests . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.5 Engineering Model Integration . . . . . . . . . . . . . . . . . 63
6.6 Flight Model Integration . . . . . . . . . . . . . . . . . . . . 65
7 Conclusion 68
References 72
A Payload hardware schematics 73
vii
1 Introduction
The increasingly market of small spacecrafts [1] is leading a rapid evolution
of the technology and standards employed in these missions and pushing
the limits of size, power consumption, reliability and capabilities of the
embedded systems. The CubeSat, a satellite standard, and its variants are
emerging as promising models for several applications in remote sensing,
telecommunications, earth observation and even space exploration.
Comparing with the other standards and bulky satellites, which use
high-end and tailored components and require considerable effort in devel-
opment and launch, the CubeSats have an advantage due to the use of
Commercial Of-The-Shelf (COTS) components and the reduced logistics
involved that impacts directly in the mission cost.
Despite this advantage, the CubeSat missions do not reach all the space
sector applications yet, due to the size scope or even a technological im-
practicability, reinforcing that the bulky missions still have relevance and
importance in the subject. This scenario brings a new horizon for techno-
logical advances and encourage the widespread usage of small satellites to
solve challenging problems and enhance the understanding of the space.
The environment faced in these space missions is harsh due to dramatic
temperature variations, vacuum, radiation doses, and mechanical stress
during the launch. These parameters achieve critical levels when consider-
ing long-term missions or higher altitude orbits. The majority of CubeSat
missions are deployed in low altitude orbit profiles, where the conditions are
less demanding, nevertheless still dangerous and onerous for development.
Also, the utilization of COTS components without caution and previous
analysis could lead to catastrophic failures as consequence of the creation
of bottlenecks and unpredictability in the system. For this reason, several
studies are being carried out to identify and quantify the vulnerabilities of
these components in the space environment.
The most challenging condition to overcome is the significant amount
of radiation in which these systems are exposed outside the protection of
the earth magnetic field. Since the deployment, the satellite is exposed
to a wide spectrum of random radiation interactions with diverse magni-
tudes and consequences [2]. In order to minimize these effects, different
approaches are adopted in various layers, since the hardware architecture
itself to complex software correction error techniques and redundancies.
Then, evaluating the vulnerability of those components due to the radia-
tion exposure and characterizing the critical failure thresholds are essential
1
to determine the efforts that should be applied during the development.

The Integrated Circuit (IC) memories, in a wide variety of technologies,
system integration, manufacturing nodes, and operational characteristics,
are one of the most critical components affected by the high doses of radi-
ation [3].
The capacity of these devices, the importance of the information stored,
and the strict requirements imposed make unfeasible, in several applica-
tions, the employment of intensive failure mitigation techniques due to the
performance trade-offs or even the substantial amounts of data. For this
reason, other approaches are investigated, which generally leads for high-
cost custom hardened devices for specific niches. Therefore, it is essential
to evaluate the real vulnerability of these components and determine which
radiation mitigation strategy is required in each application.
In this context, two types of memory could be enumerated: non-volatile
and volatile. The first group offers technologies with significant robustness
within radiation exposure conditions without technological enhancements,
such as: NOR Flash, MRAM, and FRAM. Also, due to less performance
intensive requirements, some memory management techniques can signifi-
cantly reduce errors and degradation. However, the pressure to fulfill the
performance needs of demanding applications with the available volatile
memory technologies introduce challenges that are under the analysis of
many studies. The most performance capable and widespread technologies
are the Synchronous Dynamic Random-Access Memory (SDRAM) chips,
which are being improved and tailored for decades in the personal comput-
ers, workstations and servers industries.
1.1 Objectives
The efforts of this work focus on the development of a platform capable
of performing radiation characterization of different SDRAM memories in
space conditions. This payload will test these chips in the real harsh space
environment by participating of the FloripaSat-2 mission. These particular
SDRAM memories were previous characterized on laboratory experiments,
then by exposing them to the real environments and executing the same
tests routines will not only generate more results for analysis, but also
provide an opportunity to assess the test methodologies themselves. Also,
after collecting sufficient data to be analysed, this payload could be used to
provide a meaningful health status, concerning the radiation doses which
the satellite was exposed.
In order to accomplish these objectives, the payload is designed to fol-
2
1.2 Work Outline
low the FloripaSat-2 OBDH DaughterBoard standard [4] [5], which defines
the connectors, shape and size of the board. This standard allows the uti-
lization of the module throughout future FloripaSat [6] core1 missions in
reason of its low space occupation inside the CubeSat, being considered in
further uses as an expansion module instead of a payload experiment. Also,
due to the mission limited power budget, the developed board consider re-
duced power consumption and define clever power management strategies.
In addition, methods for monitoring latch-up, a type of short circuit which
can occur inside an IC, are considered in the design.
Therefore, combining all these requirements, the payload architecture
should consists of the following modules: a control and management sub-
system, operated by a System-On-a-Chip (SoC) solution Field-Programmable
Gate Array (FPGA) [7]; power converters for properly voltage level supply;
latch-up monitors; communication and interface buses; debug module; and
the SDRAM memory chips.
1.2 Work Outline

The work is structured in the following sections: background, providing a
detailed explanation of the main topics approached in this work; mission
analysis, describing the context in which the experiment is performed and
defining the requirements for the development of this work; development,
introducing all the systems developed and integrated to create the exper-
iment platform and presenting the motivations, strategies, and guidelines
for them; results, describing the executed tests and their results to validate
the operation of the platform; and conclusion, providing a summary of the
outcomes of the work.
1
The FloripaSat-2 mission reuses the FloripaSat-1 core modules.
3
2 Methodology
Regarding the methodology applied for the development of this payload,
a significant background knowledge came from both laboratory members
and professors during years of experience working with dependable embed-
ded systems, radiation tolerant devices, experimental tests, and extensive
data analysis in the subject. The work was mainly developed as part of
an internship in the Laboratory of Computer Science, Robotics and Mi-
croelectronics of Montpellier (LIRMM), with later support of the group
for testing in radiation facilities. Then, the conclusion of the project and
the integration with the FloripaSat-2 mission was performed in the Space
Technology Research Laboratory (SpaceLab).
Some important architectural decisions and considerations were result
of discussions based on previous publications and experiments. Moreover,
during the development, different design guidelines were used to improve
the payload architecture and overall reliability. Some of this standards are
managed by respected institutions and incorporate a wide variety of sys-
tems, including high complexity missions and critical applications. Then,
despite being based on these standards, the scope is scaled and simplified
to attend the demands of a CubeSat project and the payload impacts on
the success criteria of the satellite mission. The following topics describe
the methodology used for the main aspects of this work.
2.1 Experimental setup

This payload uses previous works as a base for the experimental setup,
particularly, the analysis of a wide variety of memories in harsh radiation
conditions of the doctorate student Viyas Gupta [3] and the experiments
performed at the RADEF (Jyväskylä, Finland) and at VESPER (CERN,
Switzerland) facilities evaluating the same SDRAMs chips used in this
project [8]. Then, this work uses this background knowledge intending
to expand characterization of the memories behavior and fault models in
harsh radiation conditions.
Following the same approach, the memory tests are implemented using
standardized methods, which are subdivided in two categories: static and
dynamic [9]. The static tests consist in evaluating the memory in absence
of commands or single operation bursts and the dynamic covering the fault
events in case of multiple operation bursts, in which each operation is
a read, write, and cell refresh execution. In order to fulfill a significant
part of the fault cases, different static and dynamic tests are executed
4
2.2 Hardware development
continuously seeking for their condition specific deviations. Since the same
algorithms were used in the laboratory experiments, similar results are
expected, unless unpredictable rare events occurs, and a correlation could
be traced between the ground and space test segments.
2.2 Hardware development

The hardware development methodology consisted of following key prac-
tices and guidelines to guarantee the proper board operation from the first
time manufacturing it. For instance, the Printed Circuit Board (PCB) fol-
lows a simplified version of the European Space Agency (ESA) [10] guide-
lines, which were adapted for another CubeSat payload in a similar mission,
regarding objectives and radiation concerns [11].
The design process consists of several repeated steps until the PCB
project completion: requirement analysis, components selection, schemat-
ics preparation, layout design, design rules verification, and manufactura-
bility assessment. Note that this process is iterative, in other words, many
of these steps are repeated until a solid PCB design is achieved. For that,
several independent reviews are performed intending to mitigate the risks
before the actual board production.
2.3 Firmware development

Similar to the hardware strategy, the flight firmware is a iterative process
requiring different assessments and tests. Also, previous experience and
guidelines form the base of the code, where the FloripaSat-2 OBDH design
and development strategy are a key source of inspiration. In section 5 this
characteristics are extensively debated and the main ideas for increasing
the payload reliability and code quality are detailed.
The project started with a simple firmware prototype developed for a de-
velopment kit. Then, a firmware with a robust architecture was introduced
after the addition of several functional and safety features and the execu-
tion of tests. This final version is able to flight alongside the FloripaSat-2
OBDH, following its requirements and standards.
2.4 SoC FPGA development

In order to reduce the development time, the SoC FPGA design is based
on implementations and tools provided by the device manufacturer. This
approach is possible since the experiment requirements require only stan-
dard interfaces with the memories chips. Then, the development consists
5
of integrating different available blocks (e.g., memory controller, micro-

processor, and peripherals), enabling safety features (e.g., watchdog, and
SECDED), and testing these elements by simulations and in the target
hardware platforms.
2.5 Project management

The project execution was divided in different phases, including require-
ments definition, documentation and design reviews. Generally, a standard
used for space application is the systems engineering methodology, which
defines the space mission from its initial specification until the operations
finalization [12]. This standard require long-term planning and develop-
ment periods, support multidisciplinary teams and produce high reliability
systems. Then, for the scope of this work only key aspects and good prac-
tice patterns were followed. Also, regarding this project premises, agile
standards are incorporated into the processes in order to increase the over-
all payload quality despite the rapidly development campaign.
6
3 Background
3.1 CubeSat Standard
This work proposes a scientific experiment payload for CubeSats [13], a
nanosatellite [1] standard. This standard of satellites consists of specific
criteria for its shape, size, and weight, which help reduce costs due to the
higher feasibility for mass-production and availability of off-the-shelf parts.
Besides these benefits, the standardization reduces the development time
and ease the access of transportation and deployment into space.
Essentially, CubeSats are satellites composed by small cube units, which
might be combined to form larger spacecrafts and to attend the mission
requirements and goals. This ”unit” is referred to as a 1U, then a 1U Cube-
Sat is a 10 cm cube with a mass of approximately 1 to 1.33 kg. Figure 3.1
shows an illustrative diagram of the internal architecture of a 2U CubeSat,
containing the core modules (power management, data handling and com-
munication), payloads2 (primary and secondary experiments), solar panels,
antennas and others auxiliary modules.
Figure 3.1: Conceptual exploded view of a CubeSat (FloripaSat-2).
Source: SpaceLab, 2020.
2
The ”Radiation Monitor” illustrated in the diagram is the payload proposed in this work. It also
presents its preliminary location inside the satellite.
7
3.2 Radiation Effects

The space is full of engineering challenges related to the harsh environment
conditions, including: mechanical stress, drastic temperature variations
and severe radiation doses. This work focus on the last aspect, analysing
its influence in electronic devices and evaluating the temporary and cumu-
lative damaging phenomena. These effects are characterized by the Single
Event Effects (SEEs), caused by transient interactions, and the Total Ion-
izing Dose (TID) and Displacement Damage (DD), caused by accumulative
interactions. The sensitive circuit nodes are affected or permanently dam-
aged with the penetration of ionizing particles, which are representative
outside the Earth’s magnetic field protection [14] [15] [16].
The interaction with ionizing particles can induce the occurrence of in-
stantaneous damaging events, which are characterized by the single event
effects in various categories depending on the errors produced and the de-
vice components affected: Single-Bit Upset (SBU), soft-error; Multiple-Bit
Upset (MBU), soft-error; Multiple-Cell Upset (MCU), soft-error; Single
Event Transient (SET), soft-error; Single Event Functional Interruption
(SEFI), soft-error; Single Event Latch-up (SEL), hard/soft-error; Single
Event Gate Rupture (SEGR), hard-error; and Single Event Burnout (SEB),
hard-error [14]. These effects might lead to soft-errors, errors that are re-
versible since can be mitigated by power cycles, resets, or other erase oper-
ations. In other cases, the effects induce hard-errors, leading to permanent
device failure.
Both SBUs and MBUs are transient events that causes bit-flips (upsets)
within a memory cell or latch, differing in the quantity of elements affected.
Similarly, the MCUs are caused by the generation of two or more bit-flips
within a cell array. The SETs are characterized by the collection of free
carriers generated that induce a current or voltage transient that may lead
to an error. The SEFIs are caused due to a perturbation in control signals,
causing a loss of functionality and entering in a undefined state, a test
mode, or a halt. The SELs occurs when a parasitic thyristor is triggered in
the device structure, which generates high-current consumption and may
lead to a thermal overheat in the affected region. The SEGRs occurs when
a particle hit breaks the gate dielectric of a MOS transistor and the SEBs
when a strike causes a destructive burnout due to high-currents.
The cumulative effects depends on the continuous exposure to radiation
conditions that degrades the function of the device until its operation is
definitely compromised [15]. The TID is a long-term failure mechanism
8
3.3 SDRAM Memories
that causes shift in the transistors threshold voltage, increase of leakage

currents (power consumption), and also the degradation of the gain in
bipolar devices. The DD effect is the result of collisions between high-
energy protons and the device that, when a minimum required energy is
achieved, creates deformities in the lattice by removing the hit atom which
results in different local electrical characteristics. The accumulation of
this effect with energy above the displacement threshold can create a large
fault cluster. For instance, it causes the reduction in bipolar transistor
gain, reduction of the efficiency in solar cells, light emitting diodes and
photodetectors, charge transfer inefficiency in charge coupled devices and
resolution degradation in solid-state detectors.
3.3 SDRAM Memories

Synchronous dynamic random-access memories (SDRAM) are dynamic
random-access memories (DRAM) whose operation is coordinated by an
external supplied clock signal. The DRAM devices are a type of random
access semiconductor memory that stores each bit of data in a cell structure
based on a capacitor and a transistor. The capacitor retains or releases the
energy during charge and discharge events controlled through the transis-
tor. These two states, charged and discharged, represent the two values of
a bit. However, due to parasitic coupling loads, the capacitor slowly leaks
off, which leads to data loss after a certain period. Then, to prevent this,
the device requires an external controller to perform periodic refresh cycles
that rewrites the data in the capacitors, restoring them to their original
initial charge.
The DRAM memories have the disadvantage of direct influence of input
signals in the internal functions since each combination of control signals
determine the execution of one memory operation (e.g, read, write, and
refresh). Using a synchronous interface, it is possible to use pipeline tech-
niques that improve the memory performance in comparison with asyn-
chronous interfaces at the same frequency of operation. Pipelining means
that the device can handle new commands before the termination a previ-
ous operation processing. Then, write and read commands can be followed
by other commands after a fixed number of clock cycles (latency). Also, to
improve even more the access operation speed, the memory is divided into
equally sized sections called banks, which allows independent operations
occurring simultaneously. This architecture enables SDRAMs to achieve
greater concurrency and higher data throughput than the asynchronous
memories.
9
These devices are susceptible to harsh radiation environments and many

studies are carried out to evaluate their behavior in different conditions
using ground-based experiments [17] [18] [19].
3.4 FPGA Devices

A Field-Programmable Gate Array (FPGA) is an integrated circuit de-
signed to be reconfigurable after manufacturing, differing from its counter-
parts that are purpose specific and unchangeable. Then, it can be config-
ured by the developer to perform almost any digital operations in various
levels of complexity using a Hardware Description Languages (HDL) and
automation tools to translate the high-level commands into the physical
structure combinations. The device contains an array of programmable
logic blocks and a hierarchy of reconfigurable interconnects that enables
the blocks to be combined for creating complex structures or merely sim-
ple logic gates (e.g., AND, OR, XOR). Also, in the majority of the devices,
these blocks include memory elements that might be from simple flip-flops
to more complete blocks of memory. Figure 3.2 illustrates a simplified
internal architecture of these devices.
Figure 3.2: Simplified FPGA internal architecture.
Source: allaboutfpga, 2021.
The FPGAs core structure can be combined with other technologies

and structures to form even more flexible and ready to use devices. This
mixed chips are generally referred to as System-On-a-Chip (SoC) devices
10
3.5 PCB Principles
[7], which internal architecture combine several elements to attend the

different elements required by an application in an unique and compact
solution. For instance, in this work is used a SoC solution that includes
a FPGA array, an ARM-core processor, volatile and non-volatile memo-
ries, communication interfaces, clock sources and conditioners, independent
memory controllers, and a bus interface. In subsection 5.2 the device and
its subsystems are described with more depth.
Besides the architectural aspect of FPGA devices, the technology em-
ployed is important to determine its characteristics under radiation con-
ditions. Despite the chosen chip not being a rad-hard device, it presents
robust attributes in comparison with regular systems due to its Flash based
implementation [3] and radiation characterization reports provided by the
manufacturer [20] [21].
3.5 PCB Principles

The Printed Circuit Boards (PCB) are a combination of interspersed lay-
ers of conductive and non-conductive materials to form electrical circuits.
These layers and electrical circuits are connected using structures called
”vias” and ”tracks”, respectively. The electronic components are attached,
electrically and mechanically, in the external layers through a soldering
process in their corresponding ”pads” (i.e., the designated electrical inter-
face location). Figure 3.3 presents a simplified conceptual diagram of a
multi-layer PCB.
Using electronic Computer-Aided Design (CAD) tools, the PCBs are
deigned for production in specialized companies that use automated ma-
chinery from the board manufacturing and assembly to optical and electri-
cal testing. Due to this production chain, the PCBs design can incorporate
high precision layouts, which allowed their evolution for complex circuits
and structures. However, this progress exploiting the limit of the physical
implementation transformed the development of these boards a challeng-
ing task. Some unusual and counter intuitive effects start to change the
expected characteristics of the circuits, which might lead to defective de-
signs. For instance, when working with high-speed 3 signals, their integrity
might be compromised by mismatching in length, impedance, reflections,
crosstalking, and return paths.
In order to avoid these phenomena, the PCB designers use mitigation
techniques and follow validated standards. In this work, the developed
3
Signals with short periods of time during edge-to-edge changes, which generally appears in higher
frequencies.
11
board required some measures to guarantee the proper operation and meet
the requirements, since it is designed for space applications [11]. These
techniques and patters are described in further sections and the proper
justifications provided.
Figure 3.3: Conceptual PCB board.
Source: PCBWay, 2020.
12
4 Mission Analysis
Before defining the payload specification and the subsystems architecture,
it is important to estimate and preview the environmental conditions in
which the system will be exposed. Also, since the payload objective is to
evaluate the SDRAM memories, it is important to use previous laboratory
experiments to predict and estimate the faults associated with radiation
exposure, besides the required information to define timing and operation
parameters during the in-orbit experiments. The following sections present
the effects and concerns for the critical environment parameters in which
the payload is exposed and provide an analysis of memory experiments and
results.
4.1 Environmental Parameters

In order to predict the environmental conditions, the orbit parameters are
required and since the payload is designed for CubeSats, generally in Low-
Earth Orbits (LEO), the parameters should be analysed in a mean orbit
in this range. Since the payload experiment is part of the FloripaSat-2
mission, the estimations presented in the work are performed for this mis-
sion parameters: heliosynchronous orbit; 98o inclination; 500 km apogee
and perigee; approximately 100 minutes orbit period; approximately 0 ec-
centricity. Since the orbit is heliosynchronous and circular, the satellite
follows a circumference in a pole to pole trajectory, which traces almost a
perpendicular line with the equator plane. Then, due to the Earth rotation
around its own axis, the satellite describes an orbit that periodically covers
the entire sphere area relative to the Earth surface. Figure 4.1 presents a
preview of this orbit using the parameters herein described and demon-
strate the relative surface coverage in orbital passages.
Radiation Analysis
In this orbit (LEO), the satellite is protected against the major part of
the high energy particles and radiation, due to the Earth magnetic field
shielding. However, there are two problematic regions, in terms of high ex-
posure: the South Atlantic Anomaly (SAA) and in high latitudes (around
the magnetic axis) [15]. Figure 4.2 shows schematically the magnetic belts,
known as Van Allen radiation belts, and the region where the anomaly is
located. The high energy particles are entirely deflected from the Earth
trajectory or experience severe deviation hitting the Earth poles, as con-
13
Figure 4.1: A preview of the satellite simulated groundtrack.
Source: SpaceLab, 2021
sequence of the magnetic interactions. The lower energy, although still

ionizing and harmful, particles achieve the lower orbits and might cause
damages in the most sensible electronic devices. Moreover, the SAA re-
gion, where the inner radiation belt is closest to the Earth surface, increase
the amount of exposure of higher energy particles in a considerable area,
expanding the harmful effects in the satellites subsystems.
Figure 4.2: Schematic overview of the Van Allen radiation belts.
Source: Wikipedia, 2021
In order to characterize these belts and evaluate the ionizing parti-

cle penetration, the PROBA-V mission [22], using advanced equipment,
performed measurements of these particles in different energy intervals.
The measures include: Electrons, from 0.5MeV to 20MeV; Protons, from
9.5MeV to 248MeV, and after the 248MeV; and Helium particles, from
38MeV to 980MeV and further. Also, a penetration intensity relative to
14
4.1 Environmental Parameters
the Earth surface position was provided. The results suggest critical ra-
diation levels for LEO missions in these particular regions and provide a
reference value for estimations in this work. Figure 4.3 is a sample of
the measurements, for low energy electrons in logarithmic scale, performed
by the PROBA-V mission and shows qualitatively the regions herein de-
scribed, intending to only provide a simplified visualization.
Figure 4.3: Simplified preview of the radiation vulnerable regions.
Source: V. Pierrard et al., 2016
Thermal and Mechanical Analysis
A comprehensive thermal analysis for FloripaSat-1 mission was carried

out by the development members, which characterize the environmental
temperatures for the satellite during its orbit [23]. In summary, the re-
sults lead to the estimated range of -25 to 60 degrees Celsius as maximum
variation in several orbital conditions. These values are predicted in the
surface of the solar panels, then it is expected less variation inside the
satellite. For the payload, the component must be operational in these
ranges, which COTS commercial or industrial grades are capable to meet
the requirements, avoiding the use of specific components ratings, such as
space or even military.
Moreover, concerning mechanical stresses, especially during the launch
and deployment, the payload must maintain its physical integrity for the
entire mission operation. Then, the design, assembly and integration adopt
the FloripaSat-2 guidelines that are based in the lessons learned from the
predecessor mission (FloripaSat-1). These procedures and design consider-
15
ations are summarized throughout the document, in the design robustness

considerations or in qualification tests planning. Therefore, using the Flori-
paSat platform methodology, the developed payload should work properly,
since mechanically the board and attachment scheme is similar to the other
satellite modules. Also, to ensure this statement, the payload will pass
through the entire FloripaSat-2 integration and qualification process per-
formed by their experienced members.
4.2 Memory Experiment Analysis

Regarding the memory experiments, these three SDRAM chips were char-
acterized in test facilities by the laboratory group [8] and one of the mem-
ories by other groups at the California Institute of Technology in dif-
ferent studies [17] and [18]. The SDRAM memory chips used are pro-
duced by the company Integrated Silicon Solution Inc. (ISSI) and use
different manufacture nodes: 110 nm for IS42S16320B [24], 72 nm for
IS42S16320D [25], and 63 nm for IS42S16320F [26]. The memories are
Single Data Rate (SDR) SDRAMs, with 536,870,912 bits organized in four
banks with 8192 rows and 1024 columns of 16 bits. The maximum operat-
ing frequency is 143 MHz, with a 3.3 V input supply voltage, and packaged
in 54-pin TSOP-II packages. Figure 4.4 shows the memory internal struc-
ture.
Figure 4.4: Inside view of the SDRAM memory chip (IS42S16320F).
Source: D. Söderström et al., RADECS, 2019
16
4.3 Payload Specification
4.3 Payload Specification

The payload specification is subdivided in four categories: payload, gen-
eral payload requirements; environment, reliability requirements related to
environmental parameters; performance, capability and features require-
ments; and operation, behavioral requirements.
Payload
REQ-PAY-000 The payload shall be compliant with the CubeSat standard

and general restrictions.
REQ-PAY-010 The payload must be compatible with the FloriapaSat-II mis-
sion.
REQ-PAY-020 The system shall be compatible with the FloriapaSat-II OBDH
DaughterBoard standard.
REQ-PAY-030 The system must have a communication interface with the
OBDH module through the DaughterBoard connector.
REQ-PAY-040 The payload must include three different SDR SDRAM mem-
ories.
REQ-PAY-050 The payload must convert specific voltage levels for its sub-
system from the provided OBDH power supply.
REQ-PAY-060 The OBDH module must be able to shutdown the payload
without turning down the power supply channel.
REQ-PAY-070 The system must adopt strategies to reduce power consump-
tion.
Environment
REQ-ENV-000 The payload components shall be selected in order to reduce

the harsh space environment effects.
REQ-ENV-010 The payload shall be designed to minimize the radiation in-
fluence over the components other than the memories.
REQ-ENV-020 The payload must be resilient to the temperature variations
and vacuum faced on the mission orbit.
REQ-ENV-030 The board mechanical attachment shall be resilient to the vi-
brations and stresses during the launch and deployment.
REQ-ENV-040 The PCB solder mask and components soldering must be in
compliance with space applications.
Performance
17
REQ-PER-000 The memory controller must be able to operate in the memo-

ries frequency ranges.
REQ-PER-010 The memory refresh rates should attend the specifications.
REQ-PER-020 The system controller must operate in frequencies similar to
the memories.
REQ-PER-030 The communication interfaces shall attend the OBDH perfor-
mance requirements.
Operation
REQ-OPE-000 The system must have two operation modes: experiment and
health monitor.
REQ-OPE-010 When in experiment mode, the system must perform memory
test operations and send results continuously.
REQ-OPE-020 When in monitor mode, the system must execute essential
memory tests, send status and reduce the power consumption.
REQ-OPE-030 The OBDH module must be able to manage the operation
modes.
REQ-OPE-040 The OBDH module must be able to request and schedule com-
mands through a communication interface.
REQ-OPE-050 The OBDH module must be able to receive data and logs
through a communication interface.
REQ-OPE-060 The payload must have a memory controller module to manage
the SDRAM memories.
REQ-OPE-070 The system shall perform different tests in the SDRAM mem-
ories.
REQ-OPE-080 The system shall synchronize execution time with the OBDH.
REQ-OPE-090 The system must count the elapsed time to provide reference
for the radiation events data.
REQ-OPE-100 The payload must use a watchdog timer to prevent execution
faults.
These requirements were important to guide the architecture definition
and the elaboration of tests. Considering the scope of this work, the pay-
load has a lean list of requirements, which provide the minimal conditions
to execute the project. In section 6, the main requirements are cited for
the tests that exercise their validation.
18
5 Development
The following topics will cover the entire payload development process in
details, focusing on the architecture, methods, and technologies, besides
the actual development steps and results. Some organizational and work
activities aspects are shortly mentioned or placed as annexes, unless es-
sential for the comprehension of the measures and approaches adopted
throughout the development, since the focus of this work is the technolog-
ical challenges and analysis, and the architectural proposals. Figure 5.1
shows the payload board (Flight Model) developed during this work. Also,
since the source code, source FPGA project, scripts, and hardware files are
very extensive to include as annexes, the entire project is available in a
licensed open-source format in a repository at GitHub [27]4 .
Figure 5.1: Preview of the developed payload.
Source: Author
5.1 System Overview

In order to accomplish the payload requirements, the development pro-
cess reached different stages of completion: prototype phase, engineering
model and flight model. These categories are a simplification of the system
engineering phases definition, which generally define a deliverable and a
associated review. For this reason, an overview of each stage of the system
4
All parts of the project were developed by the author with guidance of supervisors and colleagues,
except by the preliminary radiation experiment in the engineering model, which was performed by the
LIRMM colleagues.
19
is provided to ease the understanding of the project evolution and an itera-

tive architectural conception. Table 5.1 summarizes the delivered features
in each phase, the development period, and overall standards compliance.
Table 5.1: Project phase progress according to the specifications.
Features and standards Prototype Engineering Model Flight Model

(1 month) (5 months) (6 months)
System control and management x x x
Reliable radiation controller x x x
Radiation hardened board x x
Single SDRAM memory access x x x
Multiple SDRAM memory access x x
Static memory test algorithms x x
Dynamic memory test algorithms x
Frequency test algorithms
Refresh rate test algorithms
UART communication interface x x x
SPI communication interface x x
I2C communication interface
CAN communication interface
Watchdog timer protection x x
Low power mode operation x x
FSP protocol implemented x x
Debug logging routines x x x
Experiment routines x x
Communication routines x x
System housekeeping routines x x
Reliable FreeRTOS instance x x
Firmware reliability review x x
Hardware reliability review x
Source: Author.
5.1.1 Prototype
During the prototyping phase, the base architecture and components of

the design were selected to fulfill the payload requirements. The SDRAM
memories controller was the first aspect to be defined due to its importance
and objective inside the payload. This definition lead for a FPGA oriented
architecture, which could provide the necessary design flexibility and port
connections, high frequencies support, and parallel execution during mem-
ory operations. Then, among different technologies and vendor options,
the SmartFusion2 family from Microsemi emerged as a good trade-off be-
tween performance, power consumption, and reliability. Also, these devices
20
5.1 System Overview
have an embedded ARM Cortex-M3 processor, several useful on-chip pe-

ripherals and the advantage of being flash based, which provides a better
radiation resilience [20] [21] [28].
Then, in order to test and validate the first design concepts, the next
stage was selecting a suitable development board. Among the different op-
tions provided for this device family, the SMF2000 development kit (from
Trenz Electronic) were the best solution for the prototype conception. This
board standout due to its low price, simple architecture, and all the neces-
sary features, including a SDR SDRAM memory for the first design assess-
ments. Figure 5.2 presents the board and its components highlighted: in
yellow, a serial to USB converter used to format the FPGA bitstream, de-
bug, and send log messages; in orange, the 64Mb (or 8MB) SDR SDRAM;
and in red, the M2S010 SoC FPGA chip.
Figure 5.2: Development board used during the prototype phase.
Source: Trenz Electronic, 2021
Regarding the delivered features of the prototype, shown in Table 5.1,

the base SoC design solution and the minimal system firmware were de-
veloped to attend the most critical aspects of payload, which includes the
memories control and tests, simple communication routines, and usage of
the internal non-volatile memory to store the firmware sources. Since the
FPGA is flash based, a non-volatile memory, the bitstream is retained
indefinitely and any formatting routine is necessary after system resets.
5.1.2 Engineering Model
After the prototyping phase, the engineering model started to be developed

considering the previous phase review outputs. Since the first approach was
using a development kit, the major design revisions focus on creating the
hardware platform, defining the FPGA SoC architecture and developing
the embedded software. Then, the first iteration of hardware development
21
was based on the SMF2000 and to reduce further changes5 , this version
intended to be as close as possible of the flight model. Interfaces, con-
nectors and the memories were the major changes from the development
kit, besides the FPGA assignments and the board shape itself. Figure 5.3
presents a simplified architecture diagram of the engineering model, which
includes the hardware and SoC FPGA modules.
Figure 5.3: Simplified engineering model architecture.
Source: Author
In order to visualize the integration with the FloripaSat-2 OBDH, some

conceptual assemblies were performed during the development. Figure 5.4
presents one of these integration setups and provide a visual understand-
ing of both modules, their mechanical connection and electrical interface
through the contact connector.
In summary, the engineering model review revealed that the hardware
design and the SoC FPGA solution are adequate to the payload mission
and requirements as a flight version. The firmware, showing the basic
operation and experiments, presented satisfactory overall stability, but it
was decided to refactor some routines, perform more specific tests, and
improve the reliability and redundancy of some modules.
5
Despite the engineering model providing a good opportunity for a board focused on ground experi-
ments, with more resources and isolation for the experiment memories section, the platform was developed
to minimize changes for the flight model due to budget restrictions.
22
5.1 System Overview
Figure 5.4: Conceptual payload model integrated with the FloripaSat-2 OBDH.
Source: Author
5.1.3 Flight Model
Regarding the flight qualified model, the major changes from the engi-
neering version were the system firmware and the experiment algorithms.
These modifications were important to improve the experiment execution
and provide better results. Also, the integration tests revealed some weak
points and non-reliable management routine implementations that might
led to critical failures. Then, in order to solve these issues, the firmware
was updated, tested and the design reviewed.
Figure 5.5 presents the payload attached to the FloripaSat-2 OBDH
during the integration. More details about the integration setup and re-
sults are described in further topics. Also, the final design architecture is
presented in details in the following sections.
Figure 5.5: Payload model integrated with FloripaSat-2 OBDH.
Source: Author
23
5.2 SoC FPGA Architecture

The payload core subsystem is the SoC FPGA, which provides the system
control and management due to the embedded microprocessor, memory
controller, communication interfaces and main peripherals. The device
comprehends the main functionalities of the payload system, then using a
radiation resilient device6 improves the overall dependability and permits
the analysis of the memory faults within the absence of controller errors [20]
[21] [28]. Also, the SmartFusion2 family is suitable for critical applications
due to its intrinsic robustness, high density die, high-performance, and
availability of a wide variety of validated peripherals. These devices have
a heritage of utilization in space applications and demonstrates satisfac-
tory overall performance and reliability [29]. Figure 5.6 provide a internal
physical architecture overview of the SmartFusion2 devices. The following
sections describe the SoC system implemented inside the M2S010, part of
the SmartFusion2 family.
Figure 5.6: FPGA die overview.
Source: Microsemi, 2020.
6
The device is not radiation tolerant, but offers some reliability features and the manufacturer provides
some valuable radiation performance reports for SEE (mainly SEL, SEU, and SEFI [21]).
24
5.2.1 Design Overview
The SoC architecture embedded in the chip has several features and allows
each subsystem to be enabled or disabled in the design, in order to reduce
the power consumption. The device is subdivided in different functional
sectors, where the main part for this project are the Microcontroller Sub-
system (MSS), with a fixed implementation, and the FPGA Fabric, where
the user modules and configurations are implemented. Both parts are em-
ployed to create a flexible system attending the required capabilities and
define the core design: controller, using the ARM Cortex-M3 processor;
Soft Memory Controller(SMC) for the SDRAM management, in the FPGA
Fabric section; serial communication (UART 0, SPI 0, I2C 0); Watchdog
timer, for system protection; timers, for timing and synchronization; GPIO
ports; Embedded Non-Volatile Memory (eNVM 0) for code sources stor-
age; Embedded Volatile Memory (eSRAM 0) for code execution and tem-
porary data storage; and debug, using the System Controller for JTAG
interface. The following topics details each subsystem characteristics and
operation. Also, Figure 5.7 presents a simplified diagram of the built-in
internal available modules.
Microprocessor
In the SoC architecture, the processing unit is a hard core instance

of an ARM Cortex-M3 microprocessor. The unit has a low-power con-
sumption design and intend to accomplish deeply embedded applications
requirements. This processor consists in a 32-bit RISC architecture with
3-stage pipeline that provide enough processing performance for the pay-
load routines and algorithms. In order to provide the utility features for
this device, the SoC design includes a set of peripherals, which combine
communication, timers, system memories, watchdog and debug modules.
When disabled, these subsystems are hold in low power mode and provide
customization during the development that contribute for the feasibility in
power constrained applications. Also, the system uses the ARM Advanced
Microcontroller Bus Architecture (AMBA) as interface for the peripherals
and the FPGA fabric devices, employing the Advanced High-performance
Bus (AHB) protocol in the communications.
Memory Controller
In order to manage the SDRAM memories, a controller instantiated in
25
Figure 5.7: Internal architecture diagram overview.
the FPGA fabric is used for the external interface with these devices. In
this architecture, the controller is shared among the memories to simplify
the hardware design (only one shared interface instead of three times the
number of signals) and provide similar operational characteristics to iso-
late the memories from other effects. A strategy was adopted to optimize
the experiment execution that consists of a round Robin cyclic algorithm.
The method implementation is described in further sections, but the main
objective is to keep experiments in the memories running simultaneously
with this shared controller scheme. Also, due to similar internal logical
architecture, despite the manufacturing differences, the memories are com-
patible in operation and constraints. Figure 5.8 describes the interfaces
used for the controller from the processor until the external interface. The
processor, a master in the AHB bus, requests data operations for the DDR
Bridge that redirect these commands for the memory controller, using a
26
AHB to AXI interface. Then, the controller, besides the regular manage-
ment operations, handles the communication and control signals through
the MSIO ports to the actual memory. Since the SDRAM chips are con-
nected in parallel in the same MSIO ports, the controller uses chip select
signals to enable the correct device.
Figure 5.8: Memory controller interfaces overview.
This controller is part of the catalog collection provided by the SoC

FPGA vendor, which provides several ported IP Cores for the fabric im-
plementation. The used core is designed for SDR SDRAM memories and
adapted to be connected to an Advanced extensible Interface (AXI). Fig-
ure 5.9 shows a simplified diagram of this IP core. In summary, this module
receive operation requests through the AXI bus and the internal controller
handles this demands, generating the formatted operation frame for the ac-
tual memory controller and handling its responses for the requester. How-
ever, since the MSS subsystem (the requester) architecture provide an AHB
interface, a converter is required to properly handle the protocol exchange
for an AXI bus. Also, this module is provided in the vendor catalog and
do not require external control, besides the reset signal.
The CoreSDR is the controller that manage the memory communication,
generating the control signal within the time constraints. It receives the
operation requests, data length and addresses from the AXI controller and
the data from the write buffer in case of a write operation. The input
27
Figure 5.9: Core SDR wrapped for an AXI interface architecture.
address is structure as described in Figure 5.10. This scheme is important

to determine which memory should be accessed in relation to the input
address, where the three most significant bits are decoded in up to eight
chip selects and the others bits to set the column, row and bank. When
an encoded chip select bit changes, it means that the address space of that
memory ends and the next starts. This scheme allows the usage of up
to eight memories without the need of additional controllers or external
interfaces.
Figure 5.10: Core SDR Address scheme overview.
Figure 5.11 shows the internal modules of the controller and the corre-
sponding signals. The output signals are directly connected to the SDRAM
memories: RAS, CAS and WE determine the requested commands; SA
and BA set the target addresses; DQM is a mask for bytes within a word;
CKE is used to enable the clock in the memory; CS activate the selected
memory; DQ is used for input and output data; and OE is used to enable
28
the tri-state in DQ signals. The refresh control unit is used to send peri-
odic refresh commands, due to the SDRAM technology requirements, and
the address generation module convert the input addresses to the memory
access format. The rest of the subsystems handles other functionalities:
initialization, resets and timing constraints. Regarding the last item, the
three memories have compatible time requirements and latency character-
istics at the payload operation frequency, which were manually configured
to attend the datasheet specifications.
Figure 5.11: Core SDR architecture diagram overview.
Embedded Memories
In order to store the code and data, the SoC solution includes two dif-
ferent types of memories: embedded Non-Volatile Memory (eNVM), using
the flash technology; and the embedded Static RAM (eSRAM). For the
payload design, the eNVM is dedicated for code storage, constants and
user data if correctly allocated, which provides to the system all required
instructions during execution and reboots. Also, since the eNVM is a flash
memory, the radiation effects are reduced due to its intrinsic resilience.
The eSRAM is responsible for the runtime environment, providing a faster
memory for variables, stack, heap, and other system memory abstractions.
Since the experiment memories (SDRAM) could generate many bytes of
errors, in case of block failures or high radiation exposures, there is a limit
29
for the experiment data. This approach guarantee that the system tasks
will be properly executed without memory issues due to capacity, since
this data is stored in a bounded manner. In this scenario, the worst case is
achieving the eSRAM memory capacity and overwriting the older results.
The eNVM has a capacity of 256kBytes that provides a secure size for
all the system applications without limitation issues. The eSRAM has
two modules with 32kBytes each when SECDED-ON and 40kBytes each
when SECDED-OFF. The Single Error Correction, Double Error Detection
(SECDED), a extension of the Hamming code, is a technique to improve
the data storage dependability, in this case on the eSRAM that is very
susceptible to the radiation effects. Since this algorithm is a built-in fea-
ture of the SoC FPGA and there is a reasonable storage capacity margin,
the eSRAM is used with the SECDED enabled. Figure 5.12 describe the
eSRAM scheme in both cases. Then, using this approach, it is possible
to avoid potential problems with the system memories, allowing the pay-
load to properly evaluate the radiation effects on the target devices, the
SDRAMs.
Figure 5.12: eSRAM memory scheme.
Serial Interfaces and IO Ports
The Microsemi FPGA SoC solution provides several peripherals in the

MSS subsystem. For this payload, it is used different serial communication
protocols (SPI, I2C, CAN and UART) and GPIOs to provide flexibility and
redundancy. The SPI protocol, as slave, is used exclusively for communica-
tion with the FloripaSat-2 OBDH. In this interface is used the FloripaSat
Protocol (FSP), in order to attend the OBDH requirements and increase
the communication reliability. Also, as redundant channels, the I2C (as
30
slave) and CAN could be used for the same interface. This design allows
compatibility with further missions of the FloripaSat core, since the pay-
load could be used as a health monitor for radiation damage. Moreover, a
UART interface is provided for system logging, which ease the development
and debug processes, and a JTAG for the FPGA programming. Also, 20
GPIOs are available for parallel protocols, hardware tests or debugging, 6
IOs for the latch-up monitors and two pins for the FPGA live probes, used
for system monitoring during debug.
These interfaces are available in different connectors, models and lo-
cations depending on priority and utilization: SPI, I2C and 4 GPIOs on
the contact connector (main interface with the OBDH); CAN, JTAG and
14 GPIOs on dedicated connectors; UART, JTAG, SPI, live probes and 2
GPIOs on dedicated connectors only available in the engineering model for
testing purposes due to space constraints; and the 6 IOs, directly connected
to the latch-up connectors.
Watchdog Timer, Interruptions and Timers
The internal watchdog timer provide a failure recovery feature for the
payload system, without the necessity of an external device. This mecha-
nism protects the payload against software errors by resetting the device
and restoring the system execution from boot. Moreover, the payload
uses the available timers to synchronize the peripherals execution and trig-
ger system actions, alongside the interruption handler that manages these
events.
31
5.3 Firmware Architecture

The CubeSat standard, although restrictive concerning definitions of ex-
ternal mechanical and electrical interfaces, integration guidelines and ma-
terials utilization, it does not restrain the implementation of the internal
subsystems. Regarding the firmware architecture a considerable freedom
allows the developers to propose their own standards using approaches and
patterns from different application niches. For instance, companies tend to
introduce a proprietary architecture in their platforms, creating a tailored
environment of modules and development tools [30] [31] [32]. Moreover,
since the CubeSat missions have a substantial contribution from the aca-
demic environment, a wide range of techniques and models are employed
intending to attend the application requirements and explore novel strate-
gies [33] [6].
Despite these differences, the projects share principles and patterns in-
herent of critical applications, and more specifically, space niche that im-
ply focusing on the same aspects: reliability, harsh environment mitigation
techniques, redundancy, and predictability. Then, regarding the software
development, using these concerns to design failure-aware systems generally
lead to sophisticated and robust architectures, which increase the mission
success probability. Considering the scope of this project, the following
sections detail the aspects that guided the payload firmware development,
describe the behavioral operation of each module and include the subsys-
tems design.
5.3.1 Design Guidelines
The payload software follows guidelines presented in [34], where the flight
software is proposed following good design patters and practices, modu-
larity, and reliability. Despite that, the framework considers a long-term
reusability and presents an approach for the satellite OBC, with many more
tasks and responsibilities. Then, these principles are applied for this work
in a simplified context and key aspects are detailed in the following topics.
Failure Protection Strategies
The payload firmware is designed to decrease failures due to system

malfunctions and environmental conditions. Some of these strategies are
periodic system resets, watchdog timer, hardware check routines, default
parameter values and error correction algorithms in the system memories
32
and communication interfaces. For instance, the embedded SRAM memo-

ries, designated to store the experiment results, use the Single Error Cor-
rection, Double Error Detection (SECDED), a extension of the Hamming
code. Also, in the communication with the FloripaSat-2 OBDH, a Cyclic
Redundancy Check (CRC) algorithm, an error-detecting code used to de-
tect accidental changes to raw data, is applied inside the communication
interface protocol.
Moreover, the payload firmware in based on an operating system tar-
geted to embedded systems, which improves the overall reliability since
the platform has inheritance of several projects in different applications,
including the space sector. Then, using this framework to develop the pay-
load firmware, the system failures are mitigated and the architecture more
qualified to the application.
Internal and External Synchronization
The system synchronization within internal constraints and with exter-

nal devices is a challenge since the payload is intended to operate controlled
by the OBDH and, meanwhile, perform several functions within certain
time and priority limitations. Then, using the operating system frame-
work, this requirement is accomplished using queues, tasks, semaphores,
and interruption handlers, which provides tools to accommodate the dif-
ferent constraints in a deterministic fashion. In summary, each task has an
execution rate, priority and optional parameters (semaphores, initial delays
and group events) that are predictably handled by the system scheduler.
Besides this execution scheme, data should be transferred between these
task without the necessity to be immediately handled, which is the fun-
damental strategy of the data synchronization. Also, since the system
operation is controlled by the OBDH (slave mode), it is necessary an inter-
ruption handler for communications, which is non-deterministic and could
cause issues. Then, to avoid this problem, a binary semaphore is used to
create a link between the interruption occurrence and a handler task, which
transforms the operation deterministic in terms of execution alongside the
rest of the system tasks.
Moreover, the communication with the OBDH has synchronization strate-
gies due to the FloripaSat Protocol (FSP), which defines a communication
standard between both modules. This protocol uses handshake operations,
acknowledge responses and set a command list, besides error-detecting rou-
tines to ensure correct communication. These strategies and features are
33
detailed in depth throughout the following sections, reveling the actual

architecture, operation mechanisms, and consequences.
Abstraction Layers
The firmware structure is based on abstraction layers, which creates a

separation between layers and allow a development oriented to the appli-
cation itself instead of the hardware details in that feature. Also, this
strategy increase the firmware readability, flexibility, organization, and
maintenance, due to the implementation independence from distant lay-
ers and abstraction of unnecessary information. Figure 5.13 presents this
layers and their hierarchy. At the bottom, it is represented the lowest level,
the SoC implementation, then the first abstractions, called hardware ab-
straction layers due to handling with specific operation related with the
processor and peripherals. At the upper levels, there are the application
layers that use a high-level description approach for the implementation of
the payload system functionalities and operations.
Figure 5.13: System abstraction layers diagram.
Source: Author.
The firmware architecture, as herein described, use an embedded operat-

ing system that is widely used in commercial products. The FreeRTOS
is a Real-Time Operating System (RTOS) for microcontrollers and small
microprocessors with proven robustness, tiny footprint, and wide device
support. Then, in order to use a similar architecture as the FloripaSat-2
34
OBDH, share libraries, and ease the development process, the FreeRTOS
was the most feasible platform for this project, besides an official port for
the ARM Cortex-M3 microprocessor inside the SoC FPGA. This firmware
development approach lead to the conception of functionalities translated
into operating system tasks and synchronization schemes in queues and
semaphores. In summary, the firmware is designed using the operating
system features and structure.
Regarding the system functionality, Figure 5.14 describes a simplified
execution diagram, presenting the main experiment functions and their se-
quence. The housekeeping and system functions are omitted to evidence
the major payload purpose, the experiment execution itself. After power-
on and internal setup, the payload receives a command from the OBDH,
prepares the experiment parameters and enables the experiment execution.
Then, this data is stored in the embedded SRAM for later retrieve when
a OBDH data request occurs. This loop summarizes the experiment ap-
plication and the payload purpose, evaluate the SDRAM memories in the
harsh environment.
Figure 5.14: Simplified system execution flow diagram.
Source: Author.
These functionalities are translated in tasks, queues, semaphores, and

interrupt handlers, which are represented in Figure 5.15. Also, some pa-
rameters are presented (priority, rate, periodicity and depth) that are de-
tailed and justified in the following topics.
Experiment Routines
35
Figure 5.15: System architecture diagram.
Source: Author.
The experiment is executed through two dependent and periodic tasks:

”experiment manager task” and ”experiment runner task”. The first is re-
sponsible to handle the commands received through the communication,
constantly check the latch-up monitors, and coordinate the system queues.
The second task coordinate the experiment execution and save the gener-
ated experiment data results. Concerning the execution flow, the manager
task has a higher priority than the runner one, thereby executing despite
the experiment cycle accomplished the end. This design would lead to is-
sues if a synchronization mechanism did not coordinate the execution of
one task accordingly to the other. Then, in order to fulfill this need, a
queue system was designed to trigger some states that are executed in key
moments, for instance: reading the memory to restore the experiment re-
36
sults, changing the execution configuration parameters, and many other

functionalities.
There are two queues directly used in the experiment routine and three
indirectly, which transfer data, configuration parameters, and status. The
two direct queues are used for receiving the configuration from the manager
to the runner task, and sending the position and size of the experiment
data stored in the dedicated memory sector to the manager task. The other
queues are used by the manager and communication tasks for inputting the
commands from the OBC, and outputting the data and status information
to the OBC.
Figure 5.16 summarizes the experiment execution flow, presenting from
the communication with On-Board Computer (OBC) to the execution of
the memory test algorithms. It starts with the command received from
OBC, process the execution parameters, run the test algorithms, store
data in the dedicated memory, send data status for further retrieving, read
this data, and finishes sending it to the OBC. This sequence is a simplified
overview and support the visualization of the routine, but it should be
analysed as two tasks not necessarily contiguous in time and using queues
to trigger sequential events.
Housekeeping Routines
The housekeeping routines are responsible to initialize and maintain the

system properly configured and operational. There is an aperiodic task
referred to as ”startup” that performs the system boot once after power up,
in other words, the initialization of all peripherals, interfaces, and devices.
Also, there is a dedicated periodic task that ensures constant notification
of properly operation for the watchdog timer and another one with the
lowest priority for other periodic non essential functions (e.g., blink LED).
Communication Routines
The communication routines are handled using an aperiodic task and

interruptions (one for each physical protocol). The task execution trig-
ger is associated with the interruption since the payload is a slave in the
communication from the perspective of the OBC. Then, to ensure that
the communication is correctly attended, the task has the highest priority.
This strategy is adopted to accomplish both requirements, attend commu-
nication requests with low latency and use the payload firmware formal
37
Figure 5.16: Experiment architecture diagram.
EXPERIMENT ARCHITECTURE
OBC BOARD Queues packages:

SPI/I2C INTERFACES
obc_command_package_t
uint8_t operation_mode
uint16_t execution_config
Commands Data/State
uint32_t obc_sys_time
Rate: OBC INTERFACE TASK obc_data_package_t

Aperiodic uint32_t time_stamp
(after ISR) Get package Send package
uint8_t device
uint8_t memory_frequency
Priority: uint16_t refresh_rate
Higher Decode(FSP) Encode(FSP) uint8_t algorithm
uint16_t iteration
uint32_t address
OBC OBC uint32_t data
command data/state uint16_t error
queue queue
sys_state_package_t
uint32_t time_stamp
Rate: EXPERIMENT MANAGER TASK uint8_t operation_mode
Periodic uint16_t execution_config
(500ms) Process command Send package uint8_t error_count
uint16_t error_code
Priority:
Check latch-up Read eSRAM
Medium experiment_command_package_t
uint16_t execution_config
Send command Receive state
experiment_state_package_t
uint16_t package_id
Experiment uint32_t address
Experiment
command uint32_t length
state queue
queue
Rate: EXPERIMENT RUNNER TASK Algorithm tests:

Periodic Static read/write and Dynamic Loop C-
(2000ms) Run tests Send package
Store results Others tests:
Priority: in eSRAM Frequency and refresh rate variations
Lower
Source: Author.
application structure (i.e., the operating system tasks). Also, this method
prevents conflicts between the scheduler and manually configured interrup-
tions, and allows the use of the operating system features safely. Figure 5.17
presents the scheme adopted to receive and process the communication in-
teractions. Also, Figure 5.16 describes the interface of the communication
task with the experiments routines using queues for synchronization.
Also, the communication uses the FloripaSat Protocol (FSP), developed
with the purpose of standardizing the communication between the Flori-
paSat service modules. This protocol does not specify the physical layer, so
it can be used, for instance, over SPI, I2C, or UART. For the payload, the
SPI interface is used as the physical layer and a FSP address was provided.
The package fields defined by the FSP are shown in Table 5.2. The n
value is defined by the field ”Length” and can assume values between 0 and
248. Therefore, the package total size can reach from 7 to 255 bytes. In
order to grant the correctness of the transmitted data, a Cyclic Redundancy
Check is made. The standard used is CRC-16-CCITT (initial value = 0
38
Figure 5.17: Communication interrupt and task architecture diagram.
Source: FreeRTOS, 2020
and polynomial = 0x1021). All the FSP’s package fields, except the SOD,
are used to generate the CRC value.
Field Description Length (Bytes)

SOD Start of data (always 0x7E) 1
SRC Source address 1
DST Destination address 1
Length Length of the package payload 1
Type Type of package 1
Payload Data of the package n
CRC CRC-16-CCITT bytes 2
Table 5.2: FSPv0.2 package fields.
The FloripaSat team defined module addresses for each board in the
system, including the payload referred to as ”HARSH”. Table 5.3 presents
this list.
Module Address
EPS 1
TTC 2
OBDH 3
HARSH 4
Table 5.3: FSPv0.2 adresses.
39
Also, the protocol defines package types, as expressed in Table 5.4, and
allowed commands, defined in Table 5.5
Package Type Value

Data without ACK 1
Data with ACK 2
Command without ACK 3
Command with ACK 4
ACK 5
NACK 6
Table 5.4: FSPv0.2 package types.
Command Value
NOP 1
Send Data 2
Request RF Mutex 3
Shutdown 4
Table 5.5: FSPv0.2 commands.
Debug and Logging Routines
In order to perform debug sessions and execute integration tests, there

is a logging system to provide useful feedback during the development.
The routines use a serial interface (UART) to output relevant steps and
notify critical failures, which are easily read through a serial monitor (e.g.,
PuTTY or equivalent). These logs are inserted in key positions, using
status flags to select between appropriate messages.
5.3.3 Memory Fault Detection Algorithms
Memory fault detection algorithms are used to evaluate the three memories
under the harsh radiation conditions. The implemented algorithms use
static, based on writes and reads executed once per address, and dynamic
analysis, in which the operations are continuously executed several times
for each memory address.
The static analysis consists of write operations with a fixed data pattern
(e.g., solid ‘0’, solid ‘1’, or checkerboard patterns). After a specified time,
defined by the OBC or a default 10-minute period, the memory is read
to detect any difference from the previously written pattern. In (1), it
40
is presented a simplified schematic view of the algorithm [35], where the

arrow indicates the addressing order (‘↑’ up or ‘↓’ down), ‘w’ (write) and
‘r’ (read) indicates the operation, and the following number indicates the
data background.
↓ (w0);
↓ (r0); (1)
The dynamic analysis performs continuous read and write operations.

This algorithm allows the detection of functional faults and emulates a
more realistic behaviour [36, 37]. For this purpose, the March C- algorithm
(2) was applied. Note that each element enclosed by the parenthesis is
applied to each memory address.
↑ (w0);
(2)
{↑ (r0, w1); ↑ (r1, w0); ↓ (r0, w1); ↓ (r1, w0); ↑ (r0); }
41
5.4 Hardware Architecture

The payload hardware consists of a 6-layer PCB, using the FloripaSat-2
OBDH DaughterBoard standard and following simplified space application
design guidelines. In order to enumerate this patterns and constraints, the
following section describes the applied techniques and particularities of the
payload design. Then, each developed modules receives a brief architectural
and functional description.
5.4.1 Design Guidelines
During the board development, regarding the design guidelines, the rules
specified in the ESA normative for space qualified printed circuit boards,
ECSS-Q-ST-70-12C [10], were used as a reference. However, since this stan-
dard embraces the space environment characteristics and high reliability,
following these rules would require an extensive study and analysis, besides
the higher manufacturing prices due to specific procedures and materials.
Then, in order to conciliate the board requirements for dependability and
feasibility in terms of development time and funding, this payload follows
rules applied in the master student Cezar Rigo thesis [11]. These rules are
summarized in Table 5.6 and some observations are noted concerning the
compliance of these rules in the payload project design.
Table 5.6: Summary of ESA guidelines.
Rule Compliance
The distribution of layers and their thickness must Full
be symmetrical. This is done to prevent the board
from deforming or distorting, especially when under
intense vibration.
The copper thickness on both sides of a laminate Full
must be the same, except in the external board lay-
ers.
The outer and inner layers must use basic copper Full
thickness of 70 µm, 35 µm or 17 µm. This is neces-
sary for the manufacturing process.
42
Table 5.6 – Continued from previous page

Rule Compliance
The distribution of copper within a layer must be Full
homogeneous. This ensures homogeneous pressure
during lamination, avoiding empty spaces, cracks, or
compression of the glass. Mainly needed when using
70 µm thickness.
Tracks should not be routed in layers of copper Full
plane. This is done to avoid obstacles for the high-
frequency return currents.
The projected insulation distance between two layers Full
must be at least 100 µm. This avoids risk of reduced
electrical insulation.
The fabricated thickness of a rigid epoxy PCB must Full
be ≤ 2.4 mm.
The number of copper layers for an epoxy PCB must Full
be ≤ 20.
The relationship between the thickness of the PCB Full
and the diameter of the via hole on a rigid PCB must
be ≤ 7.
For copper thickness 17 µm, no width of track or Full
track spacing and/or components must be ≤ 96 µm,
already including manufacturing tolerances.
7
Tracks should not be routed in external layers, given Partial
a higher vulnerability to disruption.
BGA component pads must be circular and with Full
teardrop.
8
Minimum distance between BGA pads should be None
1mm.
9
BGA component pads must be designed with via on None
the pad, being micro vias or filled vias.
7
Since no vias on pad were used due to the high cost, there are some tracks on outer layers.
8
The FPGA family used in this project only offer 0.8mm BGA pads, which is slightly lower than this
rule, but large enough to avoid common problems of very small BGA packages.
9
This technique was not used due to its high cost.
43

Rule Compliance
BGA footprint trails must be equidistant between Full
the pads. This increases the distance isolation.
Pads must be designed with teardrop reinforcement. Full
10
Non-functional pads should be kept on footprint. Partial
Annular ring must be at least 50 µm wide in internal Full
layers and 200 µm in external ones.
Copper planes larger than 10 cm2 must be made in Full
grid format, with 45 degree rotation. This creates
ventilation openings and moisture evaporation of the
inner layers.
The fabricated thickness of a rigid epoxy high- Full
frequency PCB must be ≤ 3 mm.
The number of copper layers for a rigid epoxy high- Full
frequency PCB must be ≤ 14.
Dielectric strength of the material must be greater Full
than 1000 Vrms/mm
11
For power distribution, a thickness of copper of 35 Partial
µm or more should be used.
Any conducting elements and copper islands should Full
be left isolated.
The temperature of the tracks must be less than 85 Full
degree Celsius.
12
Critical tracks should all be routed on one single Partial
layer.
13
Conductors in outer layers must be covered with Partial
polymeric film and not the solder mask.
10
Due to size limitations, some unused pads were removed, but restricted to the BGA components.
11
The power density of the payload is very low and have a distribution over planes, then thinner internal
planes were used.
12
Again due to size and cost (and consequently layers) limitations, critical tracks had to use 2 layers,
in which at least the care to route them in protected and referenced internal layers was taken.
13
The board was designed to use solder mask due to the difficulty of assembling components without
it. It is planned to use polymeric film before the flight integration.
44

Rule Compliance
Tracks with impedance control must be made in spe- Full
cific layers.
14
Vias should not be used on impedance controlled Partial
tracks, except for the connection with the compo-
nent pads.
Low-speed digital circuits must be separate from Full
high-speed digital circuits.
Grounding planes must be used in high-speed digital Full
applications.
High-speed signals must be routed above of uninter- Full
rupted power plans.
The location of the components must be such that Full
each solder connection can be visually inspected.
The designed test points must be separated compo- Full
nent pads.
The footprint fanout must be symmetrical. This is Full
done to prevent the component from moving in spe-
cific direction during the soldering process.
There must be a minimum distance of 0.25 mm be- Full
tween the pads and the vias. This is done to prevent
the solder being removed from the pad by the via,
during the soldering process.
The width of a track must be less than 1/3 of the Full
width of a pad. This prevents the track from remov-
ing heat from the pad during the soldering process.
15
The solder mask should not be used as it has prob- None
lems related to outgassing.
14
In the memories routing, mentioned in further sections, more than one layer was required due to the
quantity of signals and parallel connections.
15
As mentioned before, the board was designed for easier assembly due to size limitations. A bakeout
process is intended to be executed, mitigating the outgassing effects.
45
5.4.2 Preliminary Design Analysis
Layer Stackup Planning
The payload layers scheme was specified to attend the rules herein de-
scribed and to increase the feasibility of production, which uses convenient
dimensions for the target manufacturer. Since the engineering model do
not require space qualified boards, this scheme allowed to reduce the costs
and time by using a less controlled manufacturing processes. Figure 5.18
describe the payload stackup, including: layers, dimensions and character-
istics. In order to avoid tracks in the external layers, the strategy was to use
the middle ones for routing, permitting the shield properties of these ex-
ternal layers, and suitable power planes in the internal ones. Moreover, to
reduce crosstalk between the signal layers, they are orthogonal concerning
the routing preferential directions. Despite the external layers assigned for
ground reference, some parts are used to handle the external supply volt-
ages to prevent splitting the power plane since this leads to a degradation
of the expected current return paths. In summary, to correctly employ this
stackup, the internal layers must have the lowest impedance (short return
paths) and the external providing electromagnetic interference shielding to
internal signals.
Figure 5.18: Board stackup planning.
Source: Author.
Placement Planning
The components placement were defined using the external connectors

accessibility, considering the position in relation to the motherboard (the
FloripaSat-2 OBDH), and internal requirements. However, the positioning
46
of the FPGA device and memory chips were the major factor considered,
since the most critical routing is between these components. Also, to ease
the layout development process, the memories were symmetrically placed
in relation to the FPGA and uniformly distributed in the board. Fig-
ure 5.19 present the FPGA pin assignment to attend these requirements.
It is important to note that the DDRIO and MSIOD banks were not used
due to the maximum voltage levels allowed, 2.5 Volts. This assignment
strategy provides three groups of signals in different directions, which ease
the BGA fanout and tracks escape routes: memory control and address
signals; memory data signals; and general purpose inputs and outputs.
Figure 5.19: FPGA pinout usage.
Source: Author.
High-Speed Design Planning
The board component interfaces are in the edge (frequencies of 100MHz

and sharp signal transitions) of being considered as high-speed signals due
to the SDRAM memories. Then, even if a more complex approach is not
required for this work, some measures were considered in the payload de-
sign to avoid issues and bad performance. The most important strategy is
the properly grounding and power planes for return signals, which were de-
47
scribed in the stackup planning topic. Also, orthogonal and similar length
routing strategies were adopted to avoid crosstalking and latency issues in
the memory signals. The memories are placed symmetrically to provide an
easier and organized pattern for routing.
Figure 5.20 presents the signal layer used for tracing from the FPGA
to the memory chips. The highlighted tracks are the address signals that
are routed together to mitigate the length mismatch. The other signals are
grouped together depending on their purpose, control or data signals.
Figure 5.20: Top Mid-layer routing with focus on the memory address signals.
Source: Author.
Figure 5.21 shows a similar overview of the same address signals, but
presenting them in the other signal layer. The tracks are traced in the
shortest routes as feasible and provide the required parallel connections,
since the three memories share the same controller pins interface.
Figure 5.21: Bottom Mid-layer routing with focus on the memory address signals.
Source: Author.
48
The payload hardware essentially consists of a controller, to manage com-

munication and memories, and the SDRAM devices under experiment.
However, some auxiliary components and modules are necessary to handle
other tasks and fulfill the requirements, including: power converter, to sup-
ply the correct FPGA voltage; latch-up monitors, to prevent catastrophic
system failures and provide additional data for the experiment; debug sup-
port for power supply, logging, and programming; additional communica-
tion modules and connectors; and the motherboard interface connector.
Figure 5.22 presents the payload subsystems, internal connections and ex-
ternal interfaces, besides an internal overview of the SoC FPGA device
implemented architecture.
Figure 5.22: Hardware architecture overview.
Source: Author.
In addition to the summarized power supply architecture presented,

Figure 5.23 shows in more details the power line names, voltages, and
currents, besides their relation with the latch-up monitors.
Figure 5.24 presents a rendered view of the board top and bottom lay-
ers and Figure 5.25 shows the manufactured board. The following top-
ics describe the subsystems functionality and characteristics. Also, the
49
Figure 5.23: Power architecture overview.
Source: Author.
schematics are presented in Appendix A, alongside layers prints and other

information.
Figure 5.24: PCB 3D rendering overview.
Source: Author.
SoC FPGA Module
The FPGA device is a Ball Grid Array (BGA) component that re-
quire a fanout implementation and escape routes for the internal pins.
The adopted strategy for this work is the dog-bone pattern, which is
a widespread technique and attend the project necessities. Figure 5.26
50
Figure 5.25: PCB manufactured overview.
Source: Author.
presents the implemented pattern, escape route, and decoupling capacitors

placement using a top view of the board. Since several FPGA pins are not
used and the board placement favors the routing, this implementation only
required two signal layers and two power planes, which attend the payload
specification.
Figure 5.26: FPGA fanout dog-bone pattern and decoupling capacitors implementation.
Source: Author.
51
Memories Module
The memories module is composed of the three experiment memory

chips: IS42S16320B, IS42S16320D, and IS42S16320F. These devices are
512Mb (or 64MB) Single Data Rate (SDR) SDRAMs operating at 3.3V and
up to 143MHz in a 54-pin TSOP-II packaging. A SDR device means that it
can only read/write one time in a clock cycle, differing from its successors
Double-Data Rate (DDR) memories that perform two operations per cycle.
The selected parts configuration has a 16-bit data width and the industrial
grade qualification.
The target operation frequency is 100MHz using the other parameters in
the nominal indications, except for the refresh frequency (8K cycles every
64ms) that might be changed during some experiment tests. The electrical
topology is a parallel connection that shares the same controller interface.
This strategy was adopted since it saves the usage of several FPGA pins
and the used configuration is the same.
During the board design, the placement was selected to avoid any com-
ponent unrelated to the memories be located on their opposite side, with
exception of their decoupling capacitors, ensuring that they are as close as
possible of their power pins. Regarding the routing, the strategies employed
were described in subsubsection 5.4.2.
Communications and Debug Interfaces
The payload uses several communication interfaces distributed in dif-

ferent connectors according to the requirements or usage. There are six
available interfaces for different purposes: SPI, JTAG, UART, I2C, GPIOs,
and CAN. The SPI, JTAG, and UART are the main used communication
protocols and the rest were added for redundancy or additional non-critical
features. In the same scheme, there are six different connectors that share
some interfaces: 3 picoblade connectors, 2 debug headers, and 1 contact
connector. The debug headers are not used in the flight configuration due
to size limitations.
The picoblades are separately utilized for a CAN channel, a JTAG in-
terface, and the application GPIOs. The debug headers provide an easier
access for the UART logger, the application SPI, a JTAG interface, debug
GPIOs, and a external power supply input for debug. The contact con-
nector is the main interface with the OBC, which provides the application
SPI, an I2C for redundant communication, OBC power inputs, and the
52
control GPIOs.
This approach was adopted to improve the design flexibility and allow
the adaptation of the payload for different scenarios. For instance, it is
planned to perform ground experiments before the payload launch and
also the possibility of utilization in different satellite missions.
Power Module
The power subsystem is composed of a DC converter and a simple noise

filtering network. In the payload specification is stipulated that a 3.3V
power line is reserved for supplying the board, which should ensure current
limitation in case of a latch-up. This requirement is accomplished using
a anti latch-up circuitry and through the power converter protection as a
redundancy.
In order to supply the 1.2V for the FPGA chip, there is a DC switch-
ing power converter (TLV62565DBVR). This step-down converter operates
with high efficiency (above 85%), supplying up to 1.5A with overcurrent
and thermal protections. The selected part is a 5-Pin SOT-23 chip and
features an enable input.
The noise filtering network is the combination of four passive compo-
nents: two ferrite inductors and two ceramic capacitors. This circuit filters
the high frequency noises generated by the switching converter and received
from the OBC. Then, there are 1.2V power lines and power grounds before
and after the filter, which allows better power performance for the rest of
the circuits.
Latch-up Monitors
The latch-up circuitry consists of four monitors: one for the entire board
and three for individually controlling the experiment memories. The cir-
cuit is based on the LTC4361ITS8-1 device that provides the required
overcurrent protection through the management of a MOSFET transis-
tor (SI1416EDH-T1-GE3). The monitor uses a SOT-8 package and the
transistor chip a SOT-363-6 package, which offers a compact and efficient
solution. This system is completely independent of a controller for open-
ing the circuit in case of non nominal condition, but dependent for closing
again. The memory monitors are controlled by the SoC FPGA in case of
an event and the general monitor is only controlled by the OBC, since the
payload is completely turned off during this condition. The system also
53
provides a status pin that is used for detecting these events.
54
6 Results
The payload subsystems in hardware, firmware, and SoC FPGA were
tested during the development for later be integrated with the FloripaSat-2
OBDH. Since there were several simulations and tests to achieve enough
reliability for integration, this section focus on presenting the most critical
tests and their results. The test strategy focus on evaluating the lower level
elements and then validating the payload operation as a system. Before
the actual testing, some simulations were performed. The final assess-
ments consisted of a radiation test on the board and the actual integration
with the FloripaSat-2 platform. The requirements were used to assess the
readiness of the payload.
6.1 Simulations
In order to validate the first concepts, a simulation before the design syn-
thesis was performed intending to verify mainly the SDRAM controller.
The Microsemi development tool (Libero) has integration with ModelSim
(a simulation software) and provide the Bus Functional Model (BFM) so-
lution, which enables the emulation of the communication between MSS
and fabric logic through the AHB. Figure 6.1 demonstrates the simulation
flow using the BFM scripts. The user defines the commands in the BFM
script, then a compiler converts them to a vector file that is further used as
an input for the testbench system, which consists of an AHB master inter-
face, the memory controller, and the emulated memory. Since the memory
controller is part of the Microsemi catalog, the sources of this testbench
scheme are provided to support the early design validation.
Figure 6.1: Memory controller simulation flow.
55
For this simulation, the script performed explicit write and read opera-
tions successively, leaving the task of setup and refresh commands to the
memory controller, since it must independently execute this operations.
The simulation outputs are logged in a text format detailing events, opera-
tions, and their timestamps. Figure 6.2 presents a summarized log output.
Figure 6.2: Memory controller simulation results: log output.
Source: Author.
Another output is the waveform of the controller signals. Figure 6.3

shows a part of the simulation execution, regarding refresh, load mode,
read and write commands. The parameters were selected in conformity
with the datasheet [24] [25] [26] nominal values.
During this design evaluation, some misunderstanding of memory pa-
rameters were detected and corrected, such as the refresh rate that was
smaller than the minimal recommended. Also, this test ensured that the
memories could operate in parallel without losing the timing constraints
and functional requirements.
Requirements validated with these simulations: REQ-PAY-040, REQ-PER-000
16 , REQ-PER-010, REQ-PER-020, REQ-OPE-060.
16
As further explained, the operation frequency in the board had limitations not detectable during the
simulations.
56
6.2 Hardware Tests
Figure 6.3: Memory controller simulation results: signal waveforms.
Source: Author.
6.2 Hardware Tests

The board hardware evaluation was performed in steps: visual inspection,
mechanical inspection, electrical inspection and electrical testing. During
the first inspection, the packaging was assessed to ensure integrity of the
board, the 3D renders were compared with the received board, the layer
markers checked, and the reports from the manufacturer revised. The me-
chanical inspection was executed to ensure that the board dimensions and
mounting holes were correct. The electrical inspection was important to
detect any potential problem concerning the proper electrical operation,
such as: solder short circuits, missing components, lifted pins, poor solder-
ing in any pin, swapped components, and device partnumbers. The final
step was to perform electrical testing, starting with a continuity evaluation
of several points and at the end a power-up procedure. Figure 6.4 and
Figure 6.5 presents the final steps of the hardware testing.
After these procedures, any problem was detected in the hardware de-
sign, despite some limitations in the maximum memories operation fre-
quency. It was detected that in the maximum frequency (approximately
143MHz) the memories presented some corrupted data addresses and con-
trol signal glitches, attributed to signal interference and integrity. This was
expected since the project focused on an 100MHz memory operation and
with three devices in parallel is hard to precisely match lengths and return
paths. Despite that, this limitation not affect the The debug interfaces
supported easy debugging sessions and the status LEDs provided a good
visual feedback for the board operation. Further functional testing was
57
performed in the scope of the firmware evaluation.

Figure 6.4: Hardware test results: fully operational board.
Source: Author.
Figure 6.5: Hardware test results: average power consumption.
Source: Author.
Requirements validated with these tests: REQ-PAY-000, REQ-PAY-030, REQ-

PAY-040, REQ-PAY-050, REQ-PAY-060, REQ-PAY-070, REQ-ENV-000, REQ-ENV-010, REQ-
ENV-020, REQ-ENV-030, REQ-PER-020. Requirements that failed with these
tests: REQ-ENV-040. This last requirement was not followed in the board
design due to the size limitations and the increased assembly difficulty.
Requirements that partially failed with these tests: REQ-PER-000 17 .
6.3 Firmware Tests

The firmware was tested across all the project phases with different ap-
proaches. During the prototype, more flexible and specific tests were exe-
17
As previously explained in this section.
58
6.3 Firmware Tests
cuted to validate the behavior of peripherals and external devices. Then,

starting with the engineering model and the first board manufactured, the
firmware was already in a more mature state with several log messages,
self-test routines, and the major structure implemented. This lead to func-
tional testing and the requirements were confronted until achieving the
desired behavior. When the first integration tests started, the real appli-
cation in the full state could be excited, providing enough confidence of
the payload performance and reliability. Also, a full radiation experiment
was performed, which produced more insights about the platform under a
simulated harsh environment, as explained in the next section.
In the flight model, the firmware was already tested and integrated with
the FloripaSat-2 OBDH. Then, the efforts were applied to the firmware
documentation. Figure 6.6 presents an example of log message showing
the last version of the firmware.
Figure 6.6: Example of a firmware log message.
Source: Author.
Requirements validated with these tests: REQ-PAY-070, REQ-PER-030, REQ-

OPE-000, REQ-OPE-010, REQ-OPE-020, REQ-OPE-030, REQ-OPE-040, REQ-OPE-050, REQ-
OPE-070, REQ-OPE-080, REQ-OPE-090, REQ-OPE-100.
59
6.4 Radiation Tests

During the development and improvements for the flight model, it was pos-
sible to evaluate the payload under experimental radiation conditions in the
ChipIr beamline [38] [39]. The experiment was intended to provide only a
preliminary overview of the platform under radiation environments due to
schedule and budget restrictions for more extensive and broad assessments.
Two identical boards were exposed to high energy neutrons during contin-
uous hours before presenting critical damage and reported several events.
This experiment represented a great evaluation opportunity for the pay-
load during the critical transition of the engineering model to the flight
system, providing precious data to enhance the testing routines and iden-
tify potential fault mechanisms. Despite that, the experiment presented
some limitations since the type of radiation used was not the main target
of the experiment (atmospheric-like neutrons instead of more energetic and
diverse particles found in LEO). As presented in Figure 6.7, the payload
was exposed to a irradiation beam that produces neutron particles in a
controlled intensity, spectrum, and area. Note that the beam intensity is
several orders of magnitude higher than the atmospheric conditions, which
turns feasible only few hours of experimental exposure representing months
in the real environment.
Figure 6.7: Experiment radiation parameters.
Source: ChipIr, 2020.
Figure 6.8 describes a simplified diagram of the test setup used during
60
6.4 Radiation Tests
the experiment. Figure 6.9 presents the actual setup mounted inside the
experiment facilities.
Figure 6.8: Radiation experiment setup diagram.
USB JTAG SDRAM B

Laptop USB / RJ45 RJ45 /
USB
UART SoC
SmartFusion2
SDRAM D
+3.3 +3.3
GND GND SDRAM F
Control Room Irradiation Room Neutron Beam
Source: L. Luza et al., 2021
Figure 6.9: Payload board in red fixed inside the beam area in blue.
The scope of this work focus on the development aspects of the platform,
61
then the results acquired from radiation experiments, in ground facilities or

in orbit, are used for the production of future scientific studies [40]. Despite
that, a preliminary result achieved was the comparison between the tech-
nological differences of the memory devices. Figure 6.10 shows a summary
of the analysis of the experiment, which is better described in a work under
review by the author and other colleagues. The experiment exposed Single
Bit Upsets (SBU) and stuck bits 18 . The results point that the technological
node scaling is not the only factor changing the error cross sections, but
also the manufacturing enhancements and capabilities (materials, foundry
equipment, physical implementation enhancements, and other processes)
interfere in the analysis. Despite still preliminary, this result is interesting
since it is expected that reducing the node size tend to increase the error
cross sections, which is not seen in the results transition from 110nm to
72nm. The scaling from 72nm to 63nm follows the expected trend and
support the evidence that the experiment was properly performed.
Figure 6.10: Radiation cross section results according with the SDRAM memories tech-
nology scaling (models B, D, and F).
SBUs
Stuck bits
Cross section (cm2 bit 1)
10 16
10 17
B D F
110 nm 72 nm 63 nm
Memory model
Requirements validated with these tests: REQ-ENV-010, REQ-OPE-010, REQ-

OPE-100, REQ-PER-010, REQ-PER-020. Requirements that partially failed with
these tests: REQ-PER-000 19 .
18
A effect similar to a SBU, but with an extended failure period, resisting to multiple read and writes
and then restoring to the expected cell behavior
19
As previously explained.
62
6.5 Engineering Model Integration
6.5 Engineering Model Integration

The integration with the engineering model occurred in three different
steps: the first using a Raspberry Pi as OBC, the second with an older
version of the FloripaSat-2 OBDH (the FloripaSat-1 OBDH), and the last
using the FloripaSat-2 OBDH engineering model. In order to perform the
first tests, a Raspberry Pi 3 was used to emulate the OBC behavior and
communication. This approach was necessary due to limited access to the
actual OBC. Despite the hardware differences, this test setup allowed the
debug of the most critical communication issues and the improvement of
the interface protocol. The integration with an older FloripaSat-1 OBDH
was necessary due to similar limitations. Figure 6.11 present this test setup.
Figure 6.11: Integration setup with FloripaSat-1 OBDH engineering model
Source: Author.
Finally, with sufficient access to a proper FloripaSat-2 OBDH board,

the final engineering model testing could be done. Figure 6.12
Figure 6.13 presents a command request from the OBC during tests with
the FloripaSat-2 OBDH. It is important to note that the communication
between the payload and the OBC uses the FloripaSat Protocol (FSP). In
the figure is shown 8 bytes: header, destination address, source address,
package type, number of payload packages, payload (command in this case)
and the last two for CRC.
Figure 6.14 presents the payload acknowledgement answer due to the
master request. The same package structure is observed, differing just for
the type, payload content, address positions, and CRC check.
63
Figure 6.12: Engineering model payload integrated with the FloripaSat-2 OBDH.
Source: Author.
Figure 6.13: Example SPI command communication signals from the OBC to the payload
using the FSP protocol.
Source: Author.
All requirements, with few exceptions, were exercised with the integra-
tion since all features of the payload are assessed. However, the most impor-
tant requirements validated with this integration: REQ-PAY-000, REQ-PAY-010,
REQ-PAY-020, REQ-PAY-030, REQ-PAY-060, REQ-PER-030, REQ-OPE-030, REQ-OPE-040,
REQ-OPE-050, REQ-OPE-080.
64
6.6 Flight Model Integration
Figure 6.14: Example SPI acknowledgement answer communication signals from the OBC
to the payload using the FSP protocol.
Source: Author.

The payload flight model was integrated with the FloripaSat-2 platform in
the FlatSat phase as presented in Figure 6.15. The system performed as
intended during these tests since the actual interface between the payload
and satellite continued the same (i.e., a communication and power bus
provided by the FloripaSat-2 OBDH). Due to schedule limitations, the
real integration with the FloripaSat-2 satellite in the final form factor was
not possible, but all the required steps were planned and the payload is
waiting for the satellite launch. Figure 6.16 shows a schematic view of the
satellite with the payload highlighted.
65
Figure 6.15: Flight model payload model integrated with FloripaSat-2 platform in the
FlatSat.
66
Figure 6.16: Flight model payload model integrated with FloripaSat-2 platform (payload
highlighted).
67
7 Conclusion
The development of a complete payload experiment was presented, achiev-
ing the desired mission objectives. Also, this work lead to relevant out-
comes for both research laboratories, since the payload is currently be-
ing used for different radiation assessments in the memory devices and is
planned to be launched alongside the FloripaSat-2 satellite in a complete
space mission. Concerning the technologies involved in the payload, the
approach and design presented some improvements in comparison with the
previous similar missions developed in both laboratories since some new
concepts were employed, such as the use of a RTOS for a more robust
firmware system and the creation of a multipurpose device in relatively
controlled budget.
The project management techniques facilitated and structured the de-
velopment, from defined phases and base requirements. The final verifica-
tion and integration tests presented satisfactory overall performance and
reliability, but revealed some bottlenecks. In firmware, the payload allowed
a robust framework for future utilization and good maintenance. In hard-
ware, the board work properly from the first production, but presented
limitations in the maximum memory frequency operation (in comparison
with the maximum operation allowed). In the FPGA design, the system
performed properly, but more investigation to improve the radiation re-
silience could increase the reliability of the experiments and its duration
before presenting critical failures.
For future work, the payload might be exposed to more broad radiation
sources and energies, providing a better assessment of the system under
radiation. Also, this could be used to augment and corroborate the results
found in the experiments performed in the space missions.
In summary, the payload accomplished its requirements and purpose,
brought some enhancements to the previous employed methods, reported a
complete CubeSat payload development campaign, and provided the neces-
sary tools for personal development and learning experience. Future works
are planned since after the FloripaSat-2 successful launch, the experiment
data will be provided and other ground experiments are intended, allowing
data analysis and further investigation in the memory devices.
68
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2019. Disponı́vel em: <gomspace.com/shop/subsystems/command-
and-data-handling/default.aspx>.
[31] ISIS. Command and Data handling, Acesso em: Dezembro de 2019.
Disponı́vel em: <www.isispace.nl/products/command-data-handling-
systems/>.
[32] EnduroSat. OnBoard Computer (OBC), Acesso em: Dezembro de
2019. Disponı́vel em: <www.endurosat.com/cubesat-store/cubesat-
obc/onboard-computer-obc/>.
[33] PolySat. PolySat Research Laboratory, Acesso em: Dezembro de 2019.
Disponı́vel em: <www.polysat.org/>.
[34] Carlos E. Gonzalez, Camilo J. Rojas, Alexandre Bergel, and Marcos A.
Diaz. An architecture-tracking approach to evaluate a modular and
extensible flight software for CubeSat nanosatellites. IEEE Access,
7:126409–126429, 2019.
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[35] Said Hamdioui. Test for single-port and two-port SRAMs. In Testing
Static Random Access Memories, volume 26 of Frontiers in Electronic
Testing, chapter 6, pages 106–107. Springer, Boston, MA, US, 1 edi-
tion, 2004. DOI: 10.1007/978-1-4757-6706-3.
[36] Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch,
and Arnaud Virazel. Basics on SRAM testing. In Advanced Test
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[37] D. Niggemeyer, M. Redeker, and J. Otterstedt. Integration of non-
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72
A Payload hardware schematics
73
1 2 3 4
Rev Description Date Author
1.0 Initial release. 30-Apr-2020 Andre M. P. Mattos

A A
1.1 Review updates. 28-May-2020 Andre M. P. Mattos
Power Diagram
B B
Revision History
PCB FIDUTIALS MECHANICAL HOLES

1_Interface.SchDoc
COFD1
FD1 COFD2
FD2 COFD3
FD3 COM1
M1 COM2
M2 COM3
M3 COM4
M4
COFD4
FD4 COFD5
FD5 COFD6
FD6 PIM10 PIM20 PIM30 PIM40
GND
PCB Elements
C C
HARSH Payload Daughter Board

(HARSH_Payload) for OBDH 2.0 Hardware
Copyright © 2020
by SpaceLab and LIRMM.
- Drawn by: André Martins Pio de Mattos.

- Based on OBDH 2.0 designed by: André Martins Pio de Mattos.
- Based on DB_Memory designed by: Yan Castro de Azeredo.
- Support: Kleber Reis Gouveia Júnior.
D Block Diagram D
Title: HARSH Payload Achitecture LIRMM - SPACERADGroup

Project: HARSH_Payload.PrjPCB UFSC - SpaceLab
Size: A4 Revision: 1.1
Project Information Date: 6/1/2020 Time: 3:23:15 PM Sheet 1 of 8 Institutional partnership project:
Drawn By: Andre Martins Pio de Mattos research in memory radiation hardness
Model: HARSH_DB
1 2 3 4
1 2 3 4
MAIN DEBUG HEADER COP1

P1 DNP FLIGHT MODEL VERSION: (P1 header not GPIO INTERFACE ALTERNATIVE DEBUG INTERFACES
placed) JTAG flight model
GND PIP101 1
COP3
P3 DNP
UART i UART_RX 1 NLEXTERNAL0VCC
EXTERNAL_VCC Additional GPIOs and live probes
PIP102 2 - Power supply: from FloripaSat EPS Antenna PIP301
UART_TX PIP103 regulator place J_V1 or from FSat-II EPS OBDH DNP 2 TDI
COP4 DNP
P4
A 3 PIP302 PROBES i PROBE_A PIP401 A
POWER_SOURCES regulator place J_V2 (ONLY one J_Vx placed) 1 GPIO_17 3 TDO 1
SPI i SPI_CS - Programming: use P3 picoblade connector PIP201 PIP303 PROBE_B PIP402
i
PIP104 4 2 GPIO_12 4 TMS 2
SPI_MOSI PIP202 PIP304
PIP105 5 3 GPIO_18 5 TCK GPIO i GPIO_20
SPI_MISO OTHER VERSIONS: PIP203 PIP305 PIP403 3
SOURCE_VCC PIP106 6 4 GPIO_13 6 GPIO_19
SPI_CLK PIP204 PIP306 PIP404 4
PIP107 7 - Power supply: from FloripaSat EPS Antenna 5 GPIO_10
EXTERNAL_VCC J_V0 COJ0V0 PIP205
MNT 1 7
PIJ0V002 PIJ0V001 JTAG i TDI regulator place J_V1, from FSat-II EPS OBDH 6 GPIO_8 PIP307 GND PIP405 5
PIP108 8 PIP206
0R DNP TDO regulator place J_V2 or from external supply place 7 GPIO_9 MNT 2 8
COJ0V1 PIP109 9 J_V0 (ONLY one J_Vx placed or connected) PIP207 PIP308 GND
ANTENNA_VCC J_V1 PIJ0V102 PIJ0V101 TMS PIP1010 - Programming: use P1 header pins (8, 9, 10 and 11) 8 GPIO_15
PIP208
10
0R TCK 9 GPIO_16
PIP1011 11 PIP209
OBDH_DVCC
COJ0V2
J_V2 OBSERVATIONS: 10 GPIO_26
PIP2010
PIJ0V202 PIJ0V201 EXTERNAL_VCC - JTAG programming requires power supply from 11 GPIO_25
0R DNP
PIP1012 12 PIP2011 CAN TRANCEIVER AND INTERFACE
external supply or OBDH sources 12 GPIO_21 COU1
U1
PIP2012
13 GPIO_22 COP5
P5 DNP 5 4 CAN_RX
PIP2013 PIU105 NC RXD PIU104
14 GPIO_29
PIP2014 1
PIP501 CAN_N 6
PIU106 3
PIU103
CANL VCC 3V3_DVCC
15 NLCAN0P
2 CAN_P 7 2
TOPOLOGY HARNESS SIGNALS PIP2015 PIP502 PIU107 CANH GND PIU102
B 3
PIP503 8
PIU108 1 CAN_TX
PIU101 B
MNT 1 16 NC TXD
PIP2016
2_Topology.SchDoc MNT 2 MNT 1 4 TCAN332DCNR
17
PIP2017 GND PIP504
GND
GPIO_USER MNT 2 5 GND
PIP505
NLGPIO025
GPIO_25 I2C_INTERFACE COP2
P2
NLGPIO026
GPIO_26 GPIO_25 NLI2C0SDA
GPIO_26 I2C_SDA
NLGPIO019
GPIO_19 12C_INTERFACE I2C_SDA
NLI2C0SCL Termination resistor Decoupling capacitor
GPIO_20 GPIO_19
NLGPIO020 I2C_SCL
GPIO_21 GPIO_20
NLGPIO021 I2C_SCL CAN_P PIR102COR1
R1 NLCAN0N
PIR101 CAN_N 3V3_DVCC PIC101 PIC102 GND
GPIO_22 GPIO_21
NLGPIO022 120R COC1
C1 0.1uF
GPIO_29 GPIO_22
NLGPIO029
GPIO_12 GPIO_29
NLGPIO012 GPIO_USER UART_INTERFACE
GPIO_13 GPIO_12
NLGPIO013
GPIO_17 GPIO_13
NLGPIO017 UART_TX
NLUART0TX
UART_TX
GPIO_18 GPIO_17
NLGPIO018 UART_INTERFACE NLUART0RX
UART_RX
NLGPIO08
GPIO_8 GPIO_18 UART_RX SYSTEM LED INTERFACE FROM OBDH DAUGHTER BOARD CONNECTOR
NLGPIO09
GPIO_9 GPIO_8
GPIO_10 GPIO_9
NLGPIO010 NLOBDH0DVCC
OBDH_DVCC PIP601 COP6
P6
GPIO_15 GPIO_10
NLGPIO015 SPI_INTERFACE NLANTENNA0VCC
ANTENNA_VCC
1 2 PIP602
GPIO_16 GPIO_15
NLGPIO016 NLSPI0CLK
SPI_CLK SYS_LED PIP603 3 4 PIP604 GND
GPIO_16 SPI_CLK
NLSPI0MOSI
SPI_MOSI PIP605 5 6 PIP606
SPI_SDI DB_GPIO_0 DB_GPIO_1
NLSYS0LED
GPIO_SYSTEM SPI_INTERFACE
SPI_SDO
NLSPI0MISO
SPI_MISO PIR202 DB_GPIO_2
PIP607 7 8 PIP608
DB_GPIO_3
C SYS_LED NLSPI0CS COR2
R2 PIP609 9 10 PIP6010 C
DB_GPIO_1 GPIO_1
NLDB0GPIO01 SPI_SS
SPI_CS
1K SPI_CLK PIP6011 11 12 PIP6012
DB_GPIO_0 GPIO_14
NLDB0GPIO00 SPI_MISO BOARD_ENABLE_N
DB_GPIO_2 GPIO_24
NLDB0GPIO02 GPIO_SYSTEM PIR201 SPI_MOSI
PIP6013 13 14 PIP6014
PWRGD_BOARD
DB_GPIO_3 GPIO_23
NLDB0GPIO03 PIP6015 15 16 PIP6016
GPIO_11 CAN_INTERFACE SPI_CS I2C_SDA
POWER_ENABLES
CAN_TX
NLCAN0TX
CAN_TX
NLCAN0RX
CAN_RX
PID10 COD1
PIP6017
FPGA_ENABLEPIP6019
17
19
18
20
PIP6018
PIP6020
I2C_SCL
CAN_INTERFACE CAN_RX D1
NLBOARD0ENABLE0N
BOARD_ENABLE_N Orange FSI-110-03-G-D-AD
BOARD_ENABLE_N
NLFPGA0ENABLE
FPGA_ENABLE Features not used from the generic daughter board interface connector:
FPGA_ENABLE
ON_B POWER_ENABLES JTAG
NLTDI
TDI
PID102 -BATTERY VCC
Features used differently, but compatible, in the generic daughter board interface
ON_D TDI NLTDO connector:
TDO
ON_F JTAG TDO NLTCK
TCK - DB_CS2 as GPIO for FPGA enable (Active High)
TCK NLTMS
TMS - DB_ADC0 as GPIO for board "power good" status (feedback of payload power status)
PWRGD_STATUS TMS GND
- DB_ADC1 as GPIO for board enable (Active Low)
PWRGD_B
PWRGD_D LIVE_PROBES According to SAMTEC product specification, the maximum body height of the connector
PWRGD_STATUS NLPROBE0A
PROBE_A when pressed should be 3.28 mm.
PWRGD_F PROBE_A
NLPWRGD0BOARD
PWRGD_BOARD LIVE_PROBES NLPROBE0B
PROBE_B
D PWRGD_BOARD PROBE_B D
SOURCE_VCC SOURCE_VCC 3V3_DVCC 3V3_DVCC Title: HARSH Payload Interface LIRMM - SPACERADGroup
Project:HARSH_Payload.PrjPCB UFSC - SpaceLab
Date: 6/1/2020 Time: 3:23:15 PM Sheet 2 of 8 Institutional partnership project:
Model: HARSH_DB
1 2 3 4
1 2 3 4
5_FPGA_Banks_4_7.SchDoc 3_SDRAM_Memories.SchDoc
A A
MEM_DATA MEM_DATA
MEM_ADDR MEM_ADDR
MEM_CTRL MEM_CTRL
3V3_MEM_B 3V3_MEM_B
POLIVE0PROBES0PROBE0B
POLIVE0PROBES0PROBE0A
POLIVE0PROBES
LIVE_PROBES LIVE_PROBES 3V3_MEM_D 3V3_MEM_D
3V3_MEM_F 3V3_MEM_F
4_FPGA_Banks_0_2.SchDoc 7_Power_Supply.SchDoc
B B
POPOWER0ENABLES0ON0F
POPOWER0ENABLES0ON0D
POPOWER0ENABLES0ON0B
POPOWER0ENABLES0FPGA0ENABLE
POPOWER0ENABLES0BOARD0ENABLE0N
POPOWER0ENABLES
POWER_ENABLES POSOURCE0VCC
SOURCE_VCC SOURCE_VCC
POWER_ENABLES POWER_ENABLES
3V3_DVCC PO3V30DVCC
3V3_DVCC
POPWRGD0STATUS0PWRGD0F
POPWRGD0STATUS0PWRGD0D
POPWRGD0STATUS0PWRGD0BOARD
POPWRGD0STATUS0PWRGD0B
POPWRGD0STATUS
PWRGD_STATUS
POGPIO0USER0GPIO029
POGPIO0USER0GPIO026
POGPIO0USER0GPIO025
POGPIO0USER0GPIO022
POGPIO0USER0GPIO021
POGPIO0USER0GPIO020
POGPIO0USER0GPIO019
POGPIO0USER0GPIO018
POGPIO0USER0GPIO017
POGPIO0USER0GPIO016
POGPIO0USER0GPIO015
POGPIO0USER0GPIO013
POGPIO0USER0GPIO012
POGPIO0USER0GPIO010
POGPIO0USER0GPIO09
POGPIO0USER0GPIO08
POGPIO0USER
GPIO_USER GPIO_USER PWRGD_STATUS PWRGD_STATUS
POGPIO0SYSTEM0GPIO024
POGPIO0SYSTEM
GPIO_SYSTEM GPIO_SYSTEM 3V3_MEM_B 3V3_MEM_B
3V3_MEM_D 3V3_MEM_D
POCAN0INTERFACE0CAN0TX
POCAN0INTERFACE0CAN0RX
POCAN0INTERFACE
CAN_INTERFACE CAN_INTERFACE 3V3_MEM_F 3V3_MEM_F
SOURCE_VCC SOURCE_VCC
C PO12C0INTERFACE0I2C0SDA
PO12C0INTERFACE0I2C0SCL
PO12C0INTERFACE
12C_INTERFACE 12C_INTERFACE 3V3_DVCC 3V3_DVCC C
1V2_DVCC 1V2_DVCC
POUART0INTERFACE0UART0TX
POUART0INTERFACE0UART0RX
POUART0INTERFACE
UART_INTERFACE UART_INTERFACE
6_FPGA_Miscellaneous.SchDoc
POSPI0INTERFACE0SPI0SS
POSPI0INTERFACE0SPI0SDO
POSPI0INTERFACE0SPI0SDI
POSPI0INTERFACE0SPI0CLK
POSPI0INTERFACE
SPI_INTERFACE SPI_INTERFACE
POJTAG0TMS
POJTAG0TDO
POJTAG0TDI
POJTAG0TCK
POJTAG
JTAG JTAG
3V3_DVCC 3V3_DVCC
1V2_DVCC 1V2_DVCC
D D
Title: HARSH Payload Topology LIRMM - SPACERADGroup

Project: HARSH_Payload.PrjPCB UFSC - SpaceLab
Model: HARSH_DB
1 2 3 4
1 2 3 4
SDRAM MODEL-B SDRAM MODEL-D SDRAM MODEL-F HARNESS AND PORTS

3V3_MEM_B COU2
U2 3V3_MEM_D COU3
U3 3V3_MEM_F COU4
U4
1 1
PIU301 1
PIU201 VDD VDD VDD
PIU401
14 14
PIU3014 14
PIU2014 VDD VDD PIU4014
VDD
27 27 27
PIU2027 VDD PIU3027 VDD PIU4027 VDD
3 3 3
A PIU203 VDDQ PIU303 VDDQ PIU403 VDDQ A
9 9 9
RAM_CTRL PIU209 VDDQ RAM_DATA RAM_CTRL PIU309 VDDQ RAM_DATA RAM_CTRL PIU409 VDDQ RAM_DATA
43 43 43
PIU2043 VDDQ i
PIU3043 VDDQ i PIU4043 VDDQ MEM_DATA
i 49 i 49
PIU3049 i 49 i
PIU2049 VDDQ VDDQ PIU4049
VDDQ NLDQ0
DQ0
NLDQ1
DQ1 DQ0
CKE 37 CKE 37 CKE 37 NLDQ2 DQ1
PIU2037 CKE PIU3037 CKE PIU4037 CKE DQ2
CLK 38 2 DQ0 CLK 38 2 DQ0 CLK 38 2 DQ0 NLDQ3
DQ3 DQ2
PIU2038 CLK DQ0 PIU202 PIU3038 CLK DQ0 PIU302 PIU4038 CLK DQ0 PIU402
NLDQ4 DQ3
4 DQ1 4 DQ1 4 DQ1 DQ4
DQ1 PIU204 DQ1 PIU304
DQ1 PIU404 NLDQ5
DQ5 DQ4
CAS_NPIU2017
17 5 DQ2 CAS_NPIU3017
17 5
PIU305 DQ2 CAS_N PIU4017
17 5 DQ2 DQ5
CAS DQ2 PIU205 CAS DQ2 CAS DQ2 PIU405 NLDQ6
DQ6
CS0_N PIU2019
19 7 DQ3 CS1_N PIU3019
19 7 DQ3 CS2_N PIU4019
19 7 DQ3 NLDQ7
DQ7 DQ6
CS DQ3 PIU207
RAS_NPIU3018
18
CS DQ3 PIU307
8 DQ4 CS DQ3 PIU407
NLDQ8 DQ7 POMEM0DATA0DQ15
POMEM0DATA0DQ14
POMEM0DATA0DQ13
POMEM0DATA0DQ12
POMEM0DATA0DQ11
POMEM0DATA0DQ10
POMEM0DATA0DQ9
POMEM0DATA0DQ8
POMEM0DATA0DQ7
POMEM0DATA0DQ6
POMEM0DATA0DQ5
POMEM0DATA0DQ4
POMEM0DATA0DQ3
POMEM0DATA0DQ2
POMEM0DATA0DQ1
POMEM0DATA0DQ0
POMEM0DATA
MEM_DATA
RAS_NPIU2018
18 8 DQ4 RAS DQ4 PIU308 RAS_N PIU4018
18 8 DQ4 DQ8
RAS DQ4 PIU208
WE_N PIU3016
16 RAS DQ4 PIU408 NLDQ9 DQ8
WE_N PIU2016
16 10 DQ5 WE DQ5 PIU3010 DQ5
10 WE_N PIU4016
16 10 DQ5 DQ9
WE DQ5 PIU2010
11 DQ6 11 DQ6 WE DQ5 PIU4010 DQ10 DQ9
NLDQ10
DQ6 PIU2011 DQ6 PIU3011 11 DQ6 DQ11 DQ10
NLDQ11
DQMH PIU3039
39 13 DQ7 DQ6 PIU4011
DQMH PIU2039
39
DQMH DQ7
13
PIU2013
DQ7 DQMH DQ7 PIU3013 DQMH PIU4039
39
DQMH DQ7
13 DQ7
PIU4013 DQ12 DQ11
NLDQ12
DQML PIU2015
15 42 DQ8 DQML PIU3015
15
DQML DQ8
42 DQ8
PIU3042 DQML PIU4015
15 42 DQ8 DQ13 DQ12
NLDQ13
DQML DQ8 DQ14 DQ13
PIU2042 PIU4042
44 DQ9 44 DQ9 DQML DQ8 NLDQ14
DQ9 PIU2044 DQ9 PIU3044 44 DQ9
PIU4044 DQ15 DQ14
NLDQ15
BA0 20 45 DQ10 BA0 20 45 DQ10 DQ9 DQ15
PIU2020 BA0 DQ10 PIU2045 PIU3020 BA0 DQ10 PIU3045 BA0 20 45 DQ10
BA1 21 47 DQ11 BA1 21 47 DQ11 PIU4020 BA0 DQ10 PIU4045
PIU2021 BA1 DQ11 PIU2047 PIU3021 BA1 DQ11 PIU3047 BA1 21 47 DQ11
48 DQ12 48 DQ12
PIU4021 BA1 DQ11 PIU4047
DQ12 PIU2048 DQ12 PIU3048 48 DQ12

A0 23 50 DQ13 A0 23 50 DQ13 DQ12 PIU4048
B PIU2023 A0 DQ13 PIU2050 PIU3023 A0 DQ13 PIU3050 A0 23
PIU4023 50 DQ13
PIU4050 MEM_ADDR B
A1 24 51 DQ14 A1 24 51 DQ14 A0 DQ13
PIU2024 A1 DQ14 PIU2051 PIU3024 A1 DQ14 PIU3051 A1 24
PIU4024 51 DQ14
PIU4051 NLA0
A0
A2 25 53 DQ15 A2 25 53 DQ15 A1 DQ14 NLA1 A0
PIU2025 PIU2053 PIU3025 A2 DQ15 PIU3053 A2 25 53 DQ15 A1
A2 DQ15 A3 26 PIU4025 A2 DQ15 PIU4053
NLA2
A2 A1
A3 26
PIU2026 PIU3026 A3 A3 26 A2
A3 A4 29 40
PIU4026 A3 NLA3
A3
A4 29 40 PIU3029 A4 NC PIU3040 A4 29 40 NLA4
A4 A3
PIU2029 A4 NC PIU2040
A5 30
PIU4029 A4 NC PIU4040
A4
A5 30 PIU3030 A5 A5 30 NLA5
A5
PIU2030 A5 A6 31 28 PIU4030 A5 NLA6 A5
A6 31 28 PIU3031 A6 VSS PIU3028 A6 31 28 A6
PIU2031 A6 VSS PIU2028
A7 32 41 PIU4031 A6 VSS PIU4028 NLA7
A7 A6
A7 32
PIU2032 41
PIU2041 PIU3032 A7 VSS PIU3041 A7 32 41 NLA8 A7 POMEM0ADDR0BA1
POMEM0ADDR0BA0
POMEM0ADDR0A12
POMEM0ADDR0A11
POMEM0ADDR0A10
POMEM0ADDR0A9
POMEM0ADDR0A8
POMEM0ADDR0A7
POMEM0ADDR0A6
POMEM0ADDR0A5
POMEM0ADDR0A4
POMEM0ADDR0A3
POMEM0ADDR0A2
POMEM0ADDR0A1
POMEM0ADDR0A0
POMEM0ADDR
MEM_ADDR
A7 VSS A8 33 54 PIU4032 A7 VSS PIU4041 A8
A8 33
PIU2033 54
PIU2054 PIU3033 A8 VSS PIU3054 A8 33 54 NLA9
A9 A8
A8 VSS A9 34 6
PIU4033 A8 VSS PIU4054
A9
A9 34
A9 VSSQ
6 PIU3034 A9 VSSQ PIU306 A9 34 6 NLA10
A10
A10
PIU2034
22
PIU206
12 A10 22 12
PIU4034 A9 VSSQ PIU406
NLA11
A11 A10
PIU2022 A10 VSSQ PIU2012 PIU3022 A10 VSSQ PIU3012 A10 22
PIU4022 12
PIU4012 A11
A11 35 46 A11 35 46 A10 VSSQ NLA12
A12
PIU2035 A11 VSSQ PIU2046 PIU3035 A11 VSSQ PIU3046 A11 35
PIU4035 46
PIU4046 NLBA0
BA0 A12
A12 36 52 A12 36 52 A11 VSSQ BA0
PIU2036 A12 VSSQ PIU2052 PIU3036 A12 VSSQ PIU3052 A12 36 52 NLBA1
BA1
PIU4036 A12 VSSQ PIU4052
BA1
IS42S16320B-6TLI IS42S16320D-7TLI IS42S16320F-7TLI
i i i
RAM_ADDR MEM_CTRL
RAM_ADDR GND GND RAM_ADDR GND NLCKE
CKE
NLCLK
CLK CKE
NLCAS0N
CAS_N CLK
NLRAS0N
RAS_N CAS_N
C DECOUPLING CAPACITORS SDRAM MODEL-B DECOUPLING CAPACITORS SDRAM MODEL-D DECOUPLING CAPACITORS SDRAM MODEL-F NLWE0N
WE_N RAS_N C
NLCS00N
CS0_N WE_N POMEM0CTRL0WE0N
POMEM0CTRL0RAS0N
POMEM0CTRL0DQML
POMEM0CTRL0DQMH
POMEM0CTRL0CS20N
POMEM0CTRL0CS10N
POMEM0CTRL0CS00N
POMEM0CTRL0CLK
POMEM0CTRL0CKE
POMEM0CTRL0CAS0N
POMEM0CTRL
MEM_CTRL
To VDDQ To VDDQ To VDDQ NLCS10N
CS1_N CS0_N
3V3_MEM_B 3V3_MEM_D 3V3_MEM_F NLCS20N
CS2_N CS1_N
NLDQMH
DQMH CS2_N
NLDQML
DQML DQMH
PIC201 PIC301 PIC401 PIC501 PIC601 PIC1 01 PIC1201 PIC1301 PIC1401 PIC1501 PIC20 1 PIC2101 PIC2 01 PIC2301 PIC2401 DQML
COC2
C2 COC3
C3 COC4
C4 COC5
C5 COC6
C6 COC11
C11 COC12
C12 COC13
C13 COC14
C14 COC15
C15 COC20
C20 COC21
C21 COC22
C22 COC23
C23 COC24
C24
PIC202 10uF PIC302 0.1uFPIC402 0.1uFPIC502 0.1uFPIC602 0.1uF PIC1 02 10uF PIC1202 0.1uFPIC1302 0.1uFPIC1402 0.1uFPIC1502 0.1uF PIC20 2 10uF PIC2102 0.1uFPIC2 02 0.1uFPIC2302 0.1uFPIC2402 0.1uF
PO3V30MEM0B
3V3_MEM_B 3V3_MEM_B
To VDD To VDD To VDD
3V3_MEM_B 3V3_MEM_D 3V3_MEM_F PO3V30MEM0D
3V3_MEM_D 3V3_MEM_D
GND GND GND
PIC701 PIC801 PIC901 PIC10 1 PIC1601 PIC1701 PIC1801 PIC1901 PIC2501 PIC2601 PIC2701 PIC2801 PO3V30MEM0F
3V3_MEM_F 3V3_MEM_F
COC7
C7 COC8
C8 COC9
C9 COC10
C10 COC16
C16 COC17
C17 COC18
C18 COC19
C19 COC25
C25 COC26
C26 COC27
C27 COC28
C28
PIC702 10uF PIC802 0.1uFPIC902 0.1uFPIC10 2 0.1uF PIC1602 10uF PIC1702 0.1uFPIC1802 0.1uFPIC1902 0.1uF PIC2502 10uF PIC2602 0.1uFPIC2702 0.1uFPIC2802 0.1uF
GND GND GND
D D
Title: HARSH Payload SDRAM memories LIRMM - SPACERADGroup

Model: HARSH_DB
1 2 3 4
1 2 3 4
DDRIO BANK (not used) MSIO BANKS (Communication and GPIOs) HARNESS AND PORTS
COU5A
COU5B
COU5C
U5A
A18 GPIO_USER
DDRIO29PB0/MDDR_ADDR14 PIU50A18 U5B NLGPIO025
GPIO_25
BANK 0
B18 G17 NLGPIO026

GPIO_26 GPIO_25
DDRIO29NB0/MDDR_ADDR15 PIU50B18 MSIO21PB1/GB5/USB_XCLK_C PIU50G17
BANK 1
D17 G16 NLGPIO019
GPIO_19 GPIO_26
DDRIO30PB0/MDDR_ADDR12 PIU50D17
MSIO21NB1/MMUART_1_TXD/GPIO_24_B/USB_DATA2_C PIU50G16 NLGPIO020 GPIO_19
A C17 E18 GPIO_25 GPIO_20 A
DDRIO30NB0/MDDR_ADDR13 PIU50C17 MSIO22PB1/GB6/MMUART_1_CLK/GPIO_25_B/USB_DATA4_C PIU50E18 NLGPIO021
GPIO_21 GPIO_20
D15 F18 GPIO_26 NLGPIO022 GPIO_21
DDRIO31PB0/MDDR_ADDR10 PIU50D15 MSIO22NB1/MMUART_1_RXD/GPIO_26_B/USB_DATA3_C PIU50F18 GPIO_22
E15 F15 NLGPIO029
GPIO_29 GPIO_22
DDRIO31NB0/MDDR_ADDR11 PIU50E15 MSIO23PB1/MMUART_0_RTS/GPIO_17_B/USB_DATA5_C PIU50F15
GPIO_29
A16
PIU50A16 F16 NLGPIO012
GPIO_12 POGPIO0USER0GPIO029
POGPIO0USER0GPIO026
POGPIO0USER0GPIO025
POGPIO0USER0GPIO022
POGPIO0USER0GPIO021
POGPIO0USER0GPIO020
POGPIO0USER0GPIO019
POGPIO0USER0GPIO018
POGPIO0USER0GPIO017
POGPIO0USER0GPIO016
POGPIO0USER0GPIO015
POGPIO0USER0GPIO013
POGPIO0USER0GPIO012
POGPIO0USER0GPIO010
POGPIO0USER0GPIO09
POGPIO0USER0GPIO08
POGPIO0USER
GPIO_USER
DDRIO32PB0/MDDR_ADDR8 MSIO23NB1/MMUART_0_DTR/GPIO_18_B/USB_DATA6_C PIU50F16 NLGPIO013
GPIO_13 GPIO_12
B17 E17 GPIO_19 GPIO_13
DDRIO32NB0/MDDR_ADDR9 PIU50B17 MSIO24PB1/MMUART_0_CTS/GPIO_19_B/USB_DATA7_C PIU50E17 NLGPIO017
GPIO_17
B16 E16 GPIO_20 NLGPIO018 GPIO_17
DDRIO33PB0/MDDR_ODT PIU50B16 MSIO24NB1/MMUART_0_DSR/GPIO_20_B PIU50E16 GPIO_18
C16 D20 GPIO_21 NLGPIO08
GPIO_8 GPIO_18
DDRIO33NB0/MDDR_ADDR7 PIU50C16
MSIO25PB1/MMUART_0_RI/GPIO_21_B PIU50D20
NLGPIO09 GPIO_8
B14 C20 GPIO_22 GPIO_9
DDRIO34PB0/MDDR_ADDR5 PIU50B14 MSIO25NB1/MMUART_0_DCD/GPIO_22_B PIU50C20 NLGPIO010
GPIO_10 GPIO_9
A15 D18 UART_TX GPIO_10
DDRIO34NB0/MDDR_ADDR6 PIU50A15 MSI26NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C PIU50D18 NLGPIO015
GPIO_15
C14 C19 UART_RX NLGPIO016 GPIO_15
DDRIO35PB0/MDDR_ADDR3 PIU50C14 MSIO27PB1/MMUART_0_RXD/GPIO_28_B/USB_STP_C PIU50C19 GPIO_16
C15 B19 GPIO_29 GPIO_16
DDRIO35NB0/MDDR_ADDR4 PIU50C15 MSIO27NB1/MMUART_0_CLK/GPIO_29_B/USB_NXT_C PIU50B19
A13 A20 I2C_SDA
DDRIO36PB0/MDDR_ADDR1 PIU50A13 MSIO28PB1/I2C_0_SDA/GPIO_30_B/USB_DATA0_C PIU50A20 GPIO_SYSTEM
A14 A19 I2C_SCL NLGPIO01
GPIO_1
DDRIO36NB0/MDDR_ADDR2 PIU50A14 MSIO28NB1/I2C_0_SCL/GPIO_31_B/USB_DATA1_C PIU50A19 GPIO_1
D13
PIU50D13 NLGPIO014
GPIO_14
DDRIO37PB0/MDDR_BA2 NLGPIO024 GPIO_14
D14 M2S010-VF400 GPIO_24
DDRIO37NB0/MDDR_ADDR0 PIU50D14
E13 NLGPIO023
GPIO_23 GPIO_24 POGPIO0SYSTEM0GPIO024
POGPIO0SYSTEM
GPIO_SYSTEM
DDRIO38PB0/MDDR_BA0 PIU50E13 NLGPIO011
GPIO_11 GPIO_23
F13 U5C GPIO_11
DDRIO38NB0/MDDR_BA1 PIU50F13 V20 PWRGD_B
B13 MSIO0PB2
DDRIO39PB0/MDDR_CLK PIU50B13 PIU50V20
BANK 2
B12 V19 ON_B CAN_INTERFACE
DDRIO39NB0/MDDR_CLK_N PIU50B12 MSIO0NB2/USB_DATA7_B PIU50V19
F11 U18
B DDRIO40PB0/MDDR_RESET_N PIU50F11 MSIO1PB2/USB_XCLK_B PIU50U18 NLCAN0TX B
E12 U19 ON_D CAN_TX
DDRIO40NB0/MDDR_CAS_N PIU50E12 MSIO1NB2/USB_DIR_B PIU50U19 CAN_TX
C12
DDRIO41PB0/MDDR_CKE PIU50C12
T18
MSIO2PB2/USB_STP_B PIU50T18
NLCAN0RX
CAN_RX POCAN0INTERFACE0CAN0TX
POCAN0INTERFACE0CAN0RX
POCAN0INTERFACE
CAN_INTERFACE
C11 T19 CAN_RX
DDRIO41NB0/MDDR_CS_N PIU50C11 MSIO2NB2/USB_NXT_B PIU50T19
D12 T20 PWRGD_D
DDRIO42PB0/MDDR_RAS_N PIU50D12 MSIO3PB2/USB_DATA0_B PIU50T20
E11 R20 ON_F
DDRIO42NB0/MDDR_WE_N PIU50E11 MSIO3NB2/USB_DATA1_B PIU50R20
I2C_INTERFACE
A11 P20 PWRGD_F
DDRIO43PB0/MDDR_DQ14 PIU50A11 MSIO4PB2/USB_DATA2_B PIU50P20 NLI2C0SDA
I2C_SDA
B11 N19 I2C_SDA
DDRIO43NB0/MDDR_DQ15 PIU50B11 MSIO4NB2/USB_DATA3_B PIU50N19 NLI2C0SCL
D10 R17 I2C_SCL PO12C0INTERFACE0I2C0SDA
PO12C0INTERFACE0I2C0SCL
PO12C0INTERFACE
12C_INTERFACE
DDRIO44PB0/MDDR_DQ12 PIU50D10 MSIO5PB2/USB_DATA4_B PIU50R17 I2C_SCL
E10 R18
DDRIO44NB0/MDDR_DQ13 PIU50E10 MSIO5NB2/USB_DATA5_B PIU50R18
E8 P18
DDRIO45PB0/MDDR_TMATCH_0_IN PIU50E8 MSIO6PB2/USB_DATA6_B PIU50P18
F9 P19 UART_INTERFACE
DDRIO45NB0/MDDR_DM_RDQS1 PIU50F9 MSIO6NB2 PIU50P19
C9 R16 NLUART0TX
UART_TX
DDRIO46PB0/MDDR_DQS1 PIU50C9 MSIO7PB2 PIU50R16 UART_TX
B9 R15 CAN_TX
DDRIO46NB0/MDDR_DQS1_N PIU50B9 MSIO7NB2/CAN_TX/GPIO_2_A/USB_DATA0_A PIU50R15 NLUART0RX
UART_RX POUART0INTERFACE0UART0TX
POUART0INTERFACE0UART0RX
POUART0INTERFACE
UART_INTERFACE
D9 N20 CAN_RX UART_RX
DDRIO47PB0/MDDR_DQ10 PIU50D9 MSIO8PB2/CAN_RX/GPIO_3_A/USB_DATA1_A PIU50N20
C10 M19
DDRIO47NB0/MDDR_DQ11 PIU50C10 MSIO8NB2/CAN_TX_EN_N/GPIO_4_A/USB_DATA2_A PIU50M19
A9 N16 SPI_INTERFACE
DDRIO48PB0/MDDR_DQ8 PIU50A9 MSIO11PB2/CCC_NE0_CLKI1/I2C_1_SDA/GPIO_0_A/USB_DATA3_A PIU50N16
A10 M17 GPIO_1 NLSPI0CLK
DDRIO48NB0/MDDR_DQ9 PIU50A10 MSIO11NB2/CCC_NE0_CLKI2/I2C_1_SCL/GPIO_1_A/USB_DATA4_A PIU50M17 SPI_CLK
D7 P15 SPI_CLK SPI_CLK
DDRIO49PB0/MDDR_DQ7 PIU50D7 MSIO12PB2/SPI_0_CLK/USB_XCLK_A PIU50P15 NLSPI0SDI
SPI_SDI
D8 N15 SPI_SDI SPI_SDI
C DDRIO49NB0/MDDR_TMATCH_0_OUT PIU50D8 MSIO12NB2/SPI_0_SDI/GPIO_5_A/USB_DIR_A PIU50N15 NLSPI0SDO
SPI_SDO POSPI0INTERFACE0SPI0SS
POSPI0INTERFACE0SPI0SDO
POSPI0INTERFACE0SPI0SDI
POSPI0INTERFACE0SPI0CLK
POSPI0INTERFACE C
A8 L20 SPI_SDO SPI_SDO SPI_INTERFACE
DDRIO50PB0/MDDR_DQ5 PIU50A8 MSIO13PB2/SPI_0_SDO/GPIO_6_A/USB_STP_A PIU50L20
B8 L19
MSIO13NB2/SPI_0_SS0/GPIO_7_A/USB_NXT_A PIU50L19
SPI_SS NLSPI0SS
SPI_SS
DDRIO50NB0/MDDR_DQ6 PIU50B8
L15 SPI_SS
B6 MSIO14PB2/SPI_1_CLK PIU50L15
DDRIO51PB0/MDDR_DM_RDQS0 PIU50B6 L16 GPIO_11
B7 MSIO14NB2/SPI_1_SDI/GPIO_11_A PIU50L16 PWRGD_STATUS
DDRIO51NB0/MDDR_DQ4 PIU50B7 K20 GPIO_12
C6 MSIO15PB2/SPI_1_SDO/GPIO_12_A PIU50K20 NLPWRGD0B
PWRGD_B
DDRIO52PB0/MDDR_DQS0 PIU50C6 J20 GPIO_13 PWRGD_B
C7
PIU50C7 MSIO15NB2/SPI_1_SS0/GPIO_13_A PIU50J20 NLPWRGD0D
PWRGD_D
DDRIO52NB0/MDDR_DQS0_N J17 GPIO_17 PWRGD_D
A5 MSIO16PB2/SPI_1_SS4/GPIO_17_A PIU50J17 NLPWRGD0F POPWRGD0STATUS0PWRGD0F
POPWRGD0STATUS
PWRGD_STATUS
DDRIO53PB0/MDDR_DQ2 PIU50A5 J18 GPIO_18 PWRGD_F
A6 MSIO16NB2/SPI_1_SS5/GPIO_18_A PIU50J18 PWRGD_F
DDRIO53NB0/MDDR_DQ3 PIU50A6 K16 GPIO_23
E7 MSIO17PB2/SPI_1_SS6/GPIO_23_A PIU50K16 PWRGD_BOARD
DDRIO54PB0/MDDR_DQ0 PIU50E7
K15 GPIO_24
F8 MSIO17NB2/SPI_1_SS7/GPIO_24_A PIU50K15
DDRIO54NB0/MDDR_DQ1 PIU50F8 H19 GPIO_8
E6 MSIO18PB2/SPI_0_SS1/GPIO_8_A/USB_DATA5_A PIU50H19 POWER_ENABLES
DDRIO55PB0/CCC_NE0_CLKI3 PIU50E6 G18 GPIO_9
D5 MSIO18NB2/SPI_0_SS2/GPIO_9_A/USB_DATA6_A PIU50G18
DDRIO55NB0 PIU50D5 H17 GPIO_10 BOARD_ENABLE_N
A3 MSIO19PB2/SPI_0_SS3/GPIO_10_A/USB_DATA7_A PIU50H17
DDRIO56PB0/MDDR_DQ_ECC1 PIU50A3
H16 GPIO_14 FPGA_ENABLE
A4 MSIO19NB2/SPI_1_SS1/GPIO_14_A PIU50H16 NLON0B
DDRIO56NB0/MDDR_DQ_ECC0 PIU50A4 G19 GPIO_15 ON_B
D4 MSIO20PB2/SPI_1_SS2/GPIO_15_A PIU50G19 ON_B POPOWER0ENABLES0ON0F
POPOWER0ENABLES
POWER_ENABLES
DDRIO57PB0/MDDR_TMATCH_ECC_IN PIU50D4 F20 GPIO_16 NLON0D
ON_D
C5
PIU50C5 MSIO20NB2/SPI_1_SS3/GPIO_16_A PIU50F20 ON_D
DDRIO57NB0/MDDR_DM_RDQS_ECC NLON0F
ON_F
B3 ON_F
DDRIO58PB0/MDDR_DQS_ECC PIU50B3 M2S010-VF400
B4
DDRIO58NB0/MDDR_DQS_ECC_N PIU50B4
D A1 D
DDRIO59PB0/GB0 PIU50A1
B1
DDRIO59NB0/GB4 PIU50B1
C4 Title: HARSH Payload FPGA Banks 0_2 LIRMM - SPACERADGroup
DDRIO60PB0/MDDR_TMATCH_ECC_OUT PIU50C4
D3 UFSC - SpaceLab
DDRIO60NB0/CCC_NE1_CLKI3 PIU50D3 Project:HARSH_Payload.PrjPCB
M2S010-VF400 Date: 6/1/2020 Time: 3:23:16 PM Sheet 5 of 8 Institutional partnership project:
Model: HARSH_DB
1 2 3 4
1 2 3 4
MSIO BANKS (memories) HARNESS AND PORTS MSIOD BANKS (not used)
SDRAM data and control signals
A U5G A
C1 DQ2
MSIO64PB7 PIU50C1
U5E
BANK 7
C2 DQ12 MEM_DATA
MSIO64NB7 PIU50C2
R1
F6 DQ3 MSIOD100PB5 PIU50R1
BANK 5
MSIO67PB7 PIU50F6 NLDQ0

DQ0 R2
E5
PIU50E5 DQ13 NLDQ1
DQ1 DQ0 MSIOD100NB5 PIU50R2
MSIO67NB7 DQ1 P2
D2 NLDQ2
DQ2 MSIOD101PB5 PIU50P2
MSIO68PB7 PIU50D2
NLDQ3 DQ2 P3
E3 DQ1 DQ3 MSIOD101NB5 PIU50P3
MSIO68NB7 PIU50E3
NLDQ4
DQ4 DQ3
E1 NLDQ5 DQ4
MSIO70PB7 PIU50E1
DQ5
E2 DQ0 NLDQ6
DQ6 DQ5
MSIO70NB7 PIU50E2
DQ6 M2S010-VF400
MSIO71PB7
F3
PIU50F3 DQ10 NLDQ7
DQ7 POMEM0DATA0DQ15
POMEM0DATA0DQ14
POMEM0DATA0DQ13
POMEM0DATA0DQ12
POMEM0DATA0DQ11
POMEM0DATA0DQ10
POMEM0DATA0DQ9
POMEM0DATA0DQ8
POMEM0DATA0DQ7
POMEM0DATA0DQ6
POMEM0DATA0DQ5
POMEM0DATA0DQ4
POMEM0DATA0DQ3
POMEM0DATA0DQ2
POMEM0DATA0DQ1
POMEM0DATA0DQ0
POMEM0DATA
MEM_DATA
F4 DQ15 NLDQ8
DQ8 DQ7
MSIO71NB7 PIU50F4
NLDQ9
DQ9 DQ8
G6 DQ6
MSIO74PB7 PIU50G6 DQ10 DQ9
NLDQ10
F7 CS2_N DQ11 DQ10
NLDQ11
MSIO74NB7 PIU50F7
MSIO75PB7
G4
PIU50G4 CS1_N DQ12 DQ11
NLDQ12
F5 DQ7 DQ13 DQ12
NLDQ13
MSIO75NB7 PIU50F5
G2 DQ11 DQ14 DQ13
NLDQ14
U5F
MSIO78PB7/GB2 PIU50G2 DQ15 DQ14
NLDQ15
G3 DQ5 DQ15 H1
MSIO78NB7 PIU50G3
MSIOD82PB6 PIU50H1
BANK 6
G1 DQ4 H2
MSIO79PB7/GB1 PIU50G1
MSIOD82NB6 PIU50H2
F1 DQ14 J4
B MSIO79NB7 PIU50F1 MSIOD83PB6 PIU50J4
B
H5 DQML MEM_ADDR J5
MSIO80PB7 PIU50H5 MSIOD83NB6 PIU50J5
H4 DQMH NLA0
A0 J2
MSIO80NB7 PIU50H4
NLA1
A1 A0 MSIOD84PB6/CCC_NE1_CLKI2 PIU50J2
J7 DQ9 A1 J3
MSIO81PB7 PIU50J7
NLA2
A2 MSIOD84NB6 PIU50J3
H6 DQ8 NLA3 A2 K7
MSIO81NB7 PIU50H6 A3 MSIOD85PB6/CCC_NE1_CLKI1 PIU50K7
NLA4
A4 A3 J6
M2S010-VF400 NLA5 A4 MSIOD85NB6 PIU50J6
A5 K5
NLA6
A6 A5 MSIOD86PB6 PIU50K5
A6 K6
NLA7
A7 POMEM0ADDR0BA1
POMEM0ADDR0BA0
POMEM0ADDR0A12
POMEM0ADDR0A11
POMEM0ADDR0A10
POMEM0ADDR0A9
POMEM0ADDR0A8
POMEM0ADDR0A7
POMEM0ADDR0A6
POMEM0ADDR0A5
POMEM0ADDR0A4
POMEM0ADDR0A3
POMEM0ADDR0A2
POMEM0ADDR0A1
POMEM0ADDR0A0
POMEM0ADDR
MEM_ADDR MSIOD86NB6 PIU50K6
K2
NLA8
A8 A7 MSIOD87PB6 PIU50K2
NLA9
A9 A8 K3
PIU50K3
NLA10
A10 A9 MSIOD87NB6
SDRAM address and control signals A10 L6
NLA11
A11 MSIOD89PB6 PIU50L6
NLA12 A11 L7
COU5D
COU5E
COU5F
COU5G
U5D A12 MSIOD89NB6 PIU50L7
NLBA0
BA0 A12 L4
Y10 A5 BA0 MSIOD90PB6 PIU50L4
MSIO102PB4 PIU50Y10 NLBA1
BA1 L5
BANK 4
W10 A2 BA1 MSIOD90NB6 PIU50L5

MSIO102NB4/CCC_NE1_CLKI0 PIU50W10 L1
PIU50L1
Y11 PROBE_A MSIOD93PB6
MSIO103PB4/PROBE_A PIU50Y11 K1
W12 PROBE_B MSIOD93NB6 PIU50K1
MSIO103NB4/PROBE_B PIU50W12 MEM_CTRL M7
V11 BA1 MSIOD94PB6 PIU50M7
MSIO104PB4/GB3 PIU50V11
NLCKE
CKE M6
U11 A7 CKE MSIOD94NB6 PIU50M6
MSIO104NB4/GB7 PIU50U11 NLCLK
CLK M3
Y12 A11 NLCAS0N CLK MSIOD95PB6 PIU50M3
MSIO105PB4/CCC_NE0_CLKI0 PIU50Y12 CAS_N L3
PIU50L3
C Y13 BA0 NLRAS0N
RAS_N CAS_N MSIOD95NB6 C
MSIO105NB4 PIU50Y13 RAS_N M1
V12 A9 NLWE0N
WE_N MSIOD97PB6 PIU50M1
MSIO110PB4 PIU50V12 NLCS00N
CS0_N WE_N POMEM0CTRL0WE0N
POMEM0CTRL0RAS0N
POMEM0CTRL0DQML
POMEM0CTRL0DQMH
POMEM0CTRL0CS20N
POMEM0CTRL0CS10N
POMEM0CTRL0CS00N
POMEM0CTRL0CLK
POMEM0CTRL0CKE
POMEM0CTRL0CAS0N
POMEM0CTRL
MEM_CTRL M2
U12 A12 CS0_N MSIOD97NB6 PIU50M2
MSIO110NB4 PIU50U12 NLCS10N
CS1_N N4
W13 A10 NLCS20N
CS2_N CS1_N MSIOD98PB6 PIU50N4
MSIO112PB4 PIU50W13
CS2_N M4
W14 A8 NLDQMH
DQMH MSIOD98NB6 PIU50M4
MSIO112NB4 PIU50W14
NLDQML DQMH N1
PIU50N1
U13 A0 DQML MSIOD99PB6
MSIO113PB4 PIU50U13 DQML N2
T13 CAS_N MSIOD99NB6 PIU50N2
MSIO113NB4 PIU50T13
R13 RAS_N M2S010-VF400
MSIO114PB4 PIU50R13
R12 WE_N
MSIO114NB4 PIU50R12
V14 A3 LIVE_PROBES
MSIO115PB4 PIU50V14
U14 CS0_N NLPROBE0A
PROBE_A
MSIO115NB4 PIU50U14
PROBE_A
T14
PIU50T14 CLK NLPROBE0B POLIVE0PROBES0PROBE0B
POLIVE0PROBES0PROBE0A
POLIVE0PROBES
LIVE_PROBES
MSIO116PB4 PROBE_B
T15 CKE PROBE_B
MSIO116NB4 PIU50T15
Y15 A1
MSIO117PB4 PIU50Y15
Y16
MSIO117NB4 PIU50Y16
W15 A6
MSIO118PB4 PIU50W15
V15 A4
MSIO118NB4 PIU50V15
M2S010-VF400
D D
Title: HARSH Payload FPGA Banks 4_7 LIRMM - SPACERADGroup

Model: HARSH_DB
1 2 3 4
1 2 3 4
1V2_DVCC VPP AND VDD DECOUPLING CAPACITORS 3V3_DVCC FPGA POWER CONNECTIONS
1
90C29
PIC2COC29 PIC30 1 COC30
C30
PIC3101 COC31
C31
PIC3201 COC32
C32
PIC3 01COC33
C33
PIC3401 COC34
C34
PIC3501 COC35
C35
PIC3601 COC36
C36
PIC3701COC37
C37
PIC3801 COC38
C38
PIC3901COC39
C39
PIC40 1 COC40
C40 COC41
1 PIC4201COC42
PIC410C41 C42
PIC4301 COC43
C43
PIC4 01COC44
C44
PIC4501COC45
C45
A 2
PIC29047uF PIC30 2 4.7uF PIC3102 0.47uFPIC3202 0.47uF PIC3 02 0.47uFPIC3402 0.47uFPIC3502 0.47uFPIC3602 0.47uFPIC3702 0.47uFPIC3802 0.47uFPIC3902 0.47uF PIC40 2 0.47uFPIC41047uF
2 PIC4202 0.47uFPIC4302 0.47uFPIC4 02 0.47uFPIC4502 0.47uF Ground connections IO banks supply A
U5M U5L
A2 R9 UPD A7
PIU50A7 H18
PIU50H18
PIU50A2 VSS VSS PIU50R9 VDDI0 VDDI2 3V3_DVCC
GND GND A12 T1 A17 L17
PIU50A12 VSS VSS PIU50T1 PIU50A17 VDDI0 VDDI2 PIU50L17
B5 T2 B10 M20
PIU50B5 VSS VSS PIU50T2 PIU50B10 VDDI0 VDDI2 PIU50M20
B15 T3 C3
PIU50C3 N14
PIU50N14
PIU50B15 VSS VSS PIU50T3 VDDI0 VDDI2
C8 T4 C13
PIU50C13 P16
PIU50P16
PIU50C8 VSS VSS PIU50T4 VDDI0 VDDI2
FPGA CLOCK SUBSYSTEM REFERENCE VDDIO DECOUPLING CAPACITORS C18 T5 D6
PIU50D6 R19
PIU50R19
3V3_DVCC
PIU50C18 VSS VSS PIU50T5 VDDI0 VDDI2
D1 T6 D16 V18
PIU50D1 VSS VSS PIU50T6 PIU50D16 VDDI0 VDDI2 PIU50V18
3V3_DVCC D11 T7 E9
U5J PIU50D11 VSS VSS PIU50T7 PIU50E9 VDDI0
PIC4601 COC46
C46
PIC4701 COC47
C47 H14
E4
PIU50E4 VSS VSS
T9
PIU50T9 G8
PIU50G8 VDDI0 VDDI3
R14
PIU50R14
PIU50H14 CCC_NE0_NE1_MSS_MDDR_PLL_VDDA PIC4801COC48
C48
PIC4901 COC49
C49
PIC50 1 COC50
C50
E14
PIU50E14 VSS VSS
T10
PIU50T10
G10
PIU50G10 VDDI0
PIC4602 4.7uF PIC4702 0.47uF G13
F17
PIU50F17 VSS VSS
T16
PIU50T16
G12
PIU50G12 VDDI0 VDDI4
T12
PIU50T12
PIU50G13 CCC_NE0_NE1_MSS_MDDR_PLL_VSSA PIC4802 0.47uF PIC4902 0.47uF PIC50 2 0.47uF G9
PIU50G9 VSS VSS
T17
PIU50T17
B20
VDDI4
U15
PIU50U15
W11
GND G11 U1
M2S010-VF400 PIU50G11 VSS VSS PIU50U1 3V3_DVCC PIU50B20 VDDI1 VDDI4 PIU50W11
VDDIO3 VDDIO4 VDDIO7 G20 U2 E19 Y14
PIU50G20 VSS VSS PIU50U2 PIU50E19 VDDI1 VDDI4 PIU50Y14
H3 U3 G15
PIU50G15
PIU50H3 VSS VSS PIU50U3 VDDI1 NLUPD
H8 U4 R3
PIU50R3 UPD
PIU50H8 VSS VSS PIU50U4 VDDI5
H10 U6 PIR502
B PIU50H10 VSS VSS PIU50U6 B
FPGA JTAG INTERFACE HARNESS AND PORTS H12 U7 J1 COR5
R5
PIU50H12 VSS VSS PIU50U7 VDDI6 PIU50J1
H13 U8 F2 K4 10k
COU5H
COU5I
COU5J
COU5K
COU5L
COU5M
COU5N
U5H PIU50H13 VSS VSS PIU50U8 PIU50F2 VDDI7 VDDI6 PIU50K4
TDI V16 JTAG

J9
PIU50J9 VSS VSS
U9
PIU50U9
G5
PIU50G5 VDDI7 VDDI6
L8
PIU50L8 PIR501
PIU50V16 JTAG_TDI/M3_TDI NLTDI J11 U10 J8
PIU50J8 N3
PIU50N3
TDO Y20 TDI PIU50J11 VSS VSS PIU50U10 VDDI7 VDDI6
COR18
R18 PIU50Y20 JTAG_TDO/M3_TDO/M3_SWO NLTDO
TDO TDI J13 U20
TCK W19 TDO
PIU50J13 VSS VSS PIU50U20
GND PIR1802 PIR1801 PIU50W19 JTAG_TCK/M3_TCK NLTCK
TCK POJTAG0TMS
POJTAG0TDO
POJTAG0TDI
POJTAG0TCK
POJTAG
JTAG J16 V1 M2S010-VF400
TMS V17 NLTMS
TMS TCK PIU50J16 VSS VSS PIU50V1
GND
1K PIU50V17 JTAG_TMS/M3_TMS/M3_SWDIO TMS K8
PIU50K8 V2
PIU50V2
VSS VSS
K10 V3
W20 PIU50K10 VSS VSS PIU50V3
3V3_DVCC PIU50W20 JTAG_TRSTB/M3_TRSTB K12 V4
PIU50K12 VSS VSS PIU50V4
COR3
R3 PO3V30DVCC
3V3_DVCC 3V3_DVCC K14 V5 Core and general supply
U16
3V3_DVCC PIR302 PIR301 PIU50U16 JTAGSEL K19 V6
1K PO1V20DVCC L2 V7
M2S010-VF400 1V2_DVCC 1V2_DVCC PIU50L2 VSS VSS PIU50V7
L9 V8 U5K
PIU50L9 VSS VSS PIU50V8
L11 V9 H9 P9
PIU50L11 VSS VSS PIU50V9
1V2_DVCC PIU50H9 VDD VDD PIU50P9
L13 V10 H11 P11
PIU50L13 VSS VSS PIU50V10 PIU50H11 VDD VDD PIU50P11
M5 V13 J10 R7
PIU50M5 VSS VSS PIU50V13 PIU50J10 VDD VDD PIU50R7
M8 W1 J12 R8
OSCILLATORS AND RESET DO NOT CONNECT PINS PIU50M8
M10
VSS VSS PIU50W1
W3
PIU50J12 VDD VDD PIU50R8
PIU50M10 VSS VSS PIU50W3 K9
PIU50K9 VDD
R10
U5I M12 W5 VDD PIU50R10
C PIU50M12 VSS VSS PIU50W5 K11
PIU50K11 VDD
T8 C
M18
3V3_DVCC PIU50M18 N7 W7 VDD PIU50T8
SC_SPI_CLK PIU50N7 VSS VSS PIU50W7 K13 U5
L18 N9 W9
PIU50K13 VDD VDD PIU50U5
PIU50L18 SC_SPI_SDI U5N PIU50N9 VSS VSS PIU50W9 L10
N17 N11 W16
PIU50L10 VDD
PIU50N17 SC_SPI_SDO R4 G7 PIU50N11 VSS VSS PIU50W16 L12
PIU50L12 VDD J14
PIU50J14
PIR402 P17 PIU50R4 DNC NC PIU50G7
N13 Y1 VPP 3V3_DVCC
PIU50P17 SC_SPI_SS R5 G14 PIU50N13 VSS VSS PIU50Y1 M9
PIU50M9 VDD
P5
PIU50R5 DNC NC PIU50G14
N18 Y3 VPP PIU50P5
COR4
R4 W2 H7 PIU50N18 VSS VSS PIU50Y3 M11
PIU50M11 VDD
P14
D19 PIU50W2 DNC NC PIU50H7
P1 Y5 VPP PIU50P14
10k PIU50D19 FLASH_GOLDEN_N W4 H15 PIU50P1 VSS VSS PIU50Y5 M13 T11
PIR 401 PIU50W4 DNC NC PIU50H15
P4 Y7
PIU50M13 VDD VPP PIU50T11
0.47uF COC51C51 W6
PIU50W6 DNC
H20 PIU50P4 VSS VSS PIU50Y7 N6
PIU50N6 VDD
U17 NC PIU50H20
P8 Y9 N8 F10
GND PIC5101 PIC5102 PIU50U17 DEVRST_N W8 J15 PIU50P8 VSS VSS PIU50Y9 PIU50N8 VDD VREF0 PIU50F10
PIU50W8 DNC NC PIU50J15
P10 Y19 N10 F12
Y2 J19 PIU50P10 VSS VSS PIU50Y19 PIU50N10 VDD VREF0 PIU50F12
B2 PIU50Y2 DNC NC PIU50J19
P12 N12
Y4 K17
PIX10 PIU50B2 MDDR_IMP_CALIB_ECC PIU50Y4 DNC NC PIU50K17 PIU50P12
R6
VSS
M14
PIU50N12 VDD
1
COX1
X1 Y6 K18 PIU50R6 VSS VSSNVM PIU50M14 P7
PIU50P7 VDD
L14
Y18 PIU50Y6 DNC NC PIU50K18 VPPNVM PIU50L14 3V3_DVCC
PIU50Y18 XTLOSC_MAIN_XTAL Y8
PIU50Y8 DNC
M15
W18 NC PIU50M15
M2S010-VF400 M2S010-VF400
PIU50W18 XTLOSC_MAIN_EXTAL M16
NC PIU50M16
COX2 N5
GND
GND
X2 W17 NC PIU50N5
PIU50W17 XTLOSC_AUX_XTAL E20
PIU50E20 P6
PIU50P6
1 2 Y17 NC NC
PIX201 PIX202
PIU50Y17 XTLOSC_AUX_EXTAL F14 P13
PIU50F14 NC NC PIU50P13 GND
PIX104 PIX102 PIX103 32.768KHz M2S010-VF400
F19
PIU50F19 NC NC
R11
PIU50R11
4
2
D PIC5201 M2S010-VF400 D
COC52
C52
PIC5301 PIC5401 PIC5 01
COC53
C53 COC54
C54 COC55
C55
PIC5202 12pF PIC5302 12pF PIC5402 Title: HARSH Payload FPGA Miscellaneous LIRMM - SPACERADGroup
12pF PIC5 02 12pF
GND UFSC - SpaceLab
Size: A4 Project:HARSH_Payload.PrjPCB Revision: 1.1
Model: HARSH_DB
1 2 3 4
1 2 3 4
POWER CONVERTER (3V3 TO 1V2) BOARD LATCH-UP MONITOR 3V3_MEM_B MEMORY MODEL-B LATCH-UP MONITOR
Monitor bypass jumper (DO NOT PLACE) PIR1202 Monitor bypass jumper (DO NOT PLACE)
3V3_DVCC COJ0V3
J_V3 COR12
R12 COJ0V4
J_V4
A
4
COU6
U6
PIU604 VIN
3 1
COL1
L1
SW PIU603 PIL101 PIL102
2 PITP201 1V2_PVCC
SOURCE_VCC PIJ0V302
0R DNP
PIJ0V301 3V3_DVCC
PIR1201
1K 3V3_DVCC PIJ0V402
0R DNP
PIJ0V401 3V3_MEM_B A
PIR602 PIR601FPGA_ENABLE 1
PIU601 EN 2.2uH COTP2
IR802
PTP2
PIC5701 PID401
PIC5601
COR6
R6
COC56
PITP10
2
PIU602 GND
TLV62565DBVR
5
FB PIU605
PIR801
COR8
R8
120k
PIC5702
COC57
C57
10uF 1
PIU701
COU7
U7
D D
6
PIU706
Max Current: 1A
3V3_DVCC
COD4
D4
Green COU9
U9 Max Current: 0.5A
C56 COR7
R7 2 5
PIC5602 4.7uF PIU702 D D PIU705 1 6 3V3_MEM_B
PIR702 PIR701 PIU901 D D PIU906
COTP1
TP1 120k
3
PIU703 G S
4
PIU704 PITP401
COTP4
TP4
PID402 2
PIU902
3
D
5
D PIU905
4
SI1416EDH-T1-GE3 PIC60 1 PIU903 G S PIU904 PITP601
PGND PGND PGND PGND SOURCE_VCC COC60

C60 SI1416EDH-T1-GE3 COTP6
TP6
CORsense1 PIC60 2 10uF PIC6101
Rsense1 GND COC61
C61
PIRsense102 PIRsense101 COU8 10uF
50mR U8
7
PIC6102
6 GATE PIU807
3V3_DVCC COU10
U10
PIU806 SENSE 2
5 OUT PIU802 CORsense2
Rsense2 6 7
PIU805 IN PIRsense202 PIRsense201 PIU1006 SENSE GATE PIU1007
GND 5 2
PIU1002
POWER STATUS LEDS NOISE FILTERING FOR POWER SUPPLY COTP3
TP3 3 100mR PIU1005 IN OUT
PIU803 GATEP
8 PWRGD_BOARD GND
3V3_DVCC 1V2_DVCC
B 1V2_PVCC
COFB1
1V2_DVCC PIT 301 BOARD_ENABLE_NPIU801
1
PWRGD PIU808
4
COTP5
TP5
3
PIU1003 GATEP
8 PWRGD_B B
PIR902
COR9
R9
PIR10 2
COR10
R10
FB1
PIFB101 PIFB102
COR11
R11
ON GND PIU804
LTC4361ITS8-1#TRMPBF GND PIR1302
COR13
R13 PITP501
PIR1301 ON_B 1
PIU1001 ON
PWRGD
4
PIU1008
GND PIU1004 GND

.
30R@100Mhz, 3A
PIR1102 PIR1101 GND 100k
1K 1K 100k LTC4361ITS8-1#TRMPBF
PIR901 PIR10 1 PIC5801 PIC5901 COC59 GND
COC58
C58 C59
PID201 COD2
PID301 COD3
PIC5802 22uF PIC5902 22uF
D2 D3 COFB2
FB2
Green Green 3V3_MEM_D MEMORY MODEL-D LATCH-UP MONITOR 3V3_MEM_F MEMORY MODEL-F LATCH-UP MONITOR
.
PIFB201 PIFB202
30R@100Mhz, 3A
PID20 PID302 PIR1402
COR14
R14
Monitor bypass jumper (DO NOT PLACE)
COJ0V5
J_V5
PIR1602
COR16
R16
Monitor bypass jumper (DO NOT PLACE)
COJ0V6
J_V6
1K 3V3_DVCC PIJ0V502 PIJ0V501 3V3_MEM_D 1K 3V3_DVCC PIJ0V602 PIJ0V601 3V3_MEM_F
PGND GND
PIR1401 0R DNP PIR1601 0R DNP
GND GND
PID501 COD5
PID601 COD6
D5 D6
Green COU11 Green COU13
U13
U11
C HARNESS AND PORTS 1 6 3V3_MEM_D 1
PIU1301 D D
6
PIU1306 3V3_MEM_F C
PIU1101 D D PIU1106
NLPWRGD0B
PWRGD_B
PWRGD_STATUS PID502 2
PIU1102 D
3
5
D PIU1105
4
PID602 2
PIU1302
3
PIU1303 G
D D
5
PIU1305
4
PWRGD_B
PIU1103 G S PIU1104 PITP801 S PIU1304 PITP1001
NLPWRGD0D COTP8
PWRGD_D
NLPWRGD0F
PWRGD_F
PWRGD_D POPWRGD0STATUS0PWRGD0F
POPWRGD0STATUS
PWRGD_STATUS
SI1416EDH-T1-GE3
PIC6201
TP8 SI1416EDH-T1-GE3 PIC6301 COTP10
TP10
PWRGD_F GND COC62 GND COC63
C63
NLPWRGD0BOARD C62 10uF
PWRGD_BOARD
PWRGD_BOARD PIC6202 10uF PIC6302
3V3_DVCC COU12
U12 3V3_DVCC COU14
U14
POWER_ENABLES CORsense3
Rsense3 7 CORsense4
Rsense4 6 7
6 GATE PIU1207 PIRsense402 PIRsense401 PIU1406 SENSE GATE PIU1407
NLBOARD0ENABLE0N
BOARD_ENABLE_N PIRsense302 PIRsense301 PIU1206 SENSE 2 2
BOARD_ENABLE_N 100mR 5 OUT PIU1202 100mR 5 OUT PIU1402
NLFPGA0ENABLE
FPGA_ENABLE PIU1205 IN PIU1405 IN
FPGA_ENABLE GND GND
NLON0B
ON_B 3 3
ON_B POPOWER0ENABLES0ON0F
POPOWER0ENABLES
POWER_ENABLES COTP7
TP7 PIU1203 GATEP COTP9
TP9
PIU1403 GATEP
NLON0D
ON_D 8 PWRGD_D 8 PWRGD_F
NLON0F
ON_F
ON_D
ON_F
GND PIR1502
COR15
R15
PIR1501
PITP701 ON_D 1
PIU1201 ON
PWRGD
4
GND PIU1204
PIU1208
GND GND PIR1702

COR17
R17
PIR1701
PITP901 ON_F 1
PIU1401 ON
PWRGD
4
GND PIU1404
PIU1408
GND
100k 100k
LTC4361ITS8-1#TRMPBF LTC4361ITS8-1#TRMPBF
PO3V30DVCC
3V3_DVCC 3V3_DVCC PO3V30MEM0B
3V3_MEM_B 3V3_MEM_B
D D
PO1V20DVCC
1V2_DVCC 1V2_DVCC PO3V30MEM0D
3V3_MEM_D 3V3_MEM_D
Title: HARSH Payload Power Supply LIRMM - SPACERADGroup
POSOURCE0VCC
SOURCE_VCC SOURCE_VCC PO3V30MEM0F
3V3_MEM_F 3V3_MEM_F Project:HARSH_Payload.PrjPCB UFSC - SpaceLab
Model: HARSH_DB
1 2 3 4
COM1 COM4 COM1 COM4
PAD102 PAD102
PAM100 PAP2017
PAP504 PAP505 PAP307 PAP2016 PAD101PAR201 PAR202 PAU2054PAU2053PAU2052PAU2051PAU2050PAU2049PAU2048PAU2047PAU2046PAU2045PAU204 PAU2043PAU2042PAU2041PAU204 PAU2039PAU2038PAU2037PAU2036PAU2035PAU2034PAU203 PAU2032PAU2031PAU2030PAU2029PAU2028 PAM400
PAP308 COD1
COR2 PAC602 PAC601PAC201 PAC202 PAC501 PAC502
COC6 COC2 COC5
COFD6 PAFD601
PAM100 PAP2017
PAP504 PAP505 PAP307 PAP2016 PAD101PAR201 PAR202 PAU2054PAU2053PAU2052PAU2051PAU2050PAU2049PAU2048PAU2047PAU2046PAU2045PAU204 PAU2043PAU2042PAU2041PAU204 PAU2039PAU2038PAU2037PAU2036PAU2035PAU2034PAU203 PAU2032PAU2031PAU2030PAU2029PAU2028 PAM400
PAP308 COD1
COR2 PAC602 PAC601PAC201 PAC202 PAC501 PAC502
COC6 COC2 COC5
COFD6 PAFD601
COP1
PAP101 PAFD101
COP5 PAP25015 PAP2P051042 PPAP503
PAR101 PAR102
AP2013 PAP2012 PAP201 PAP2010 PAP209 PAP208 PAP207 PAP301
PAP206 PAP32025 PAP32034 PAP32043 PAP32052 PAP32061
COP3
PAR302PAX103PAR402PAX102
PAC5301
COP2 COC52
PAC5202
COJ0V4 PAJ0V402 PAR1202COU10 COC61
COFD3
PAJ0V401 PAC6101 PAC6102
PAFD301 COR12
COP1
PAP101 PAFD101
COP5 PAP25015 PAP2P051042 PPAP503
PAR101 PAR102
AP2013 PAP2012 PAP201 PAP2010 PAP209 PAP208 PAP207 PAP301
PAP206 PAP32025 PAP32034 PAP32043 PAP32052 PAP32061
COP3
PAR302PAX103PAR402PAX102
PAC5301
COP2 COC52
PAC5202
COJ0V4 PAJ0V402 PAR1202COU10 COC61
COFD3
PAJ0V401 PAC6101 PAC6102
PAFD301 COR12
COR1 PAC5502 PAX104PAR401PAX101 PAC5201 COC8 COC3 PAR1301 PAU10 1PAU10 2PAU1PAR1201 0 3PAU10 4 CORs2 COR1 PAC5502 PAX104PAR401PAX101 PAC5201 COC8 COC3 PAR1301 PAU10 1PAU10 2PAU1PAR1201 0 3PAU10 4 CORs2
PAP102 COFD1 PAU105PAU106PAU107PAU108 PAP102 COFD1 PAU105PAU106PAU107PAU108
COC54 PAC5402 PAC5401 PAX201 PAX202COC5 PAC5501 COC53 COC54 PAC5402 PAC5401 PAX201 PAX202COC5 PAC5501 COC53
COX2 PAR301 COX2 PAR301
PAR1802 PAR1801 PAC5302
COR3 COR4 COX1 COU2 PAC801 PAC301
COC4 COC7 C O R 1 3 PAR1302 PAU10 8PAU10 7PAU10 6PAU10 5 PARs202 PAD401
COD4
PAR1802 PAR1801 PAC5302
COR3 COR4 COX1 COU2 PAC801 PAC301
COC4 COC7 C O R 1 3 PAR1302 PAU10 8PAU10 7PAU10 6PAU10 5 PARs202 PAD401
COD4
PAP103 COFD4 PAU104PAU103PAU102PAU101 COU1 PAP103 COFD4 PAU104PAU103PAU102PAU101 COU1
COR18 PAC401 PAC701 COR18 PAC401 PAC701
COC43 PAC4301PAC4302 COC44 AU201PAU202PAC302
PPAC802 PAU203PAU204PAU205PAU206PAU207PAC402
PAU50A20 PAU50B20 PAU50C20 PAU50D20 PAU50E20 PAU50F20 PAU50G20 PAU50H20 PAU50J20 PAU50K20 PAU50L20 PAU50M20 PAU50N20 PAU50P20 PAU50R20 PAU50T20 PAU50U20 PAU50V20 PAU50W20 PAU50Y20
PAU208PAU2PAC702 09PAU2010PAU201 PAU2012PAU2013PAC901 PAU2014COC9 U2016PAU2017PAU2018PAU2019PAU20 PAU2021PAU20 2PAU2023PAU2024PAU2025PAU2COC10
PAU2015PAPAC902 026PAU2027 PAC1002 PAU904PAU905PAD402 PAU906 PARs201 COC43 PAC4301PAC4302 COC44 AU201PAU202PAC302
PAU208PAU2PAC702 09PAU2010PAU201 PAU2012PAU2013PAC901 PAU2014COC9 PAU2015PAPAC902 U2016PAU2017PAU2018PAU2019PAU20 PAU2021PAU20 2PAU2023PAU2024PAU2025PAU2COC10 026PAU2027 PAC1002 PAU904PAU905PAD402 PAU906 PARs201
PAP104 PAFD401 COP6PAC101 PAC102 COC1 PAC4802

PAC4402 PAC4401 PAC4801 PAC5102 COC51
PAU3054PAU3053PAPAC1502 U3052PAU3051PAU3PAC1501
050PAU3049PAC1101PAU3048PAU3047PAPAC1102 U3046PAU3045PAU30PAC1401 4 PAU3043PAU3042PAC1402 PAU3041PAU3040PAU3039PAU3038PAU3037PAU3036PAU3035PAU3034PAU303 PAU3032PAU3031PAU3030PAU3029COC62
PAC1001
PAU3028 PAU903PAU902PAU901 COU9 PAP104 PAFD401 COP6PAC101 PAC102 COC1 PAC4802
PAU3054PAU3053PAPAC1502 U3052PAU3051PAU3PAC1501
050PAU3049PAC1101
PAU3048PAU3047PAPAC1102 U3046PAU3045PAU30PAC1401 4 PAU3043PAU3042PAC1402 PAU3041PAU3040PAU3039PAU3038PAU3037PAU3036PAU3035PAU3034PAU303 PAU3032PAU3031PAU3030PAU3029COC62
PAC1001
PAU3028 PAU903PAU902PAU901 COU9
PAU50A17 PAU50B17 PAU50C17 PAU50D17 PAU50E17 PAU50F17 PAU50G17 PAU50H17 PAU50J17 PAU50K17 PAU50L17 PAU50M17 PAU50N17 PAU50P17 PAU50R17 PAC5101PAU50T17 PAU50U17 PAU50V17 PAU50W17 PAU50Y17 PAC4902 PAU50A17 PAU50B17 PAU50C17 PAU50D17 PAU50E17 PAU50F17 PAU50G17 PAU50H17 PAU50J17 PAU50K17 PAU50L17 PAU50M17 PAU50N17 PAU50P17 PAU50R17 PAC5101PAU50T17 PAU50U17 PAU50V17 PAU50W17 PAU50Y17 PAC4902
PAP105 PAP6019 PAP60AT PAP6020
PAP6017 PAP6018 PAU50A15 PAU50B15 PAU50C15PAC4502 PAC4501PAU50F15COC45
PAU50D15 PAU50E15 C O C 3 2 C 4
PAU50M15 PAU50N15COPAU50P158 O C 4
PAU50R15 PAU50T15 PAU50U15 PAU50V15 PAU50W15CPAU50Y15 9
PAU50G15 PAU50H15 PAU50J15 PAU50K15 PAU50L15
PAC4901 COC15 COC11 COC14 COU12 PAC6201 PAC6202 PAP105 PAP6019 PAP60AT PAP6020
PAP6017 PAP6018 PAU50A15 PAU50B15 PAU50C15PAC4502 PAC4501PAU50F15COC45
PAU50D15 PAU50E15 C O
PAU50G15 PAU50H15 PAU50J15 PAU50K15 C 3 2
PAU50L15 C 4
PAU50M15 PAU50N15COPAU50P158 O C 4
PAU50R15 PAU50T15 PAU50U15 PAU50V15 PAU50W15CPAU50Y15 9
PAC4901 COC15 COC11 COC14 COU12 PAC6201 PAC6202
PAP6015 PAP6016 PAC4701 PAC4702 COC47 PAC3201 PAU50A14 PAU50B14 PAU50C14 PAU50D14 PAU50E14 PAU50F14 PAU50G14 PAU50H14 PAU50J14 PAU50K14 PAU50L14 PAU50M14 PAU50N14 PAU50P14 PAU50R14 PAU50T14 PAU50U14 PAU50V14 PAU50W14 PAU50Y14
PAR1501 PAU1201PAU1202PAU1PAR1402 203PAU1204 CORs3 PAP6015 PAP6016 PAC4701 PAC4702 COC47 PAC3201 PAU50A14 PAU50B14 PAU50C14 PAU50D14 PAU50E14 PAU50F14 PAU50G14 PAU50H14 PAU50J14 PAU50K14 PAU50L14 PAU50M14 PAU50N14 PAU50P14 PAU50R14 PAU50T14 PAU50U14 PAU50V14 PAU50W14 PAU50Y14
PAR1501 PAU1201PAU1202PAU1PAR1402 203PAU1204 CORs3
PAP106 PAP6013
PAP6011 PAP6012
PAP6014 PAC4601 PAC4602 COC46 PAC3202COC36COC38COC42 PAU50A12 PAU50B12 PAU50C12
PAU50A11 PAU50B11 PAU50C11
PAU50D12 PAU50E12
PAU50D11 PAU50E11
PAU50F12 PAU50G12 PAU50H12 PAU50J12 PAU50K12
PAU50L12 PAU50M12
PAU50L11 PAU50M11
PAU50N12 PAU50P12
PAU50N11 PAU50P11
PAU50R12 PAU50T12
PAU50R11 PAU50T11
PAU50U12 PAU50V12 PAU50W12 PAU50Y12
COR15 PAR1502 PAU1208PAU1207PAU1PAR1401 COR14 PAP106 PAP6013
PAP6011 PAP6012
PAP6014 PAC4601 PAC4602 COC46 PAC3202COC36COC38COC42 PAU50A12 PAU50B12 PAU50C12
PAU50D12 PAU50E12
PAU50D11 PAU50E11
PAU50L12 PAU50M12
PAU50L11 PAU50M11
PAU50N12 PAU50P12
PAU50N11 PAU50P11
PAU50R12 PAU50T12
PAU50R11 PAU50T11
COR15 PAR1502 PAU1208PAU1207PAU1PAR1401 COR14
PAP609 PAP6010 COC31 PAC3102 PAC3101 PAC3701 PAC3702
PAU50A10 PAU50B10 PAU50C10PAC3602 PAC3601
PAU50D10 PAU50E10 PAC3801 PAC3802 PAC4202
PAU50F10 PAU50G10 PAU50H10 PAU50J10 PAU50K10 PAC4201
PAU50L10 PAU50M10 PAU50N10 PAU50P10 PAU50R10 PAU50T10 PAU50U10 PAU50V10 PAU50W10 PAU50Y10 206PAU1205 PARs302 PAP609 PAP6010 COC31 PAC3102 PAC3101 PAC3701 PAC3702
PAU50A10 PAU50B10 PAU50C10 PAC3602
PAU50D10 PAU50E10 PAC3601 PAC3801 PAC3802
PAU50F10 PAU50G10 PAU50H10 PAU50J10 PAU50K10 PAC4202 PAC4201
PAU50L10 PAU50M10 PAU50N10 PAU50P10 PAU50R10 PAU50T10 PAU50U10 PAU50V10 PAU50W10 PAU50Y10 206PAU1205 PARs302
PAP107 PAP607 PAP608 PAC3001
PAC4001 COC37 PAC3501
PAC3502 COC35
PAU50A9 PAU50B9 PAU50C9 PAU50D9 PAU50E9 PAU50F9 PAU50G9 PAU50H9 PAU50J9 PAU50K9 PAU50L9 PAU50M9 PAU50N9 PAU50P9 PAU50R9 PAU50T9 PAU50U9 PAU50V9 PAU50W9 PAU50Y9 PAD501 PAP107 PAP607 PAP608 PAC3001
PAC4001 COC37 PAC3501
PAC3502 COC35
PAU50A9 PAU50B9 PAU50C9 PAU50D9 PAU50E9 PAU50F9 PAU50G9 PAU50H9 PAU50J9 PAU50K9 PAU50L9 PAU50M9 PAU50N9 PAU50P9 PAU50R9 PAU50T9 PAU50U9 PAU50V9 PAU50W9 PAU50Y9 PAD501
COC39 PAC3901PAC3902COU3 PAC1701COC17 PAC1201COC12 PAC1301COC13 PAC1601COC16 COJ0V5 PAJ0V502 PAU1104PAU1105PAU1106 PARs301 COD5
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Development of A Satellite Radiation Experiment For Evaluating SDRAM Memories in Harsh Environments

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Development of A Satellite Radiation Experiment For Evaluating SDRAM Memories in Harsh Environments

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FEDERAL UNIVERSITY OF SANTA CATARINA

Development of a satellite radiation experiment for

Undergraduate Dissertation presented to the Federal University of Santa

André Martins Pio de Mattos

Supervisor: Eduardo Augusto Bezerra, Ph.D.

DEVELOPMENT OF A SATELLITE RADIATION

Undergraduate Dissertation pre-

Mattos, André Martins Pio de

Trabalho de Conclusão de Curso (graduação) -

1. Engenharia Eletrônica. 2. Sistemas embarcados. 3.

DEVELOPMENT OF A SATELLITE RADIATION

Este Trabalho de Conclusão de Curso foi julgado adequado para a

Florianópolis, 24 de setembro de 2021

Electronics in the context of space applications require attention to per-

Sistemas eletrônicos no contexto de aplicações espaciais requerem es-

O crescente mercado de pequenos satélites [1] está liderando uma rápida

Assim, avaliar a vulnerabilidade desses componentes devido à exposição à

SEE Single Event Effect.

6.1 Memory controller simulation flow. . . . . . . . . . . . . . . 55

List of Figures iii

5.3.2 Design Overview . . . . . . . . . . . . . . . . . . . . 34

A Payload hardware schematics 73

to determine the efforts that should be applied during the development.

1.2 Work Outline

2.1 Experimental setup

2.2 Hardware development

2.3 Firmware development

2.4 SoC FPGA development

of integrating different available blocks (e.g., memory controller, micro-

2.5 Project management

Source: SpaceLab, 2020.

3.2 Radiation Effects

that causes shift in the transistors threshold voltage, increase of leakage

3.3 SDRAM Memories

These devices are susceptible to harsh radiation environments and many

3.4 FPGA Devices

Source: allaboutfpga, 2021.

The FPGAs core structure can be combined with other technologies

[7], which internal architecture combine several elements to attend the

3.5 PCB Principles

Source: PCBWay, 2020.

4.1 Environmental Parameters

Figure 4.1: A preview of the satellite simulated groundtrack.

Source: SpaceLab, 2021

sequence of the magnetic interactions. The lower energy, although still

Source: Wikipedia, 2021

In order to characterize these belts and evaluate the ionizing parti-

Source: V. Pierrard et al., 2016

Thermal and Mechanical Analysis

A comprehensive thermal analysis for FloripaSat-1 mission was carried

ations are summarized throughout the document, in the design robustness

4.2 Memory Experiment Analysis

Source: D. Söderström et al., RADECS, 2019

4.3 Payload Specification

REQ-PAY-000 The payload shall be compliant with the CubeSat standard

REQ-ENV-000 The payload components shall be selected in order to reduce

REQ-PER-000 The memory controller must be able to operate in the memo-

5.1 System Overview

is provided to ease the understanding of the project evolution and an itera-

Features and standards Prototype Engineering Model Flight Model

During the prototyping phase, the base architecture and components of

have an embedded ARM Cortex-M3 processor, several useful on-chip pe-