EX.

NO:13
DESIGN AND IMPLEMENTATION OF COUNTERS USING 7 SEGMENT
DATE: DISPLAY IN FPGA

Aim
To design, simulate and implement counters using 7 segment display in FPGA.
Software Required
 Vivado 2014.4

Hardware Required
 Nexys A7: FPGA Trainer Board

Theory

A 7-segment display in an FPGA involves combining the concepts of counters and 7-segment
display decoding to create a functional and visually appealing display of count values. Here are the key
theoretical aspects:

Counters:
Counters are sequential circuits that generate a sequence of binary values based on a clock signal.
In the context of FPGA implementation, counters are typically implemented as finite state machines (FSMs)
with flip-flops and combinational logic. Counters can be designed to count up (increment) or count down
(decrement) based on specific triggering events, such as clock pulses or control signals.

Binary to 7-Segment Display Decoding:

A 7-segment display is composed of seven individual segments labeled a, b, c, d, e, f, and g. Each
segment can be illuminated or turned off independently. To display a specific digit (0-9) or character (A-F,
for example), the corresponding segments need to be activated. Binary to 7-segment display decoding is
the process of mapping a binary value (count value) to the appropriate segment patterns required to display
the desired digit or character on the 7-segment display.

Segment Patterns:
Each digit or character on a 7-segment display can be represented by activating specific segments.
For example, the number "0" is displayed by activating segments a, b, c, d, e, f but leaving segment g off.
Different digits and characters have different segment activation patterns. These patterns can be stored in a
lookup table or implemented as combinational logic to enable the correct segments for each count value.

Multiplexing:
In cases where multiple 7-segment displays are used, multiplexing is a technique employed to share
limited resources (pins) of the FPGA. It involves rapidly switching between different displays and
displaying their respective count values one at a time. By multiplexing, it appears as if all the displays are
active simultaneously. Multiplexing can be achieved using a time-multiplexing approach, where each
display is activated for a short period and then switched to the next display.
Counters

Block Diagram

Program Test bench Program

module SevenSegmentDisplay ( module SevenSegmentDisplay_TB;
input wire [3:0] count, reg [3:0] count;
output wire [6:0] seg wire [6:0] seg;
// Instantiate the module under test
);
SevenSegmentDisplay dut (
// Segment patterns for digits 0 to 9 .count(count),
reg [6:0] segment_patterns [9:0] = .seg(seg)
{ );
7'b111_1110, // 0 // Clock signal generation
7'b011_0000, // 1 reg clk;
7'b110_1101, // 2 always #5 clk = ~clk;
// Testbench stimulus
7'b111_1001, // 3
initial begin
7'b011_0011, // 4 clk = 0;
7'b101_1011, // 5 count = 0;
7'b101_1111, // 6 #10;
7'b111_0000, // 7 $display("Count: %d, Seg: %b", count, seg);
7'b111_1111, // 8 // Test case: Count from 0 to 9
7'b111_1011 // 9 repeat(10) begin
#20;
};
count = count + 1;
$display("Count: %d, Seg: %b", count, seg);
assign seg = segment_patterns[count]; end
endmodule // Test case: Count from 9 to 0
repeat(10) begin
#20;
count = count - 1;
$display("Count: %d, Seg: %b", count, seg);
end
$finish;
end
always @(posedge clk) begin
#1;
end
endmodule
Procedure
1. Double Click on “ vivado2014.4”
2. Clickcreate new project
3. Clicknext
4. Enter your project name,and click, next.,
5. Select “RTL project” and click next.,
6. Click create file
7. Select your file type as Verilog
8. Enter your “file name” and click ok.,
9. Clicknext.,
10. Click next.,
11. Create xdc file
11.a, Clickcreate file.,
11.b. Enter your “xdc name” and click ok.,
12. Clicknext.,
13. Select your ic details.,(ex:Nexys A7” xc7a100tcpg324-1”)
14. Click finish.,
15. Enter your input and output details and click ok, else click cancel directly enter your program and
declare your input output
16. Goto project manager and click your verilog file under Design Sources.,
17. Enter your program and save file.

Steps for Test bench creation

1. Goto project manager  right click on Simulation SourcesSelect Add or create simulation
sources,
2. Click on Create File  Select your file type as Verilog
3. Enter your “file name” and click Finish.,
4. Goto project manager and click your verilog file under Simulation Sources.,
5. Enter your program and save file.,
6. Click on”run synthesis”Running synthesis.,

Steps for Simulation

1. After successful synthesis completion, close the pop-up window and select Simulation  Run
Behavioural Simulation is enough to see output waveform If we run through testbench program.
2. Else After the Run Behavioral Simulation, Force the value for inputs by Force Constant option
and save the waveform
3. Run the simulation by clicking on Run for amount of time previously set Output of simulation is
verified with the help of waveform
Steps for Implementation

1. Click open synthesis design and click ok.,

2. Create floor plan details
a. Clickconstraints wizard
b. Click define target
c. Select your xdc file and click ok.,
d. Click schematic(F4)
e. ClickI/O Ports
f. Enter your pin details.,
g. Select I/O STDLVCMOS33
h. Clicksave, and yes,
3. Clickrun implementation
4. ClickGenerate Bitstream and click “open target”
5. Opentargetopen new target.,
6. ClickAuto connect.,
7. Clickprogram deviceselect your device
8. Clickprogram

Output

Result
Thus, the simulation and implementation of counters using 7 segment display in FPGA is verified.

Inference from the Result:

Practice Question

1. Implement an alphabetical characters using an FPGA and display on a 7-segment display.