EEE 303 : Digital Electronics

Week 4
Timing, Delay and Glitches
Reference Text: Harris section 2.9
Propagation & Contamination Delay
 Delay: Why does it occur?
• Electrons need time to move
• Capacitive effects are present
 Delay: Why are we concerned?
• Propagation delay tells us the time for waiting
before a stable output is produced, which is
connected to the maximum frequency at
which a device can function correctly
• Contamination delay tells us the time after
when output may erroneously change (glitch)
which eventually affects inputs and outputs of
next stages
 Critical Path & Short Path
• Critical Path: The path with highest delay
• Short Path: The path with lowest delay
• Propagation Delay : Sum of propagation delays
of all elements along critical path
• Contamination Delay: Sum of contamination
delays of all elements along short path
 Example 1

Find out critical path & Short path. Also calculate propagation
delay and contamination delay of the circuit. What is the maximum
frequency at which this circuit can reliably operate?

Assume both AND gate and OR gate has propagation delay of 50ps
and contamination delays of 20ps.
 Example 1 assumed
equal delay for each gate
What if delays are different for different gates?

Example 2: Finding Propagation delay

of a 4:1 multiplexer
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

S : Selector/ Control Signal

D: Data Signal
Example 2: Different Implementations
of 4:1 Multiplexer
Example 2: Two level Logic
Finding Propagation Delay
For each (input,output) pair, find
propagation delay
Propagation delay of whole circuit
is the maximum of all propagation delays

There are 2 control inputs and 4

data inputs in this circuit.
So 6 input,output pairs are
possible. All control to output
pairs have
same propagation delay. All data
to output pairs have same
propagation
delay. So calculating propagation
delay for only 2 pair are sufficient
Example 2: Two level Logic
Finding Propagation Delay
Example 2: Two level Logic
Finding Propagation Delay

This implementation is said Control-critical

Example 2: Hierarchical Logic
Finding Propagation Delay
Example 2: Hierarchical Logic
Finding Propagation Delay

This implementation is said Data-critical

 Example 2: Selecting Design
when an input arrives early
• Say, the control inputs arrive early, which
design should we choose?
--- We should choose the design with shortest
data to output delay
• If data inputs arrive early, what should we do?
--- Should choose the design with shortest
control to output delay
 Glitches
• A change in input, I may/ may not change the
output, O. But if the input I is used in multiple
paths and these paths take different amount
of time to propagate to output, the output O
may change erroneously.
 Glitch: Example

Suppose, ABC=011, so Y=1

Now B changes from 1 to 0, so Y should still be 1
But does it happen in reality?
Glitch: Example
B is used in multiple paths:
here both in Critical and
Short Path.

Before n1 can change, n2

changes and since the change
in input B has not propagated
through all possible paths,
output Y erroneously falls to
zero for some time. This is
the glitch.

But as soon as n1 changes,

output Y gains its correct
value.
Possibility of Glitch: Visualizing from K
Map
• Glitch occurs when output has this sequence:
correct value wrong value(glitch) correct value
which indicates in this case, output should not alter its
value when input changes
• This can happen when there are two adjacent boxes of
1s(for SOP) or 0s(for POS)in K Map, but they do not
overlap [same variable appears in true &
complemented form in multiple terms & hence
connected to output through multiple paths. So change
in that variable takes different times to propagate to
output through different branches. Output erroneously
alters although it should not alter]
Glitch: Example (Visualizing from K
Map)
 Glitch: Solution
• Make a box that connects the boundary of
two adjacent boxes which increases cost
• Due to this new box, an extra term will come
into expression that will not depend upon the
input variable that caused glitch
• So even when the glitch causing input
changes, the output will stay unaltered due to
the extra term
 Glitch: Example
(Glitch free circuit)