Chapter 2 - Central Processing Unit

- Case Study
Prepared By:
BIJAY MISHRA
(बिजय मिश्र)
biizay@gmail.com
@jijibisha
Chapter 2 - Central Processing Unit - Case Study 15 Hrs.

2.1 Arithmetic and Logic Unit (ALU)

2.2 Instruction Sets
2.3 Addressing Modes and Formats
2.4 Stack
2.5 Processor Organization
2.6 Register Organization
2.7 Instruction Cycle
2.8 Pentium Processor
2.9 Power PC Processor
What’s a CPU?
• A central processing unit (CPU) is the heart of all modern digital
computers.
• A CPU is a complex arrangement of combinational and sequential logic…
• combinational: outputs depend only on current inputs
• sequential: has memory, is normally controlled by a clock
• It works as a simple function:
• fetch instruction  decode instruction  execute instruction
• Each instruction is a simple operation on binary symbols
• e.g., add two numbers together, take the logical and of two bit patterns, read from
or write to memory, etc.
• Almost all modern CPUs are implemented as microprocessors, that is, as
single integrated circuits
Major CPU components
• Register section
• contains registers (memory local to the CPU)
necessary for CPU functioning, including
programmer-visible registers and internal
registers
• CPU interconnect (Bus)
Registers
ALU

• interconnects the registers and connects to

memory
• Arithmetic-logic unit (ALU)
Control Unit
• contains circuitry to perform data manipulation
operations (ADD, AND)
• Control unit (CU)
• provides appropriate signals to allow the CPU to
step through its required operational states
ARITHMETIC LOGIC UNIT
 ARITHMETIC LOGIC UNIT
Some facts in arithmetic logic shift unit that need to be considered:
i. Input Ai and Bi are applied to both the arithmetic and logic units. A particular micro-
operation is selected with inputs S1 and S0.
ii. A 4x1 MUX at the output chooses between an arithmetic output in Di and a logic
output in Ei.
iii. The data inputs to the multiplexer are selected with inputs S3 and S2.
iv. The other two data inputs to the MUX receive inputs Ai-1 for the shift right operation
and Ai+1 for the shift left operation.
v. Cin is the selection variable for the arithmetic operation.
vi. The circuit provides eight arithmetic operation, four logic operations and two shift
operations.
vii.Each operation is selected with the five variables s3, s2, s1, s0 and cin.
viii.The input carry cin is used for arithmetic operations only.
ARITHMETIC LOGIC UNIT
COMPUTER INSTRUCTIONS
• Program
• A sequence of (machine) instructions
• (Machine) Instruction
• A group of bits that tell the computer to perform a specific operation (a sequence of micro-
operation)
• The instructions of a program, along with any needed data are stored in
memory
• The CPU reads the next instruction from memory and is placed in an
Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it
INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
• An opcode (Operation Code) that specifies the operation for that instruction
• An address that specifies the registers and/or locations in memory to use for that operation
• A mode field that determines how the address field is to be interpreted (to get effective address or
the operand)

Instruction Format

15 14 12 11 0

I Opcode Address

Addressing
mode

• The number of address fields in the instruction format depends on the internal organization of CPU
 CPU Organization (Processor Organization)
• In general, most processors are organized in one of 3 ways
• Single register (Accumulator) organization
• Basic Computer is a good example
• Accumulator is the only general purpose register
• General register organization
• Used by most modern computer processors
• Any of the registers can be used as the source or destination for computer
operations
• Stack organization
• All operations are done using the hardware stack
• For example, an OR instruction will pop the two top elements from the stack, do a
logical OR on them, and push the result on the stack
Advantages and Disadvantages of CPU Organization Approaches
Stack organization
Advantages: Simple Model of expression evaluation (reverse polish). Short instructions.
Disadvantages: A stack can't be randomly accessed and this makes it hard to generate
efficient code. The stack itself is accessed every operation and becomes a bottleneck.

Accumulator organization
Advantages: Short instructions.
Disadvantages: The accumulator is only temporary storage so memory traffic is the
highest for this approach.

General register organization

Advantages: Makes code generation easy. Data can be stored for long periods in
registers.
Disadvantages: All operands must be named leading to longer instructions.
CPU Organization (Processor Organization)
Single accumulator organization:
ADD X /* AC  AC + M[X] */

General register organization:

ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */

Stack organization:
PUSH X /* TOS  M[X] */
ADD
THREE AND TWO-ADDRESS INSTRUCTIONS
• Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

• Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
ONE AND ZERO-ADDRESS INSTRUCTIONS
• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
BASIC COMPUTER INSTRUCTIONS

Memory-Reference Instructions (OP-code = 000 - 110)

15 14 12 11 0 If I = 0, the instruction uses direct addressing.
I Opcode Address
If I = 1, addressing in indirect addressing.

Register-Reference Instructions
15 12 11 0
0 1 1 1 Register operation (OP-code = 111, I = 0)

Input-Output Instructions
15 12 11 0
1 1 1 1 I/O operation
(OP-code =111, I = 1)
BASIC COMPUTER INSTRUCTIONS

Memory-Reference Instructions

Register-Reference Instructions

Input-Output Instructions
INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to be computable.

• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
ADDRESSING MODES

• The addressing mode specifies a rule for interpreting or modifying the address field of
the instruction before the operand is actually referenced.
• The decoding step in the instruction cycle determines the operation to be performed, the
addressing mode of the instruction, and the location of the operands.

Purpose of addressing modes:

- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
• The address field of an instruction can represent either
• Direct address: the address in memory of the data to use (the address of the operand), or
• Indirect address: the address in memory of the address in memory of the data to use
Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

• Effective Address (EA)

• The address, that can be directly used without modification to access an operand for a computation-type
instruction, or as the target address for a branch-type instruction
TYPES OF ADDRESSING MODES
• Direct Address Mode
Instruction specifies the memory address which can be used directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)
TYPES OF ADDRESSING MODES
• Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location that contains the address
of the operand
- When the abbreviated address is used large physical memory can be addressed with a relatively small
number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
TYPES OF ADDRESSING MODES

• Immediate Mode
Instead of specifying the address of the operand, operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
TYPES OF ADDRESSING MODES
• Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
TYPES OF ADDRESSING MODES
• Register Indirect Mode
Instruction specifies a register which contains the memory address of the operand
- Saving instruction bits since register address is shorter than the memory address
- Slower to acquire an operand than both the register addressing or memory addressing
- EA = [IR(R)]

[x]: Content of x)
TYPES OF ADDRESSING MODES
• Autoincrement or Autodecrement Mode
- When the address in the register is used to access memory, the value in the register is
incremented or decremented by 1 automatically

• Implied Mode (Stack Addressing Mode)

Address of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
- Examples from Basic Computer
CLA, CME, INP
TYPES OF ADDRESSING MODES
• Relative Addressing Modes
The Address fields of an instruction specifies the part of the address (abbreviated address) which can
be used along with a designated register to calculate the address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of address bits
- EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode (R = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode (R = IX, where IX: Index Register)
- EA = IX + IR(address)
* Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)
ADDRESSING MODES - Numerical Example
REGISTER STACK ORGANIZATION
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable

Push, Pop operations

/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP  SP + 1 DR  M[SP]
M[SP]  DR SP  SP  1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  0 FULL  0

Register Stack
MEMORY STACK ORGANIZATION
Memory with Program, Data, and Stack Segments

- A portion of memory is used as a stack with a

processor register as a stack pointer

PUSH: SP  SP - 1
M[SP]  DR

POP: DR  M[SP]
SP  SP + 1

- Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty
stack)  must be done in software
REGISTERS
• In Basic Computer, there is only one general purpose register, the
Accumulator (AC)
• In modern CPUs, there are many general purpose registers
• It is advantageous to have many registers
• Transfer between registers within the processor are relatively fast
• Going “off the processor” to access memory is much slower

• How many registers will be the best ?

PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses, data, etc.
• The processor has a register, the Program Counter (PC) that holds the memory
address of the next instruction to get
• Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits
• In a direct or indirect addressing, the processor needs to keep track of what
locations in memory it is addressing: The Address Register (AR) is used for this
• The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect addressing, it is
placed in the Data Register (DR). The processor then uses this value as data
for its operation
• The Basic Computer has a single general purpose register – the Accumulator
(AC)
PROCESSOR REGISTERS
• The significance of a general purpose register is that it can be referred to in
instructions
• e.g. load AC with the contents of a specific memory location; store the contents of AC into a specified
memory location
• Often a processor will need a scratch register to store intermediate results or
other temporary data; in the Basic Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O) operations
• Input devices are considered to send 8 bits of character data to the processor
• The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an input device
• The Output Register (OUTR) holds an 8 bit character to be send to an output
device
BASIC COMPUTER REGISTERS
BASIC COMPUTER REGISTERS
 GENERAL REGISTER ORGANIZATION
Input
Clock

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB

3x8
A bus B bus
decoder

SELD
OPR ALU

Output
 GENERAL REGISTER ORGANIZATION

Control Word
There are 14 binary selection inputs in the unit, and their combined
value specifies a control word.
The 14-bit control word is defined in figure below.
 GENERAL REGISTER ORGANIZATION

Table: Encoding of register selection fields

Table: Encoding of ALU operations
 GENERAL REGISTER ORGANIZATION

Examples of Microoperations

Table: Some of the examples of Microoperations for CPU

INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the following
cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the
next instruction

Note: Every different processor has its own (different) instruction cycle
Instruction Fetch and Decode Phase
• Sequence of steps required for fetching instruction from memory to CPU
internal register is known as fetch cycle.
• Program execution begins with: PC ← address of first instruction, SC ← 0
• After this, the SC is incremented at each clock cycle until an instruction is
completed, and then it is cleared to begin the next instruction.
• This process repeats until a HLT instruction is executed, or until the power
is shut off.

T0: AR PC
T1: IR  M [AR], PC  PC + 1
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
Determine Instruction Type and Execute Phase

D7 determines which type of instruction is to be decoded.

If D7 = 1, it will be either register-reference or input-output instruction.

 If I = 1, input-output instruction is executed during T3.
 If I = 0, register-reference instruction is executed during T3.

If D7 = 0, it will be memory-reference instruction.

 If I = 1, indirect addressing mode instruction during T3.
 If I = 0, direct addressing mode instruction during T3.

The SC is reset after executing each instruction.

INSTRUCTION CYCLE
 REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
MEMORY REFERENCE INSTRUCTIONS
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
INTERRUPT CYCLE
- The interrupt cycle is a HW implementation of a branch and save return address operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt
service routine
- The instruction that returns the control to the original program is "indirect BUN 0“
- Interrupts can be globally enabled or disabled via the IEN flag (flip-flop).
- If interrupts are enabled, then when either FGI or FGO gets set, the interrupt flip-flop (R) flag also gets set.
(R = FGI V FGO).
The interrupt enable flip-flop IEN can be set and cleared with two instructions (IOF, ION):
IOF: IEN ← 0 (the computer cannot be interrupted)
ION: IEN ← 1 (the computer can be interrupted)
Another flip-flop (called the interrupt flip-flop R) is used in the computer’s interrupt facility to decide when to
go through the interrupt cycle.
FGI and FGO are different here compared so that the computer is either in an Instruction Cycle or in an
Interrupt Cycle.
If R = 0, the CPU goes through a normal instruction cycle.
If R = 1, the CPU branches to the ISR to process an I/O transaction.
FLOWCHART FOR INTERRUPT CYCLE
 A
Case Study
on
Power PC Processor
and
Pentium Processor
Assignment For You!
•Assigned Date: 2074/04/15
•Submission Date: 2074/04/22
•Submission Criteria: Assignment would be
accepted only in loose sheets/papers. No
plagiarism, if otherwise found would
immediately be rejected (Both copier and
supplier).
•Note: Assignment submitted after the
deadline would not be entertained.
Book References:
• W. Stalling, “Computer Organization and Architecture”, 7th
edition, Prentice-Hall India Limited, New Delhi.
• A.J. Vande Goor, “Computer Architecture and Design”,
Addison Wesley, Wokingham, UK, 1989
• A.S. Tanenbaum, “Structured Computer Organization”,
Prentice Hall India Limited, new Delhi.
• M. Morris Mano, “Computer System Architecture”, Latest
Edition.
• John P. Hayes, “Computer Architecture and Organization”,
Latest Edition.