Ir itel. 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Miltary lm High-Performance Embedded 1 On-Chip Memory Management Unit Architecture —4 Gigabyte Virtual Address Space —25 MIPS Burst Execution at 25 MHz per Task 4 —3.4 MIPS! Sustained Execution at —4 Kbyte Pages with Supervisor/User 25 MHz Protection 1 On-Chip Floating-Point Unit @ Built-in Interrupt Controller — Supports IEEE 754 Floating-Point — 32 Priority Levels Standard —248 Vectors —Full Transcendental Support —Supports MB259A —Four 80-Bit Regi —3.4 us Latency —5.2 Million Whetstones/Second at Easy to Use, High Bandwidth 32-Bit Bus 25 MHz —66.7 Mbytes/s Burst m 512-Byte On-Chip Instruction Cache —Up to 16-Bytes Transferred per Burst —Direct Mapped king and Multi Parallel Load/Decode for Uncached ™_guinlasking and Multiprocessor Instructions —Automatic Task Dispatching m= Multiple Register Sets —Prioritized Task Queues —Sixteen Global 32-Bit Registers 1m Advanced Package Technology — Sixteen Local 32-Bit Registers — 132 Lead Ceramic Pin Grid Array —Four Local Register Sets Stored — 164 Lead Ceramic Quad Fiatpack ee on ae 1 Available in Two Temperature Ranges: —Register Scoreboarding —MIL-STD-883: —55°C to + 125°C (Tc) —Avionies: — 40°C to + 125°C (Tc) ‘The 80960MC is the enhanced military member of Intel's new 32-bit microprocessor family, the 960° proces- ‘sor series, which is designed especially for embedded applications. It is based on the family's high perform- ance, common core architecture, and includes a §12-byte instruction cache, a built-in interrupt controller, an integrated floating-point unit and a memory management unit. The 80960MC has a large register set, multiple parallel execution units, and a high-bandwidth, burst bus. Using advanced RISC technology, this high perform- ance processor can respond to interrupts in under 3.4 11s and is capable of execution rates in excess of 9.4 million instructions per sécond.! The 80960MC is well-suited for a wide range of military and other high reliability applications, including avionics, airbomne radar, navigation, and instrumentation. ‘Relative to Digital Equipment Corporation’s VAX-11/780° at 1 MIPS 271080-1 Figure 1. The 80960MC’s Highly Parallel Microarchitecture “Other brands and names are the property of their respective owners. November 1964 Onder Number:271000-000 MM 482b175 O1S1022 OTF Ml al‘80960MC THE 960 SERIES The 80960MC is the enhanced military member of a new family of 32-bit microprocessors from Intel known as the 960 Series, This series was especially designed to serve the needs of embedded applica- tions. The embedded market includes applications 18s diverse as industrial automation, avionics, image processing, graphics, robotics, telecommuni and automobiles. These types of applications re- ‘uire high integration, low power consumption, quick interrupt response times, and high performance. Since time to market is critical, embedded micro- processors need to be easy to use in both hardware and software designs. intgl. All members of the 80960 series share a common core architecture which utilizes RISC technology so that, except for special functions, the family mem- bers are object code compatible. Each new proces- ‘sor in the series will add its own special set of func- tions to the core to satisfy the needs of a specific application or range of applications in the embedded market. For example, future processors may include a DMA controller, a timer, or an A/D converter. ‘The 80960MC includes an integrated Floating Point Unit (FPU), a Memory Management Unit (MMU), multitasking support, and multiprocessor support. There are also two commercial members of the fam- ily: the 80960KB processor with integrated FPU and the 80960KA without floating-point. ° SIXTEEN | GLOBAL 32-BIT _ | REGISTERS() REGISTERS = FLOATING- FOUR 60-BIT REGISTERS — | POINT {p3 REGISTERS 0 SIXTEEN | LOCAL ADDRESS 3281T | REGISTERS@ SPACE REGISTERS 15 ITS__} ARITHMETIC CONTROLS 32-BITS_ | INSTRUCTION POINTER 292-4 32-8ITS _] PROCESS CONTROLS 32-8ITS _] TRACE CONTROLS NOTES: 4. Register 915 is reserved for stack management functions. 2. Registers r0, 1, and r2 are reserved for stack management functions. Figure 2. Register Set MH 4826175 0151023 135 = 2-62intel. oooeonc KEY PERFORMANCE FEATURES 0 that execution speed can be greatly improved by ‘ensuring that these core instructions execute in as ‘The 80960MC's architecture is based on the most ‘short a time as possible. The most-frequently exe- Tecent advances in RISC technology and is ground- cuted instructions such as register-register moves, ed in Intel's long experience in designing embedded add/subtract, logical operations, and shifts execute controllers. Many features contribute to the in one to two cycles (Table 1 contains a list of in- 80960MC's exceptional performance: structions.) 1, Large Register Set. Having a large number of 3. Load/Store Architecture. Like other processors registers reduces the number of times that a proces- based on RISC technology, the 80960MC has a sor needs to access memory. Modern compilers can _Load/Store architecture, only the LOAD and STORE take advantage of this feature to optimize execution _ instructions reference memory; all other instructions speed. For maximum flexibility, the 80960MC pro- operate on registers. This type of architecture simpli- vides thirty-two 32-bit registers (sixteen local and fies instruction decoding and is used in combination sixteen global) and four 80-bit floating-point global _with other techniques to increase parallelism, registers. (See Figure 2.) 2. Fast Instruction Execution. Simple functions make up the bulk of instructions in most programs, Control ‘Opoode Displacement scamome Osseo [a [pinecone] feos, ao | fear] notte, (sete [Reg [te [wT [om] Memory Ao _ Opcode | Reg Base Mode Scale | xx | Index Displacement Figure 3. Instruction Formats (| Mi 4826175 0151024 97, 2-63 flr: -:-:-=sCd=d =?”sossowe intgl. Table 1, 80960MC Instruction Set = Data Movement Arithmetic eating Logleat ti ia a ee a mae = se Pd nae tee I or ae ae e : Load Physical Remainder Remainder Exclusive Or Address Modulo ‘Scale Not Or ‘Shift Round Or Not ‘Square Root Nor = a =. re Tangent Nand Log Log Binary pod Exponent Classify ‘Copy Real =o Compare Bitand ‘Comparison Branch Bit Fiekd String ‘Compare ‘Unconditional ‘Set Bit Move String Conditional Branch Clear Bit Move Quick String Compare Conditional Branch Not Bit Fill String Compare and: Compare and Check Bit Compare String Increment Branch Alter Bit ‘Scan Byte for eeeatta i = Decrement ‘Scan over Bit Extract Modify — — — — ac Convert Real to. Move Call ‘Schedule Process integer ‘Add with Carry. Call Extended ‘Saves Process Convert Integer to. ‘Subtract with Carry Call System Resume Process Real Retum Load Process Time Branch and Link Modify Process: = Wait Saati Signal Receive — Receive = — Atomic Add ‘Atomic Modify Fault Debug Miscellaneous oaieasa | rae ae ae | eo oe Mark Inspect Access Force Mark Modify Arithmetic — Test Condition Code. MB 4826175 0151025 808 a 2-64intel. 4. Simple Instruction Formats. All instructi the 80960MC are 32-bits long and must be aligned ‘on word boundaries. This alignment makes it possi- ble to eliminate the instruction-alignment stage in the pipeline. To simplify the instruction decoder fur- ther, there are only five instruction formats and each instruction uses only one format. (See Figure 3.) 5. Overlapped Instruction Execution. A load oper- ation allows execution of subsequent instructions to continue before the data has been retumed from memory, 0 that these instructions can overlap the load. The 80960MC manages this process transpar- ently to software through the use of a register score- board. Conditional instructions also make use of a scoreboard so that subsequent unrelated instruc- tions can be executed while the conditional instruc- tion is pending. 6. Integer Execution Optimization. When the re- sult of an operation is used as an operand in a sub- sequent calculation, the value is sent immediately to its destination register. Yet at the same time, the value is put back on a bypass path to the ALU, thereby saving the time that otherwise would be re- Quired to retrieve the value for the next operation. 7, Bandwidth Optimizations. The 80960MC gots ‘optimal use of its memory bus bandwidth because the bus is tuned for use with the cache: the line size of the instruction cache matches the maximum burst size for instruction fetches. The 80960MC automati- cally fetches four words in a burst and stores them directly in the cache. Due to the size of the cache and the fact that itis continually filed in anticipation of needed instructions in the program flow, the 80960MC is exceptionally insensitive to memory wait states. In fact, each wait state causes only a 7% degradation in system perfomance. The benefit is that the 80960MC will deliver outstanding per- formance even with a low cost memory system, 8, Cache Bypass. If there is a cache miss, the proo- essor fetches the needed instruction, then sends it ‘on to the instruction decoder at the same time it updates the cache. Thus, no extra time is taken to load and read the cache. Memory Space and Addressing Modes ‘The 80960MC allows each task (process) to ad- dress a logical memory space of up to 4 Gbytes. In tum, each task's address space is divided into four 1-Gbyte regions and each region can be mapped to physical addresses by zero, one, or two levels of age tables. The region with the highest addresses (Region 3) is common to all tasks. MH 4826175 0151026 744 me 80960MC {in keeping with RISC design principles, the number of addressing modes has been kept to a minimum. but includes all those necessary to ensure efficient ‘execution of high-level languages such as Ada, C, and Fortran. Table 2 lists the memory addressing modes. Data Types The 80960MC recognizes the following data types: Numeric: © 8, 16-, 32- and 64-bit ordinals * B., 16, 32- and 64-bit integers * 32., 64- and 80-bit real numbers Non-Numeric: © Bit * Bit Field © Triple-Word (96 bits) © Quad-Word (128 bits) Large Register Set The programming environment of the 80960MC in- cludes a large number of registers. In fact, 36 regis- ters are available at any time, The availabilty of this many registers greatly reduces the number of mem- ory accesses required to execute most programs, which leads to greater instruction processing speed. There are two types of general-purpose registers: local and global. The 20 global registers consist of sixteen 32-bit registers (GO through G15) and four 80-bit registers (FPO through FP3). Those registers perform the same function as the general-purpose registers provided in other popular microprocessors. The term global refers to the fact that these regis- ters retain their contents across procedure calls. The local registers, on the other hand, are proce- dure specific. For each procedure call, the 80960MC allocates 16 local registers (RO through R15). Each local register is 32 bits wide. Any register can also be used for floating-point operations; the 80-bit float- ing-point registers are provided for extended preci- sion. Multiple Register Sets To further increase the efficiency of the register set, multiple sets of local registers are stored on-chip. This cache holds up to four local register frames, which means that up to three procedure calls can be made without having to access the procedure stack resident in memory. 265‘Table 2, Memory Addressing Modes * 12-Bit Offset * 32-Bit Offest # Register-Indirect, * Register + 12-Bit Offset # Register + 32-Bit Offset # Register + (Index-Register x Scale-Factor) © Register x Scale Factor + 32-Bit Displacement Scale-Factor is 1, 2, 4, 8 or 16 * Register + (Index-Register x Scale-Factor) + 32-Bit Displacement Although programs may have procedure calls nest- ed many calls deep, a program typically oscillates back and forth between only two or three levels. AS a result, with four stack frames in the cache, the probability of there being a free frame on the cache when a call is made is very high. In fact, runs of representative C-language programs show that 80% of the calls are handled without needing to access memory. If there are four or more active procedures and a new procedure is called, the processor moves the oldest set of local registers in the register cache to a procedure stack in memory to make room for a new set of registers. Global register G15 is used by the processor as the frame pointer (FP) for the proce- dure stack, Note that the global and floating-point registers are ‘not exchanged on a procedure call, but retain their contents, making them available to all procedures for fast parameter passing. An illustration of the reg- ister cache is shown in Figure 4, REGISTER CACHE ONE OF FOUR LOCAL REGISTER SETS LOCAL REGISTER SET Ris a ° 271080-2 Figure 4. Multiple Register Sets Are Stored On-Chip M™ 4826175 0151027 b80 ~ | 2.66 |intel. Instruction Cache To further reduce memory accesses, the 80960MC includes @ 512-byte on-chip instruction cache. The instruction cache is based on the concept of locality of reference; that is, most programs are not usually executed in’a steady stream but consist of many branches and loops that lead to jumping back and forth within the same small section of code. Thus, by maintaining a block of instructions in a cache, the number of memory references required to read in- structions into the processor can be greatly reduced. To load the instruction cache, instructions are fetched in 16-byte blocks, so that up to four instruc- tions can be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction will already be in the cache when it is needed. Code for small loops will often fit entirely within the cache, leading to @ great increase in processing ‘speed since further memory references might not be necessary until the program exits the loop. Similarly, when calling short procedures, the code for the call- ing procedure is likely to remain in the cache, so it will be there on the procedure’s return. Register Scoreboarding The instruction decoder has been optimized in sev- eral ways. One of these optimizations is the ability to do instruction overlapping by means of register scoreboarding. Register scoreboarding occurs when a LOAD in- struction is executed to move a variable from memo- ty into a register. When the instruction is initiated, a ‘scoreboard bit on the target register is set. When the register is actually loaded, the bit is reset. In be- ‘tween, any reference to the register contents is ac- ‘companied by a test of the scoreboard bit to insure that the load has completed before processing con- tinues, Sinos the processor does not have to wait for the LOAD to be completed, it can go on to execute additional instructions placed in between the LOAD instruction and the instruction that uses the register contents, as shown in the following example: LOAD R4, address 1 LOAD RS, address 2 Unrelated instruction Unrelated instruction ADD Ra, R5, RE In essence, the two unrelated instructions between the LOAD and ADD instructions are executed for MMH 4826175 0152028 517 a SS EE CC _—_—_—_—___— CEC ——E———_——_——-_|_<——_=—_—--E-EE|EE|E|E||__ |={|x[xTx__ free (1.0. take no apy they are executed while the register is being loaded. Up to three LOAD instructions can be per ne time with three corresponding scoreboard bits set. By exploiting this feature, system programmers and compilers have a useful tool for optimizing exe- cution speed. Memory Management and Protection ‘The 80960MC will be especially useful for multitask. ing applications that require software protection and a very large address space. To ensure the highest level of performance possible, the memory manage- ‘ment unit and translation look-aside buffer (TLB) are contained on-chip. The 80960MC supports a conventional form of de- mand-paged virtual memory in which the address space is divided into 4 Kbyte pages. Studies have shown that a 4 Kbyte page is the optimum size for a broad range of applications. Each page table entry includes a 2-bit page rights field that specifies whether the page is a no-access, toac-ony, of read-write page, This fold i interpret. ‘ed differently depending on whether the current t (process) is executing in user or supervisor mode, shown below: Rights User ‘Supervisor 00 No Access Read-Only a1 No Access Read-Write 10 Read-Only Read-Write "1 Read-Write Read-Write Floating-Point Arithmetic In the 80960MC, floating-point arithmetic has been made an integral part of the architecture. Having the floating-point unit integrated on-chip provides two advantages. First, it improves the performance of the chip for floating-point applications, since no additional bus overhead is associated with floating- point calculations, thereby leaving more time for oth- er bus operations such as 1/0. Second, the cost of using floating-point operations is reduced because a separate coprocessor chip is not required. The 80860MC floating-point (real number) data types include single-precision (82-bit), double-preci- sion (64-bit), and extended precision (80-bit) float ing-point numbers. Any register may be used to exe- cute floating-point operations. 2.6780960MC ‘The processor provides hardware support for both mandatory and recommended portions of IEEE Standard 764 for floating-point arithmetic, including all arithmetic, exponential, logarithmic, and other transcendental functions. Table 3 shows execution times for some representative instructions. Table 3. Sample Floating-Point Execution Times (us) at 25 MHz 32-Bit 64-Bit Add 04 05 ‘Subtract 04 05 Multiply 07 13 Divide 13 29 ‘Square Root 37 39 Arctangent 10.1 13.1 Exponent 11.3 12.5 Sine 18.2 16.6 Cosine 15.2 16.6 Multitasking Support Multitasking programs commonly involve the moni toring and control of an external operation, such as the activities of a process controller or the move- ments of a machine tool. These programs generally consist of a number of processes that run indepen- dently of one another, but share a common data- base or pass data among themselves. ‘The 80960MC offers several hardware functions de- signed to support multitasking systems. One unique feature, called selt-dispatching, allows a processor to switch itself automatically among scheduled tasks. When self-dispatching is used, all the operat- ing system is required to do is place the task in the scheduling queue. When the processor becomes available, it dis- Patches the task from the beginning of the queue and then executes it until it becomes blocked, inter- rupted, or unti its time-slice expires. It then returns the task to the end of the queue (.¢., automatically reschedules it) and dispatches the next ready task. mm 4826175 0151029 4s3 2-68 intel. During these operations, no communication be- tween the processor and the operating system is necessary until the running task is complete or an interrupt is issued. Synchronization and Communication The 80960MC also offers instructions to set up and test semaphores to ensure that concurrent tasks remain synchronized and no data inconsistency results. Special data structures, known as communi- cation ports, provide the means for exchanging parameters and data structures. Transmission of in- formation by means of communication ports is asyn- chronous and automatically buffered by the proces sor. ‘Communication between tasks by means of ports ‘can be carried out independently of the operating system. Once the ports have been set up by the Brogrammer, the processor handles the message Passing automatically. High Bandwidth Local Bus ‘An 80960MC CPU resides on a high-bandwidth ad- dross/data bus known as the local bus (L-Bus). The L-Bus provides a direct communication path be- tween the processor and the memory and I/O sub- system interfaces. The processor uses the local bus to fetch instructions, manipulate memory, and re- spond to interrupts. Its features include: ‘* 32-bit multiplexed address/data path * Four-word burst capability, which allows transfers from 1 to 16 bytes at a time ‘* High bandwidth reads and writes at 66.7 MBytes er second * Special signal to indicate whether a memory transaction can be cached Figure 5 identifies the groups of signals which con- stitute the L-Bus. Table 4 lists the function of the L- Bus and other processor-support signals, such as, the interrupt lines.‘80960MC LOCAL BUS SIGNAL GROUPS \ ADDRESS/OATA (32 LINES) ‘CONTROL (ADDRESS,DATA, ond OPERATION SIGNALS~= 15 LINES) ARBITRATION (2 LINES) 271080-3 Figure 5. Local Bus Signal Groups Multiple Processor Support (One means of increasing the processing power of a system is to run two or more processors in parallel. Since microprocessors are not generally designed to run in tandem with other processors, designing such a system is usually dificult and costly. The 80960MC solves this problem by offering a number of functions to coordinate the actions of multiple processors. First, messages can be passed between processors to initiate actions such as flush- ing a cache, stopping or starting another processor, oF preempting a task. The messages are passed on the bus and allow multiple processors to run togeth- er smoothly, with rare need to lock the bus or memo- ny. Second, a set of synchronization instructions help maintain the coherency of memory. These instruc- tions permit several processors to modify memory at the same time without inserting inaccuracies or am- biguities into shared data structures. ‘The seif-dispatching mechanism, in addition to being used in single-processor systems, provides the means to increase the performance of a system merely by adding processors. Each processor can either work on the same pool of tasks (sharing the same queue with other processors) or can be re- stricted to its ewn queue. When processors perform system operations, they synchronize themselves by using atomic operations and sending special messages between each other. ‘And changing the number of processors in a system M@™ 4826175 0151030 175 a i ever requires a software change. Software will exe- cute correctly regardless of the number of proces- sors in the system; systems with more processors. simply execute faster. Interrupt Handling ‘The 80960MC can be interrupted in one of two ways: by the activation of one of four interrupt pins ‘or by sending a message on the processor's data bus. ‘The 80960MC is unusual in that it automatically han- dies interrupts on a priority basis and tracks pending interrupts through its on-chip interrupt controller. Two of the interrupt pins can be configured to pro- vide M8259A handshaking for expansion beyond four interrupt lines. ‘An interrupt message is made up of a vector number and an interrupt priority. If the interrupt priority is greater than that of the currently running task, the processor accepts the interrupt and uses the vector as an index into the interrupt table. If the priority of the interrupt message is below that of the current task, the processor saves the information in a sec- tion of the interrupt table reserved for pending inter- rupts. Debug Features ‘The 80960MC has built-in debug capabilities. There are two types of breakpoints and six different trace modes. The debug features are controlled by two 26980960MC internal 32-bit registers, the Process-Controls Word and the Trace-Controls Word. By setting bits in these control words, a software debug monitor can closely control how the processor responds during program execution. ‘The 80960MC hes both hardware and software breakpoints, It provides two hardware breakpoint registers on-chip which can be set by a special com- mand to any value. When the instruction pointer ‘matches the value in one of the breakpoint registers, ‘the breakpoint will fire, and a breakpoint handling routine is called automaticaly, The 80960MC also provides software breakpoints through the use of two instructions, MARK and FMARK. These instructions can be placed at any Point in @ program and will cause the processor to halt execution at that point and call the breakpoint handling routine. The breakpoint mechanism is easy to use and provides a powerful debugging tool. Tracing is available for instructions (single-step exe- cution), calls and retums, and branching. Each dif- ferent type of trace may be enabled separately by a special debug instruction. In each case, the '80960MC executes the instruction first and then calls a trace handling routine (usually part of a soft- ware debug monitor). Further program execution is halted until the trace routine is completed. When the trace event handling routine is completed, instruc- tion execution resumes at the next instruction. The ‘80960MC's tracing mechanisms, which are imple- mented completely in hardware, greatly simplify the task of testing and debugging software. FAULT DETECTION The 80960MC has an automatic mechanism to handle faults. There are ten fault types including trace, arithmetic, and floating-point faults. When the processor detects a fault, it automatically calls the ‘appropriate fault handling routine and saves the cur- rent instruction pointer and necessary state informa- tion to make efficient recovery possible. The proces- sor posts diagnostic information on the type of fault to a Fault Record. Like interrupt handling routines, fault handling routines are usually written to meet the needs of a specific application and are often in- cluded as part of the operating system or kernel. For each of the ten fault types, there are numerous ‘subtypes that provide specific information about a fault. For example, a floating-point fault may have its ‘subtype sat to an Overflow or Zero-Divide fault. The fault handler can use this specitic information to re- spond correctly to the fault M™ 4426175 015103) O01 2:70 intel. Interagent Communications (IAC) In order to coordinate their actions, processors in a multiple processor system need a means for com- municating with each other. The 80960MC does through a mechanism known as Interagent Commu: nication messages or IACS. TAC messages cause a variety of actions including starting and stopping processors, flushing instruc tion caches and TLBs, and sending interrupts to oth- er processors in the system. The upper 16 Mbytes of the processor's physical memory space is reserved for sending and receiving IAC messages. BUILT-IN TESTABILITY Upon reset, the 80960MC automatically conducts an ‘exhaustive internal test of its major blocks of logic. Then, befors executing its first instruction, it does a zero check sum on the first eight words in memory to ensure that the system has been loaded correctly. If @ problem is discovered at any point during the self-test, the 80960MC will assert its FAILURE pin and will not begin program execution. The self-test takes approximately 47,000 cycles to complete. ‘System manufacturers can use the 80960MC's self- test feature during incoming parts inspection. No special diagnostic programs need to be written, and the test is both thorough and fast. The self-test ca- pability helps ensure that defective parts will be dis- covered before systems are shipped, and once in the field, the self-test makes it easier to distinguish between problems caused by processor failure and problems resulting from other causes. COMPATIBILITY WITH 80960K-SERIES Application programs written for the 80960K-Series microprocessors can be run on the 80960MC with- ‘out modification. The 80960K-Series instruction set forms the core of the 80960MC's instructions, so bi- nary compatibility is assured.intel. CHMOS ‘The 80960MC is fabricated using Intel's CHMOS IV (Complementary High Speed Metal Oxide Semicon- ductor) process. This advanced technology elimi- nates the frequency and reliabitity limitations of older 80960MC CMOS processes and opens a new era in micro- processor performance. It combines the high per- formance capabilities of Intel's industry-leading HMOS technology with the high density and low power characteristics of CMOS. The 80960MC is available at 16, 20 and 25 MHz. Table 4a. 80960MC Pin Description: L-Bus Signals Symbol | Type Name and Function cLK2 1 | SYSTEM CLOCK provides the fundamental timing for 80960MC systems. Itis divided by two inside the 80960MC to generate the internal processor clock. CLK2 is shown in Figure 9. LADa1 VO] LOCAL ADDRESS/DATA BUS carries 32-bit physical addresses and data to and LAD) | 1.8. | frommemory. During an address (T,) cycle, bits 2-1 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Tq) cycle, bits 0-31 contain read or write data. The LAD lines are active HIGH and float to a high ipedance state when not active. SIZE, which is comprised of bits 0-1 of the LAD lines during a Ta cycle, specifies the size of a transfer in words for a burst transaction. LAD, =— LAD ° ° 1. Word ° 1 2 Words 1 0 3 Words 1 1 4Words ALE © | ADDRESS-LATCH ENABLE indicates the transfer of a physical address. ALE is T.S. | asserted during a Ta cycle and deasserted before the beginning of the Ty state. It ‘active LOW and floats to a high impedance state when the processor is idle or is at the end of any bus access. ADS } ADDRESS STATUS indicates an address state. ADS is asserted every Ta state ©.D. | anddeasserted during the the following Ty state. For a burst transaction, ADS is asserted again every Ty state where READY was asserted in the previous cycle. : wh ° WRITE/READ specifies, during a T, cycle, whether the operation is a write or ©.D._| read. Itis latched on-chip and remains valid during Tg and Ty, states. DT/R © | DATA TRANSMIT/RECEIVE indicates the direction of data transfer to and from ©.D. | the L-Bus. itis low during Ta, Ty and Tq cycles for a read or interrupt ‘acknowledgement; itis high during Ts, Tw and Ty cycles for a write. DT/F never : changes state when DEN is asserted (see Timing Diagrams). DEN © | DATA ENABLE is asserted during Ty and Tw cycles and indicates transfer of data ©.0._| onthe LAD bus lines. READY 1 READY indicates that data on LAD lines can be sampled or removed. If READY is not asserted during a Tq cycle, the Ty cycle is extended to the next cycle by erting wait states (Ty), and ADS is not asserted in the next cycle. TOCK 0 | BUS LOCK prevents other bus masters from gaining control of the L-Bus : ©.D. | following the current oycie (if they would assert LOCK to do so). LOCK is used by the processor or any bus agent when it performs indivisible Read/Modity/Write (RMW) operations, For a read that is designated as a RMW-read, LOCK is examined. if asserted, the rocessor waits until itis not asserted: if not asserted, the processor asserts - FScK during tho Ta cycle and leaves it asserted Awrite that is designated as an RMW-write deasserts LOCK in the Ta cycle, VO = Input/Output, O = Output, | = Input, 0.0. = Open-Drain, TS. = three state Ta = Taddress: Td = Tatas Tw — Twait: Tr — TRecovery 4826175 0151032 T48 Tue: Th80960MC- intel ° ‘Table 4a. 80960MC Pin Description: L-Bus Signals (Continued) Symbol | Type Name and Function BE3-BEp | O | BYTE ENABLE LINES specify which data bytes (up to four) on the bus take part ©.D. | inthe current bus cycle. BE3 corresponds to LADg,-LADa4 and BE corresponds 10 LAD —LADo. ‘The byte enables are provided in advance of data. The byte enables asserted during Ta specify the bytes of the first data word. The byte enables asserted during Ty specify the bytes of the next data word (if any), thatis, the word to be transmitted following the next assertion of READY. The byte enables during the ‘Ty cycles preceding the last assertion of READY are undefined. The byte enables are latched on-chip and remain constant from one Tg cycle to the next when READY is not asserted. For reads, the byte enables specify the byte(s) that the processor will actually use. 80960MC's will assert only adjacent byte enables (e.g., asserting just BEg and BE; is not permitted), and are required to assert at least one byte enable. Accesses must also be naturally aligned (e.g., asserting BE, and BE? is not allowed even though they are adjacent). To produce address bits Ag and Ay externally, they can be decoded from the byte enables. HOLD 1 | HOLD indicates a request from a secondary bus master to acquire the bus. If the (HLDAR) processor is initialized as the primary bus master this input will be interpreted as HOLD. When the processor receives HOLD and grants another master control of the bus, it floats its three-state bus lines, asserts HOLD ACKNOWLEDGE, and enters the Th state. When HOLD is deasserted, the processor will deassert HOLD ACKNOWLEDGE and go to either the Tj or Ta state, HOLD ACKNOWLEDGE RECEIVED indicates that the processor has acquired the bus. If the processor is initialized as the secondary bus master this input is interpreted as HLDAR. HOLD timing is shown in Figure 11. HLDA 0 | HOLD ACKNOWLEDGE relinquishes control of the bus to another bus master. If (HOLDR) | T.s. | the processor is initialized as the primary bus master this output will be interpreted ‘as HLDA. When HOLD is deasserted, the processor will deassert HLDA and go to. either the T| or Ta state. HOLD REQUEST indicates a request to acquire the bus. If the processor is initialized as the secondary bus master this output will be interpreted as HOLDR. HOLD timing is shown in Figure 11. CACHE ‘© | CACHE indicates if an access is cacheable during a Ta cycle. The CACHE signal T.8,__| floats to a high impedance state when the processor is idle. input/Ouiput, © = Oulput, 1 = Input, 0.0. = Open-Drain, T'S. = three state Detar Tw = TWait. Tr = TRecovery: Ti ~ Tidle: Th = THold MB 4826175 0151033 984 we 272 Iintel ® 80960MC Table 4b. 80960MC Pin Description: Module Support Signals Symbol _| Type Name and Function BADAC. ' BAD ACCESS, if asserted in the cycle following the one in which the last READY of a transaction is asserted, indicates that an unrecoverable error has occurred on the current bus transaction, or that a synchronous load/store instruction has not been acknowledged. STARTUP: During system reset, the BADAC signal is interpreted differently. If the signal is high, it indicates that this processor will perform system initialization. Ifit is low, another processor in the system will perform system initialization instead. RESET 1 RESET clears the internal logic of the processor and causes it to re-initialize. uring RESET assertion, the input pins are ignored (except for BADAC and TAC/INTo), the tri-state output pins are placed in a high impedance state, and other output pins are placed in their non-asserted state. RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. ‘The HIGH to LOW transition of RESET should occur after the rising edge of both CLK2 and the external bus CLK, and before the next rising edge of CLK2. RESET timing is shown in Figure 10. FAILURE | © | INITIALIZATION FAILURE indicates that the processor has failed to initialize OD. | correctly. After RESET is deasserted and before the first bus transaction begins, LURE is asserted while the processor performs a self-test. If the self-test ‘completes successfully, then FAILURE is deasserted, Next, the processor performs a Zero checksum on the first eight words of memory. If it fails, FAURE. is asserted for a second time and remains asserted; if it passes, system initialization continues and FAILURE remains deasserted, NC. N/A | NOT CONNECTED indicates pins should not be connected. Never connect any pin marked N.C. TAC. ' INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates either (INTs) that there is a pending IAC message for the processor or an interrupt. The bus interrupt control register determines in which way the signal should be interpreted. To signal an interrupt or IAC request in a synchronous system, this pin (as well as the other interrupt pins) must be enabled by being deasserted for at least one bus cycle and then asserted for at least one additional bus cycle; in an asynchronous system, the pin must remain deasserted for at least two bus cycles and then be asserted for at least two more bus cycles. LOCAL PROCESSOR NUMBER: This signal is interpreted differently during system reset. If the signal is at a high voltage level, it indicates that this processor isa primary bus master (Local Processor Number = 0); ifitis at a low voltage. level, it indicates that this processor is a secondary bus master (Local Processor Number = 1). INT; : INTERRUPT 1, like INTo, provides direct interrupt signaling. INT I INTERRUPT 2/INTERRUPT REQUEST: The bus control registers determines (INTR) how this pin is interpreted. If INT, it has the same interpretation as the INT and INT1 pins. If INTR, it is used to receive an interrupt request from an external interrupt controller. INTs VO | INTERRUPT 3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register (INTA) ©.D. | determines how this pin is interpreted. If INTs, it has the same interpretation as the INTo, INT}, and INT? pins. If INTA, it is used as an output to control interrupt- acknowledge bus transactions, The INTA output is latched on-chip and remaing valid during Ty cycles; as an output, itis open-drain, W/O = Input/Output, © = Output, |= Input, 0.0. = OpenDrain, T.S. = three state Ta = Taadass: Td = Toatar TW = Twait Tr = TRecovery: Ti = Tiale: Tr. = THola M™@ 4826175 0151034 81080960MC ELECTRICAL SPECIFICATIONS Power and Grounding The 80960MC is implemented in CHMOS IV tech- nology and has modest power requirements, Its high clock frequency and numerous output buffers (ad- dress/data, control, error and arbitration signais) can cause power surges as multiple output buffers. drive new signal levels simultaneously. For clean on- chip power distribution at high frequency, 12 Voc ‘and 18 Veg pins separately feed functional units of ‘the 80960MC. Power and ground connections must be made to all power and ground pins of the 80960MC. On the cir- ‘cuit board, all Voc pins must be strapped closely together, preferably on a power plane. Likewise, all Vgg pins should be strapped together, preferably on a ground plane. Power Decoupling Recommendations Liberal decoupling capacitance should be placed near the 80960MC. The processor can cause tran- sient power surges when driving the L-Bus, particu- larly when it is connected to a large capacitive load. Low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. Inductance can be reduced by shortening the board traces between the processor and decou- pling capacitors as much as possible. Connection Recommendations For reliable operation, always connect unused in- puts to an appropriate signal level. In particular, if intel. ‘one or more interrupt lines are not used, they should bbe pulled up or down to their respective deasserted states. No inputs should ever be left floating. Al open-drain outputs require a pullup device. While in some cases a simple pullup resistor will be ade- quate, we recommend a network of pullup and pull- down resistors biased to a valid Viy (2 3.4V) and terminated in the characteristic impedances of the cir- cuit board, Figure 6 shows our recommendations for the resistor values for both a low and high current drive network, which assumes that the circuit board has a characteristic impedance of 100, The advan- tage of terminating the output signals in this fashion is that it limits signal swing and reduces AC power ‘consumption. Characteristic Curves Figure 7 shows the typical supply current require- ments over the operating temperature range of the processor at supply voltage (Vcc) of 5V. Figure 8 ‘shows the typical power supply current (Ioc) re- quired by the 80960MC at various operating fre- quencies when measured at three input voltage (Vcc) levels. Figure 9 shows the typical capacitive derating curve for the 80960MC measured from 1.5V on the system clock (CLK) to 0.8V on the falling edge and 2.0V on the rising edge of the L-Bus address/data (LAD) sig- nals. Yee 1800 ‘80960MC ‘OPEN=DRAIN ourPuT 3900, 271080-27 Low Drive Network: Von = 3.42V log = 253 mA Voc: 1300 B0960MC (OPEN-RAIN ouruT 2800, 271080-28, High Drive Network fon = 91 lot © 33.8 mA Figure 6. Connection Recommendations for Low and High Current Drive Networks MM 4826175 0151035 757 a 27480960MC sao +0 Gm 0 a Wo 1m As rarearuee (Oxoaronts axtN © 0, =5, 25,85, 120%) 271080-29, TPA SUPPLY CURRENT Gra) 4s0| 109 380 200 150 100 50 — ° 5 10 1s 20 3 ‘OPERATING FREQUENCY (i) 271060-90 Figure 7. Typical Supply Current (I¢c) Test Load Circuit Figure 10 illustrates the load circuit used to test the 80960MC's tristate pins, and Figure 11 shows the load circuit used to test the open drain outputs. The ‘open drain test uses an active load circuit in the form of a matched diode bridge. Since the open-drain out- Puts sink current, only the Io. legs of the bridge are Necessary and the lox legs are not used. When the ‘80960MC driver under test is turned off, the output pin is pulled up to VreF (18, Von). Diode Dy is tured off and the Io, current source flows through diode Dp. When the 80960MC open-drain driver under test is ‘on, diode D; is also on, and the voltage on the pin being tested drops to Vo. Diode Dz turns off and lox flows through diode Dy. z é § 'ypical Current ve Frequency s | rape 8 Tristate Output Valid Delay (ns) | 240 6080 100 Copocitive Load (pF) 271080-31 Figure 9. Capacitive Derating Curve s0s6omc TRISTATE OUTPUT. “t an Figure 10. Test Load Circult for ‘80960MC . ‘OPEN=DRAIN ourPuT 4 271080-33, ‘Tri-State Output Pins Figure 11. Test Load Circult for Open-Drain Output Pins WE 4826375 0151036 693‘80960MC ABSOLUTE MAXIMUM RATINGS* intel. NOTICE: This is @ production data sheet. The specifi- cations are subject to change without notice. sinder Best) —ssicte +128 WARNING, Stessng he denice boyond he Abokte oa 65°C to + 160°C Ines are arose ratings ony “cperaton beyond the in. =0.5V to Veg + 0.5V eee peas — “26 (5 Mi). my ano nn “Operating Conditions” OPERATING CONDITIONS MIL-STD-883 symbol Description in Max Units To Case Temperature (Instant On) —55 +125 *c Voo Digital Supply Voltage 475 6.25 Vv Avionics Grade Symbol Description Min Max Units To Case Temperature (Instant On) 55 +125 °c Voc Digital Supply Voltage 4.75 5.25 a. DC CHARACTERISTICS (Over Specified Operating Conditions) symbol Parameter Min Max | Unite | Test Conditions Vie input Low Voltage =03 +08 v Vi Input High Voltage 20 Voc + 0.3. Vv Vou CLK2 Input Low Voltage =03 +08 v Vou CLKZ Input High Voltage | 0.55Voc | Voo+o3 | V Vou Output Low Voltage 0.45 v (1,5) Vou Output High Vottage 24 v_ | @4 toc. Power Supply Current: 16 MHz 375 mA 20 MHz 420 mA 25 Miz 480 mA tu Input Leakage Current +15 HA | 05 VoS Veo ho. ‘Output Leakage Current +15 yA | 045 < Vo < Voc Cin Input Capacitance 10 pF fo = 1 MHz) Co. 1/0 or Output Capacitance 12 pF fo = 1 MHz) Coux | Glock Capacitance 10 pF | fo= 1 MHZ) M™ 4826175 0151037 S27 Ml 2-76intel ° 80960MC DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) ‘Symbol Parameter Min Max Units Test Conditions On Thermal Resistance (Junction-to-Ambient) Pin Grid Array 21 “cw Ceramic Quad Flatpack 29 “c/w 8c Thermal Resistance (Wunction-to-Case) Pin Grid Array 4 “cw Coramic Quad Flatpack 8 “cw NOTES: 1. For throw state ouput, tis parameter fs measured at Address/Data . Controls... 2. This parameter is measured at Address/Data........ Controls . AEE 3. Input, output, and clock capacitance are not tested Not messed on open-n oxi 5. For open-drain outputs MH 4826175 0151038 4bb I 27780960MC AC SPECIFICATIONS This section describes the AC specifications for the 80960MC pins. All input and output timings are specified relative to the 1.5V level of the rising edge of CLK2, and refer to the time at which the signal intel. reaches (for output delay and input setup) or leaves: (for hold time) the TTL levels of LOW (0.8V) or HIGH (2.0V). All AC testing should be done with input volt- ages of 0.4V and 2.4V, except for the clock (CLK2), ‘which should be tested with input voltages of 0.45V and 0.55 Voc. coer a 8 c une 1v outputs: ds, “LaDy, % Whe, cae oa of Iweurs: LAs LA, ‘aoac, Int, NTR, HOLD,WLDAR, ack, NOTE 1: For Tri-State pins, Te and To are measured at 1 5V. For Open-Drain ping, Tg is measured at 1.5V, Tp at 0.BV. me, YW Wik eer BD BE. WWYé~U“iWC CEG VALID OUTPUT. ne IW VALID INPUT 271080-4 Figure 12. Drive Levels and Timing Relationships for 80960MC Signals ME 4826175 0151039 372 a 27880960MC oe on coo ee | SE SSX N KS Sl 0 6 b ml ats WY le WO 271000-6 MM 4426175 0151040 O14 mm ' Figure 13. Timing Relationship of L-Bus Signals 27980960MC. AC Specification Tables 80960MC AC Characteristics (16 MHz) Symbol Parameter Min | Max | Units Test Conditions Tt Processor Clock 31.25 | 125 ns Vin = 1.5V Period (CLK2) Te Processor Clock 8 ns Vi_ = 10% Point Low Time (CLK2) =12v Ta Processor Clock 8 ns Vin = 90% Point High Time (CLK2) = 0.1V + 0.5 Voc Ts Processor Clock 10 ns Vin = 80% Point to 10% Fall Time (CLK2) Point Ts Processor Clock 10 ns | Vin = 10% Point to 90% Rise Time (CLK2) Point Te ‘Output Valid 2 25 ns CL = 100 pF (LAD) Delay Cy = 75 pF (Controls) Ten HOLDA Output 4 31 ns Cy = 75 pF Valid Delay 1 ALE Width 15 ns C. = 75 pF Ts ALE Output Valid Delay 2 18 ns | C.=75pFe) Tea ALE Output Invalid Delay 18 ns__| OL = 75 pre) To ‘Output Float 20 ns G, = 100 pF (LAD) Delay Gy_= 75 pF (Controis)(2) Tou HOLDA Output 4 20 ns C, = 75pF Float Delay Tro Input Setup 1 3 ns (Note 1) TH Input Hold 5 ns (Note 1) TitH HOLD Input Hold 4 ns. Te Input Setup 2 8 ns Ts ‘Setup to ALE 10 ns ©. = 100 pF (LAD) Inactive G._= 75 pF (Controls) Tia Hold after ALE 8 ns | C, = 100pF (LAD) Inactive Cy = 75 pF (Controls) Ts Reset Hold 3 ns Te Reset Setup 8 ns TW Reset Width 1281 ns__| _41.CLK2 Periods Minimum NOTES: 1.IAC/INTo, INT, INT2/INTR, INTs can be asynchronous. 2. A float condition occurs when the maximum output curren ‘no longer than the veld delay. MM 4826175 0151041 TSO a 2-80 #t becomes less than Io. Float delay is not tested, but should beintel 80960MC ° AC Specification Tables (Continued) 80960MC AC Characteristics (20 MHz) Symbol Parameter min [Max | Units ‘Test Conditions Ty Processor Clock 2 125 ns Vin = 1.5V Period (CLK2) Tp Processor Clock é ns | Vi, = 10% Point Low Time (CLK2) = 1.2 T3 Processor Clock 6 ns Vin = 90% Point High Time (CLK2) O.1V + 0.5 Voc. Te Processor Clock 10 ns | Vin = 90% Point to 10% Fall Time (CLK2) Point Ts Processor Clock 10 ns Vin = 10% Point to 90% Rise Time (CLK2) Point Te Output Valid 2 20 ns | C= 60pF (LAD) Delay Cx = 50 pF (Controls) Tox HOLDA Output 4 26 ns | C= 50pF Valid Delay 7 ALE Wiath 12 ns |G. = 50pF Te ‘ALE Output Valid Delay 2 18 ns [| G = 80pr@ Toa ‘ALE Output invalid Delay 2 18 ns | C= 50pFe) To Output Float 2 20 ns | Gj, = 60pF (LAD) Delay Cx = 50 pF (Controls)(2 Tou HOLDA Output 4 20 ns | C. = 50pF Float Delay To Input Setup 1 3 ns_[_ (Note 1) Ty Input Hold 5 ns (Note 1) Tr HOLD Input Hold 4 ns Tie Input Setup 2 7 ns Tis Setup to ALE 10 ns | C. = 60 pF (LAD) Inactive Cy = 50 pF (Controls) Tha Hold after ALE 8 ns inactive Ths Reset Hold 3 ns Tie Reset Setup 5 ns Ti Reset Width 1025 ns | 41 CLK2 Periods Minimum NOTES: 1. IAC/INTo, INT;, INT9/INTR, INT3 can bo asynchronous, 2. A float condition occurs when the maximum output current becomes less than Io, Float delay is not tested, but should be ‘no longer than the valid delay. MM 4826175 0151042 997 _ 28180960MC AC Specification Tables (Continued) 80960MC AC Characteristics (25 MHz) intel. ‘Symbol Parameter Min [Max | Units ‘Test Conditions Th Processor Clock 20 125 ns Vin = 1.5V, Period (CLK2) Ta Processor Clock 5 ns | Vu = 10% Point Low Time (CLK2) =12V Tg Processor Clock 8 ns Vin = 90% Point High Time (CLK2) = 0.1V + 0.5 Voc T Processor Clock 10 ns | Viv = 90% Point to Fall Time (CLK2) 10% Point Ts Processor Clock 40 ns Vin = 10% Point to Rise Time (CLK2) 90% Point Te ‘Output Valid 2 19 ns G1 = 60 pF (LAD) Delay Cy = 50 pF (Controls) Tex HOLDA Output 4 24 ns | OG, = S0pF Valid Delay Ty ALE With, 12 ns. C= 50pF Ts ‘ALE Output Valid Delay 2 18 ns__| CO, = 50pFe) Tea ALE Output Invalid Delay 18 ns__| O. = 50pF@) Te (Output Float 19 ns | Oy = 60pF (LAD) Delay Cy = 50 pF (Controts)(2) Ten HOLDA Output 4 20 ns ©, = 50 pF Float Delay Tio Input Setup 1 3 ns (Note 1) TH Input Hold 5 ns__| (Note 1) TH HOLD Input Hold 4 ns Te Input Setup 2 7 ns. Ts Setup to ALE 8 ns Cy = 60pF (LAD) Inactive Cx = 50 pF (Controts) Tia Hold after ALE: 8 ns | C= 60pF (LAD) Inactive 50 pF (Controls) Tis Reset Hold 3 18 Tie Reset Setup 5 ns TW Reset Width 820 ns | 41. CLK2 Periods Minimum NOTES: 1, IAC/INTo, INTs, INT2/INTR, INTg can be asynchronous. 2. A float condition acours when the maximum output current becomes less than Io. Float delay is not tested, but should be ‘no longer than the valid delay. M™@ 4826175 0151043 623 2-8280960MC HIGH LEVEL (MIN) 0.55V¢¢ LOW LEVEL (MAX) 0.8¥ 771080-6 cue ax reser ourpurs INIT PARAMETERS (BIDIC, lig) MUST BE SETUP 8 GLocKS rig To THIS CLK? EDGE INIT PARAMETERS UST BE HELD BEYOND THIS CLK2 EDGE aes Figure 15. RESET Signai Timing MH 4826475 O151044 757‘80960MC DELAY OF Sng MAM 15 REQURED 271080-24 Figure 16. Hold Timing Design Considerations Input hold times can be disregarded by the designer whenever the input is removed because a subse- quent output from the processor is deasserted (¢.9., IN becomes deasserted). In other words, whenever the processor generates an output that indicates a transition into @ subse- ‘quent state, the processor must have sampled any inputs for the previous state. Similarly, whenever the processor generates an out- put that indicates a transition. into a subsequent state, any outputs that are specified to be three stat- ed in this new state are guaranteed to be three stat- od. Designing for the ICE-960MC ‘The 80960MC In-Circuit Emulator assists in debug- ging 80960MC hardware and software designs. The product consists of a probe module, cable, and con- {rol unit. Because of the high operating frequency of 80960MC aystems, the probe module connects di- rectly to the 80860MC socket. MH 4826175 0151045 bTb 2.84 ‘When designing an 80960MC hardware system that uses the ICE-960MC to debug the system, several electrical and mechanical characteristics should be considered. These considerations include capacitive loading, drive requirement, power requirement, and physical layout, ‘The ICE-960MC probe module increases the load capacitance of each line by up to 25 pF. It also adds ‘one standard Schottky TTL load on the CLK2 fine, up to one advanced low-power Schottky TTL load for each control signal line, and one advanced low- power Schottky TTL load for each address/data and byte enable line, These loads originate from the probe module and are driven by the 80960MC proc- ‘essor. To achieve high noise immunity, the ICE-960MC probe is powered by the user's system. The high- speed probe circuitry draws up to 1.1A plus the max- imum current (icc) of the 80960MC processor. ‘The mechanical considerations are shown in Figure 17, which illustrates the lateral clearance require- ments for the ICE-960MC probe as viewed from above the socket of the 80960MC processor.80960MC aa case 271080-8 Figure 17. ICE-960MC Lateral Clearance Requirements MECHANICAL DATA Pin Assignment ‘The 80960MC is packaged in a 192-Iead ceramic pin grid array and a 164-lead ceramic quad flatpack. The 80960MC pin grid array pinout as viewed from the substrate side of the component is shown in Figure 18 and from the pin side in Figure 19. The 80960MC ‘ceramic quad flatpack pinout as viewed from the top of the package is shown in Figure 20. Voc and GND connections must be made to multi- ple Voc and GND pins. Each Voc and GND pin must be connected to the appropriate voltage or ground and externally strapped close to the package. Praf- erably, the circuit board should include power and ground planes for power distribution. Tables 5, 6, 7 and 8 list the function of each pin. NOTE: Pins identified as N.C., “No Connect,” should never be connected under any circumstances. MH 4826175 0151046 532 Package Dimensions and Mounting Pins in the pin grid array package are arranged 0.100 inch (2.54mm) center-to-conter, in a 14 by 14 matrix, three rows around. (See Figure 21.) ‘A wide variety of available sockets allow low-inser- tion or zero-insertion force mountings, and a choice of terminals such as soldertail, surface mount, or wire wrap. Several applicable sockets are shown in Figure 22. Package Thermal Specification ‘The 80960MC is specified for operation when its case temperature is within the range of —55°C to +125°C, The PGA case temperature should be ‘measured at the center of the top surface opposite the pins as shown in Figure 23. The ceramic quad flatpack case temperature should be measured at ‘the center of the lid on the top surface of the pack- age. WAVEFORMS Figures 24 through 30 show the waveforms for vari- ‘us transactions on the 60960MC’s local bus.80960MC. Of 02 0g Of oF OF OF Of Of of OF Of OF OF Og OF OF OF Off OF OW OF OF Of OF Of OF OF og of OF 08 OF OF OF OF 08 OF Of Of OF OF og of og osog og of of of og of of Og Og OF og og OF Og O¢ OF Og OF OF og OF OF og Og O¢ Og OF OF og og OF og og OF OF OS OS ofog of of of of of oF ososog of 08 of 50g OS OF OF OF J Of OF Og OF OF OF OF OF OF OF OF O¢ Og OF OF OF OF OY OF OY OB OFOS 271080-11 Figure 18. MG80960MC Pinout—View from Top (Pins Facing Down) MH 4826175 0152047 479 a 2.86‘80960MC. intel. O Og OY OF OF OF OF OF OF OF OF OFOLO OF Og OF OF OF OF OF OF OF OF OY OF OF O Og O¢ OF OF OF OF OF OF OF OF OF OF OF OF Og Og OF of 03 oF og Og OF osogog Og Og oO Og Og Og og Og Og Og OF Og og og OF og Og OF Og OF OF 08 0F OF OF OF 0 OF 03 Of Og OF OF OY Of OW OF Of OF Of OB OF Of Of Og OF OF O§ O§$ OF Of Of OF 03 $ 2 271080-10 Figure 19. MGB0960MC Pinout—View from Bottom (Pins Facing Up) 287 M™@ 4426175 0151048 305stsoouc intel. ef SSeb ewe SSeRRSSssBeeE eee Feeese al lalla] Is USTEIS|S|S|S/SEE IRIE] Mel Sel ele fe fe llels ileal el fof 2] 8] 8/3/55] 83 1s X 144 Ne = NS N42 NC Noo see ie Nee. a Lead 157 Ness no al ee 134 NC Pay 433_NC Wig asrnc NS 130 No Wiz 129 NC cic Cal) 127 WC dy. a uo), 2 wos0960Mc 124 NC 25H uy LS Mesa ne Udy Ta Veg 70 oe a Tie we oe as he nS N12 Ne tt Ne 10 ne py 108 NE 19 ITs 58: 107_NC ion a Vss. 105 NC ss 104 NC sfefelehelsieie tel sis tslaisis|s (slate ls! 2} z} elle [2 fzlzlle]z|z]s}elelle|2]2|zlel ale SSSSARRRR STE BS SSES SB geeeseaeueeeeeees Sggetepreseseyeeeeeee ¥ zr080-28 (Staggered pin arangomont is shown fr lary on Aci pactage asp nl ng) Figure 20. MG80960MC Pinout—View trom Top of Package MB 4826175 0151049 24) mt 2-88intel C 80960MC Table 5. MG80960MC (PGA) Pinout—in Pin Order Pin Pin Signal Pin Signal Pin | Signal AL ce LAD20 Ht wR M10_| Vss A2 c7 LADig He BE Mit Vec Aa ce LADs Ha | LOCK wiz | NG. A co LADs Hi2 [NC Mia | NG. AS cio | Voo His_[_NC. Mia | NG. AG cit_| Ves Ha [ NC. Mi Vss a7 12 INT3/INTA. a oT/R NZ. NC. AB C13 INT} J2 BE, NS Le Ag ct4 TAC/INTo J3 Vss Na NC. Ato D1 ALE vi2_ | Nc NS NC. AW b2 ADS w13 kes N6 NC. Aiz_| LAD, Ds HLDA/HLOR | Jt4 [_NC. NZ NC. A13__|_INT2/INTR p12 | Voc Kt BE, Ne NC. Al4_ | Voc b13 N.C. k2 FAILURE | No NC. Bt LAD2g piu | No. K3 Vs Nio_ | NC. B2 LAD2« Et LADeg K12_ | Voo nit | Ne. 83 LADz2 2 LADz6 kta [NG ni2_| No. Ba LADe2t 3 LAD2y kia | NG. nia_ | NC. BS | LAD e12 | Ne. ut nia | No. Be | LADis €13 | Vss 2 PA Voc 87 LADi2 E14 | NC. ir] Pa, NG. 88 Adio FA LADe29 ui2_| vss P3 Ne. Bo LADs F2 LAD us_| Ne. Pa Nc. B10 | LAD, Fa CACHE ua | No. P5 NC. B11 | CLK2 Fi2 | Nc. Mi Nc. P6 NC. B12 | LAD Fig_| NC. m2 [Voc P7 NC. Bis | RESET Fia [ NC. wa Vss. Pe N.C. B14 | Vss IE Gt LADay Ma | Ves. Pa NG. C1 HOLD/HLDAR | G2 | READY Ms | Voo Pio | Nec. cz LADas G3 BE, M6 NC. Pit NC. c3 BADAC Giz Nc. wz NG. P12 NC. ca | vec aia | NG. Me | NC. Pia | Vss cs | vss ais | Ne. Mo | Nc. Pia_| Voo NOTE: Pins identified as N.C. (“No Connect”) should never be connected under any circumstances, MH 4826175 0151050 Tho mw aL 2.8980960MC ADS AE BADAC BES H2 LADis | 85 Lig NC. PZ BE, Ga LAD g Aa ua NC. l2 BE2 J LADeo ic M1 READY G2 BES Kt LADat B4 M6 RESET B13 CACHE F3 LADz2 | 83 M7 Voc Al cLK2, Bit LADs | Bt MB Vo Ata DEN ut LAD 2g B2 wo Voc. ca oT/R fu LADas c2 M12 Voc. C10 FAILURE K2. LAD2g E2 M13 Voc D12 HUDA/HOLOR | D3 LAD | 3 Mia | Voo K12 HOLD/HLDAR | Gt (ADs | Et N2 Voc Ls TAC/INT C14 LADag al NO Voc. M2 INT, C13] LADso | Gt NA Voo MS: INT2/INTR A13_ | LADgy F2 NB Voc Mit INTS/INTA ci2 TOCK H3 NG Voc. Pt LADo Bz [NC 013 NC. N7 Voo P14 Loi Az | NC. om | NC NB Vs A2 LAD, B10 NC. E12 NC. No Vss Bid LAD3 co NC. E14 NC. nto | Vss cs LADy Att NC. Fiz NC. Nit Ves ci LADS, ato | No. Fa NC. Ni2 Vss E13 LADg 89 NC. Fria NC. Nia Vss 3 ao, Ag NC. a2 | NC Ni4_ | Vos k3 LADs 8 NC. Gia | NC. P2 = ui2 LADg AB NG. a [NG Pa Vss M3 LADio B8 No. Hi2 | NG. P4 Vss M4 Won AT NC. Hi3 NC. PS Vs M10 LADi2 87 NC. Hig NC. P6 Vss M dis c7 NC. tz NC. P7 Vss P13 die 46 Nc. 13 NC. Pe wiht Ht NOTE: Pins identified as N.C. ("No Connect”) should never be connected under any circumstances. MH 4826175 0151051 97T 2-90intel. eo96ome 1Q80960MC (CGP) Pinout—in Pin Order Pin Signal Pin Signal Signal 1 Ep 33 NC. NC. 2 ‘BES 84 Voo Ves 3 READY 85 NC. Veo. 4 BE, 86 NC. NC. 5 CACHE a7 Ves NG. 6 DVR 88 NC. N.C. 7 LADS; 89 NC. NG. 8 Wik LADs 90 NC. NC. 9 LADz9 LAD, a1 NC. NG. 10 LAD 39 LAD, 92 NG. NC. 1 LADe7 CLK 93 NG. NG. 12 LAD2g INTe 24 NG. NG. 13 ‘ALE LAD3 95 NO. NC. 14 LAD 26 LAD2 96 NG. NG. 18 ADS: LADo a7 NGC. NG. 16 LDA RESET 98 NG. NC. 7 NG. INTs 99 NG. NG. 18 Vss INT; 100 Voo NG. 19 Voc Ves 101 NC. NG. 20 Vss Voc 102, NG. NG. 21 Voc Vss 103, Vss NC. 22 Veo Voc 104 NC. NG. 23 Vss Vss 105) NC. NG. 24 Voc Voo 406 NC. NG. 25 Vss Vss 107 NC. NG. 26 Voc Voo 108 NC. NG. 27 HOLD NC. 109 NC. NG. 28 BADAC. NG. 110) NC. NG. 29 TAD 25, NG. 114 NC. NG. 30 LAD24 No. 112, NC Vs a1 LAD2g NG. 113 NC Voc [32 LADay NG. 14 NC. NC. 33 LAD22 NC. 115 NC. NG. 34 LAD ig INTo. 116 NGC. 187 NG. 35 TAD 20, NC. 17 NG. 158 Vs 36 LADi7 NC. 118 NG. 159 NC. 37 LADis NC. 119 Vss 160 TOCK 38 LAD g NC. 120 Voc. 161 FAIL 39 LAD 5 NC. 121 NGC. 162 DEN, 40 LAD 4 NC. 122 NGC. 163 BE2 at 1ADi3 NC. 123 NC. 164 Ves NOTE: Pins identified as N.C. ("No Connect”) should never be connected under any circumstances. Mi 4826175 0151052 636sone intel. ‘Table 8, MQ80960MC (COP) Pinout—in Signal Order Signal Pin Signal Pin Signal Pin Signal Pin ADS 15 (Ades 34 NG. 102 | NC. 148 ALE = LAD ag 30 NC. 104 NC. 149 BADAC 28 LAD25 29 NC. 105 NC. 150 BE 1 LAD2g 14 NC. 106 NC. 181 BE, 4 LADa7 cn N.C. 107 NC. 182 ‘BEp 163 LAD eg 12 NC. 108 NC. 155) BES 2 LADe9 9 NC. 109 NC. 156 CACHE 6 LAD 30 10. NC. 110) NC. 157, CLK2, 52 ADs: 7 NG. at NG. 159 DEN 162 COCK 160 N.C. 112 READY 3 OVA 6 NG. 7 NGC. 113 RESET ‘57 ‘FAILURE 161 NC. 68 NC. 114 Voc. 19 HLDA/HOLDR: 16 NC. 69 NG. 115 | Voc 24 HOLD/HLDAR, 27 NC. 70 Nc. 116 | Voo 22 TAC/INTo 75 NG. 74 NC. 17 | Voc 24 INT) 59 NG. 7 NG. 118 | Voc 26 INT2/INTR 53 NC. 73 NG. 121 Voc 6 TNTS/INTA 58 NG. 74 NG. 122 Veo 63 Ady, 56 NG. 76 NC. 123 | Voc 65 Ady 5t NC. 7 NG. 124 | Voc 67 Adz, 55 NG. 78 NG. 127 | Voc 84 LADs, 54 NC. 79 NC. 128 | Voc 100 LAD, 50 NG. 80 NC. 129 | Voc 120 ADs, 48 NG. 1 NC. 130 | Voc 126 LADg. 4 NG. a2 NG. 131 Voc. 154) AD? 4% NG. 83 NC. 132_ | Vss 18 LADs. a7 NC. 85, NG. 133 Vs, 20 LADg. 4 NC. 86 NG. 134 | Vss 23 LADio 45 NC. 88 NG. 135 Vss 25 LAD 42 NC. 89, NG. 196 Vss 60 LAD 43 NG. 90 NG. 137 Vss 62 LADs3 41 NG. ot NG. 138 Vss 64 LADi4 40 NC. 92 NC. 139 Vss_ 6 | LADi5 39 NC. 93 NC. 140 Vss_ a7 | LADie 38 NC. 4 NC. 144 Vss 103 LADi7 36 NG. 95 NG. 142 Vss 119) LADis a7 NC. 96 NC. 143 Vss 125 LADi9 34 NG. 97, NC. 144 Vss 153 LAD20 35 NC. 98 NC. 145 Vss 158 Ades 32 NC. 99 NG. 146 Ves 164 LADg2 33 NC. 101 NC. 147, wih 8 NOTE: Pins identified as N.C. ("No Connect) should never be connected under any circumstances. MM 4826175 0151053 772 2-92 Iintel. sovsome (ee #1 POSITION 1650 (16.497) 550 (13.959) 450 (11.421) 350 (8.883) 250 (6.345) 180 (3.807) 059 (1.269) .957¢4209) 728 (18.401) on | 001 (0.025)R Min TYP ‘SwEDce PIN STANDOFF .018(0.47) (@eucs pane 970(1.777) DA TYP BRAZE PAD 1.450 (36.802) F 1854108) L" -110(2.792) 271080-12 Figure 21. A 132-Lead Pin-Grid Array (PGA) Used to Package the MG80960MC M™ 4826175 0151054 609 mm 2.93S274 machined sockets ‘Other socket options ‘5558-1 version 55873-2 ‘Ame tt Phone 717-564-0100) mount C5192.776 cs132.01T6, 08132-0576, (6 Divsion Street) Warwick, Fl 02818 US. Phone 401-885-0485) ‘+ Amp tosts indicato 60% reduction in ingortion foros compared to *# Zoro insertion force (ZF) soldertat * Zero insertion foree (ZIF) Burnin incorporated (Hartsburg, PA 17105 USA * Low insortion force sodertal__ is shown below: * Low insertion force wire-wrap (©8182-02TG (two-lovel) €8182-08TG (thee ove) ‘= Low insorion force press-fit ‘Advanced interconnections ‘+ Low insorion force (LIF) solder AMP LIF SOCKET saz7e4 271080-13 ‘Cam handle lacks in low profile poston when MGBO960MC is installed (handle UP for open and DOWN for closed positions). ‘Courtesy Amp Incorporated PoolAWay* Mylar and Kapton Peol-A‘Way Carrer No. 132: Socket Terminal Carrs Kapton Carer is KS192 ‘+ Low insertion force surface ‘Mylar Carri MS132 Tanai | coarse Molded Plastic Body KS132 A srr Meenecsnon s 271080~14 ra ie 271080-15 Courtesy Advanced interconnections (PoakAWay Terminal Carers US. Patent No. 4442838) *Poet-A-Way is a trademark of Advanced Interconnections. Figure 22. Several Socket Options for Mounting the MG80960MC MB 4826175 0153055 545 a 2.94MEASURE CASE TEMPERATURE 152—PO Poa 271080-16 271080-17 Figure 24, System and Processor Clock Relationship Figure 23. Measuring MGB0960MC PGA Case Temperature (Tc) fo SSS SSA SSS) ~~ 271080-18 Figure 25. Read Transaction = deers O15305b 46] 2.95SS997 ASS 271060-10 Figure 26. Write Transaction with One Walt State MH 4826175 O151057 328 = 2.9680960MC_ 271080-20, ES A 27100021 Figure 28, Burst Write Transaction with One Wait State MH 4826175 0151058 254 2.9780960MC ox Lads Bp tf SSS (6 ous Stas) tous ‘oalgnnetuent 4 Si SiS Ss SSASS SS SSS bret SY WH | stern I te wont not SSS SS SSS ce She SS SSS Tl Figure 29. Interrupt Acknowledge Transaction MH 4826175 0151059 190 2-98intel. sno wm 4 SSS Pow IE sume Y y WMA MS SSS 271080-20 Figure 30. Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) REVISION HISTORY The following differences exist between this data sheet (271080-008) and the previous version (271080-007): 1. Military and Avionics Temperature Ranges and DC Characteristics have been added to the data sheet. MA 4426175 0151060 902 mm