Slide 1:

This first Slide is a reminder of the PD based calorimeter read-out architecture.

The architecture follow a tree structure that allow on one hand to distribute
commands to configure the detector and on the other to collect data from the photo
detectors attached to each crystal.
On one end we have the so call Hidra2 (2 nd version of the chip) boards housing the FE
chip. The FE chip, designed and developed by INFN Trieste, integrate a CSA followed
by a CDS and a Track and Hold circuit that allow a multiplexed read-out of the signal
produced by a set of 64 channel. The ASIC provide also information of those channel
whose signal amplitude, after integration, is above a two bits selectable threshold. As
far as each Hidra2 board manage up to 64 channels a total of 256 Hidra2 boards will be
required for the 16000 photodetector system.
Controlling of different stages of signal acquisition, collection of self-trigger
information and setting of the selected threshold is perform through 64 - LVDS
connections to the T+ROC2 boards.
Each T+ROC2 boards provide acquisition sequence and collect data from up to four
Hidra2 boards. Therefore 64 of such a boards would be required to equip the full
detector. Collection of data coming from the Hidra2 boards are packed and send using
LVDS signals to the T+ROC1 boards where at the present situation event are build and
shaped. Up to eight T+ROC1 boards each collecting data from up to eight T+ROC2
boards are required for the extrapolated case of having 16000 channels.
Depending of final DAQ architecture a third level of concentration can be required or
not.
Extrapolating the present power requirements, as measured from the different power
supplies to the situation of a 16000 channels detector a total of more than 500 W will
be required.
This huge number come mainly from the LVDS signal coming back and for the T`ROC2
boards and Hidra2 boards. Each LVDS signal requires around 20mW from a 3,3V supply
and there are 64 times 256 of such a signals.
Slide 2.
To check this assumption and to evaluate the contribution of LVDS interfaces to the
total power consumption, several measurements were carried out at Hidra2 boards
and at T+ROC2 boards. In the case of hidra2 boards this exercise was quite simple, as
far as each FE part CSA, CDS, LVDS IO has his own supply as shown in the schematic.
We only need to remove a 0 ohm pass resistor with an ammeter. After configuration,
and during normal operation at 1KHz trigger rate the (although trigger rate as well as
signal level, high or low, has a small influence on power consumption when speaking of
LVDS signals) total power consumption as measured on the main power supply is
539mA while 457mA are measured at ammeter located in the board VIO supply
(sourcing power to all the LVDS Tx/Rx).
Slide 3:
With this in mind and without VIO power consumption we get 4,22 mW / channel
@3.3V (close to the 3,75 of the data - sheet).
Slide 4.
The same exercise was repeated on T+ROC2 board, but some rework was needed to
separate the power supply of LVDS TX/RX on the board. T+ROC2 is a pure digital board
getting his power from a 1,8V regulator for the FPGA core, a 2,5V regulator for the
FPGA configuration memory and a 3,3V regulator for all the LVDS interfaces with
Hidra2 board and FPGA IO banks. To measure the LVDS Tx/Rx power requirements was
needed to separate those of them devotes to interchange signals with Hidra2 boards.
When doing so and during normal operation (1KHz and FE configured) 773mA where
measured on the main power supply and 610mA of them are required for the Tx/Rx
LVDS interfaces. When removing this part, result a total power dissipation per channel
of 2,15 mW.
As far as LVDS Tx/Rx with T+ROC1, due to his number, are implemented inside the
FPGA was not possible to do this exercise with T+ROC1 transceivers but final
communication with T+ROC1 is planned to be done through LVDS links. Further
reduction however can be reached if LVDS Tx/Rx are disabled when not needed, this is
not the case now, and only are needed few μsec over hundreds of μsec, suppling
related FPGA IO bank from a 2,5V regulator and DC-DC and use 2,5V LVDS between
T+ROC1 and T+ROC2.
T+ROC1 power dissipation is only 0,63 mW / Chn.
Slide 5.
With this in mind,
1. Locating T+ROC2 board near Hidra2 boards or merging them in the same board
and therefore changing from LVDS to CMOS communications between them .
2. Disabling the LVDS link between T+ROC1  T+ROC2 when not needed.
3. Lowering the power from 3,3 to 2,5 of T+ROC1  T+ROC2 interfaces.
4. Reducing the number of T+ROC2, moving from 4 Hidra2 / T+ROC2 to 8 Hidra2 /
T+ROC2 and then reducing the number of them from 64 to 32 although this
could have implication on the maximum trigger rate achievable and on the
reliability of the system.
we estimate a total power consumption lees than 150W for 16000 channels.
In summary, most of power consumption of the present architecture comes from LVDS
Tx/Rx between T+ROC2  Hidra2 boards and will be difficult to implement this change
for the test beam next year.