Subastil, Art Vincent D.

BSECE 2-5

Module 3 Assessment
1. Define in your own words the Field Effect Transistor
A Field Effect Transistor (FET) is an electrical component used to regulate the flow of
current in a circuit. It is a three-terminal semiconductor device, and the conductivity of a
channel between two of its terminals is controlled by an electric field. The source, drain,
and gate are the names of the three terminals.
A Field Effect Transistor can be thought of as an electrical current valve in simple
terms. The gate functions as an electronically controlled switch or amplifier by controlling
the current flow between the source and drain terminals when a voltage is applied to it.
Due to their critical function in integrated circuits, power amplifiers, digital logic circuits,
and many other applications, FETs are now important parts of modern electronic devices.
2. Discuss the operation of VMOS and its construction.
In comparison to conventional planar MOSFETs, VMOS (Vertical Metal-Oxide-
Semiconductor) is a form of power MOSFET (Metal-Oxide-Semiconductor Field Effect
Transistor) that is made to handle higher power levels. Power amplifiers and power
switching circuits are two examples of high-current, high-power applications that benefit
from VMOS's low on-resistance.

Construction of VMOS:
• A semiconductor substrate, commonly constructed of N-type silicon, serves as the
structure of the VMOS device. The foundation of the entire construction is the
substrate.
• In VMOS, the N-type substrate is transformed into a P-type area. The vertical N-
channel, the device's primary conducting channel, is formed after this P-region
serves as a foundation.
• On either side of the P-base area are produced the source and drain regions, which
are highly doped N+ regions. The connections for the current to flow into and out
of the gadget are located in these areas.
 • Between the source and drain regions of the P-base area, a thin insulating layer
of silicon dioxide (oxide) is generated. Between the gate electrode and the channel
below, this gate oxide layer serves as a dielectric.
• The gate electrode is created by depositing a metal layer on top of the gate oxide
layer. The vertical N-channel's current flow is regulated by this gate electrode.

Operation of VMOS:
• The VMOS is in its off state when no voltage is applied to the gate. Current cannot
flow from the source to the drain because of the P-base area, which acts as a
barrier. The P-type material serves as a natural insulator (depletion region)
between the N+ source and drain regions, which explains this.
• A positive voltage is given to the gate electrode to activate the VMOS. A conductive
channel is formed when the positive voltage induces an electric field in the vertical
N-channel that pulls free electrons from the N+ source and drain areas toward the
P-base region. Now, a low-resistance conduit for current to travel between the
source and drain terminals is made available by the conductive channel.
• When the VMOS is turned on, current travels from the source terminal to the drain
terminal via the conductive channel in the P-base region. Since the VMOS has a
substantially lower on-resistance than conventional planar MOSFETs, it is perfect
for high-power applications.
• In contrast to lateral MOSFETs, the VMOS has a vertical channel that enables it
to manage larger current and power levels. In contrast to lateral MOSFETs, VMOS
devices often have higher gate capacitance, which could result in slower switching
times.
3. Discuss the operation of UMOS and its construction.
Another variety of power MOSFET, commonly referred to as a U-MOSFET, is the
UMOS (Unipolar Metal-Oxide Semiconductor). As an enhancement-mode MOSFET, it
switches on and off when the proper voltage is applied to its gate terminal. Due to its
lower on-resistance and quicker switching properties when compared to VMOS, UMOS
is frequently employed in high-power and high-frequency applications.
Construction of UMOS:
• A semiconductor substrate, commonly comprised of N-type silicon, serves as the
UMOS device's base. The foundation of the entire construction is provided by this
substrate.
• UMOS doesn't have a P-base area, in contrast to VMOS. Instead, it employs an
N-type substrate covered in a thinly doped N-type epitaxial layer (N-epi). The body
of the MOSFET is made up of this N-epi layer.
• On the N-epi layer's surface, the source and drain regions are produced as strongly
doped N+ regions. The connections for the current to flow into and out of the
gadget are located in these areas.
• Between the source and drain regions, silicon dioxide (oxide) is formed as a thin
insulating layer on top of the N-epi layer. Between the gate electrode and the
channel below, this gate oxide layer serves as a dielectric.
• The gate electrode is created by depositing a metal layer on top of the gate oxide
layer. An electric field is created in the N-epi layer by providing a voltage to the
gate electrode, which regulates the current flow between the source and the drain.

Operation of UMOS:
• The UMOS is in its off state when no voltage is applied to the gate. The N-epi layer
creates an area that is only mildly doped and does not have enough electron
carriers to create a conductive channel between the source and drain. As a result,
the device is effectively off and cannot pass any meaningful current.
• A positive voltage is given to the gate electrode to activate the UMOS. By
generating an electric field in the N-epi layer as a result of the positive voltage,
electrons from the source area are drawn to the surface immediately beneath the
gate oxide. Between the source and drain areas, the collected electrons form a
conductive channel that enables current to pass through the device.
• When the UMOS is turned on, current travels from the source terminal to the drain
terminal via the conductive channel in the N-epi layer. Due to the conductive
channel's presence, the UMOS has a comparatively low on-resistance, which
enables it to effectively handle high-current and high-power applications.