SOME PARALLEL BUS DESIGN ISSUES

A typical parallel bus is the backplane bus shown below

Fig. 1 A typical backplane application using several plug-in cards

Previously, we have noted the performance of a parallel bus is limited by skew In this section, we shall consider bus hold, hot swap and ground bounce Later, we will study line termination and crosstalk, in a more general context

Bus Structure of a Simple Computer System To fix some ideas, we begin by examining a simple computer system

Fig. 2 shows the organisation of the classical Von Neumann architecture1

Although modern computers are implemented with more advanced architectures, often these structures are just tweaks of the Von Neumann architecture 6-1

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Memory unit

Input unit

Arithmetic logic unit

Output unit

Control unit Data and instruction Control signals

Fig. 2 The basic Von Neumann machine

The Central Processing Unit (CPU) consists of the Arithmetic and Logic Unit (ALU) and the Control Unit (CU) The CU coordinates the operation of the various parts of the computer The ALU performs all arithmetic ( +, , , etc.) and logic (AND, OR, XOR, etc.) functions The CPU reads data from and writes data into the Memory Unit. This unit also holds the program, consisting of a sequence of instructions that specify the overall operation of the computer The computer gets data from the outside world through the Input Unit, and returns data/information to the outside world through the Output Unit Typically, input/output (I/O) units will contain their own control lines to the outside world to coordinate their data transfers with the outside world

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For the actual physical implementation, it has been found the 3-bus structure shown below is most convenient in terms of maintenance and future expansions
Memory ROM CPU Data Bus Address Bus CU Control Bus RAM

ALU

I/O

Fig. 3 Bus organisation of a typical computer system

The CPU transfers data in words (4, 8, 16, 32 bits, etc.) to and from the memory unit and I/O device(s) through the Data Bus. If the data words each have n bits, then the data bus will have n lines The Address Bus specifies to or from which memory location or I/O device (port) that data transfer is to occur. The address bus will contain m lines for an address space of 2m memory locations and 2m I/O ports The Control Bus contains a number of lines. These lines carry timing information such as memory read and I/O write.

Example (Memory Read) Step 1 Step 2 Step 3 Step 4 CPU places memory address on the address bus CPU sets memory read line on control bus high Memory unit places data from the memory location whose address is on the address bus onto the data bus CPU brings memory read line on control bus low and clocks data on the data bus into its own internal memory (register)

In the above example, it is important that the CU allows sufficient time in and between each of the steps for the signals to stabilise and for them to meet the set-up and hold time requirements of any clocked devices in the system

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Bidirectional Bus

The data bus in the simple computer of Fig. 3 is bidirectional, i.e., data can be driven from the CPU into memory, or be driven into the CPU from memory

In other words, on each line of a bidirectional bus, a number of transmitting and receiving devices are connected
Circuit Module #1 Bus driver Bus line of interest Another bus line Circuit Module #2 Circuit Module #3

Fig. 4 Typical bidrectional bus

To avert the problem of transmitter outputs driving each other, IC manufacturers have come up with bus interface circuits whose transmitter output can assume one of three states: (see, for example, Reading List, TI SN74ABTE16245) logic 1 logic 0 and high-impedance

When a transmitting device is in the high-impedance state, its output is virtually disconnected from the bus

An external control logic is used to ensure only one transmitter is allowed to drive the bus The control logic will select only one transmitter and de-select the remaining transmitters The selected transmitter will then place a logic 1 or 0 on the bus line while the de-selected transmitters will put their output circuits into the high impedance state, in effect, disconnecting themselves from the bus and not interfere with the operation of the selected transmitter

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Slow or Floating CMOS Inputs

In recent years, CMOS and BiCMOS have become the dominant technology in the semiconductor market It is important, therefore, to understand their characteristics and be aware of techniques that will overcome their shortcomings

One problem that can arise in bus applications is that, unused CMOS inputs must not be left floating Specifically, CMOS inputs can be left effectively floating if all transmitters connected to the same bus line entered the high-impedance state at the same time

There are two phenomena that can damage the CMOS device: through currents and high frequency oscillations

3.1 Through Current

Fig. 5 shows the input stage of a CMOS gate

Fig. 5 Input structure of a CMOS device

If vI is around VDD 2 , then QP and QN can both be ON (or slightly ON) and a large current, known as through current, can flow from VDD to GND through QP and QN

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Fig. 6 plots the supply current versus the input voltage of a CMOS gate

Fig. 6 Supply current against input voltage of a CMOS device

Evidently, the input voltage must switch from low to high, or high to low, as rapidly as possible to minimise the amount of power that is dissipated by the device

Table below lists the maximum input transition rise and fall rates for various CMOS familes

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3.2 High Frequency Oscillations

Fig. 7 shows an inverting buffer stage with the parasitic inductances of the package leads ( LP ) and the capacitive load ( CL ) at the output

V+

CL

Fig. 7 Parasitic components that can cause circuit oscillation

Suppose vI is low and the output is high As vI (slowly) increases past the threshold voltage, the output will switch low The surge in load current iO will cause a voltage spike in VGND which will make v i to appear to dip low suddenly (with respect to VGND ). This in turn will cause the output to switch high By a similar argument, the induced -ve voltage spike at V+ due to output switching low to high will cause the threshold voltage of the gate to dip down. This in turn will cause v i to appear to dip above the threshold voltage and the output will switch low

Fig. 8 shows what happens at the output of a CMOS gate when its input is slowly raised

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Fig. 8 Oscillation at the output of a CMOS circuit whose input is triggered by a signal with a rise time of tr = 200 ns

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Bus Hold

A simple solution is to connect all unused (floating or open) inputs to VCC or GND or via a resp. pull-up or pull-down resistor

Pull-up resistor

VCC

Pull-down resistor

Fig. 9 Pull-up and pull-down resistors

However, pull-up and pull-down resistors can cause additional power dissipation and increase component count Also, when using todays narrow pitch packages, there may not be enough space on the PCB to add pull-up and pull-down resistors Moreover, in certain test conditions, inputs may be left open, and as discussed, in bus applications it may happen that the inputs are effectively floating when all devices driving the bus are in the high-impedance state

Many bus interface circuits now include a bus hold circuit in their input

Resistor lessens driving effect of 2nd inverter on bus

Fig. 10 Bus with bus hold circuit

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In CMOS, it is not easy to implement a purely ohmic resistor Fig. 11 shows a stand-alone 10- or 16-bit bus hold device where the feedback resistor has been replaced by a configuration known as a transmission gate
x
Input clamping diodes to protect gate input from excessive input voltages Effectively a resistor cheaper to make in a CMOS chip When x is 1, PMOS is ON and NMOS is OFF When x is 0, PMOS is OFF and NMOS in ON

Fig. 11 Stand-alone bus hold circuit (SN74ACT107x)

Transmission gate is effectively a dynamic pull-up/pull-down resistor

Fig. 12 shows the input structure of two other CMOS families with bus hold circuits

Fig. 12 Bus hold circuits for ABT/LVT and ALVC/LVC families

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Hot Swap

5.1 Introduction

In many applications, there is a requirement to exchange modules in an electronic system while the supply voltage remains on Examples include electronic telephone exchanges, the switching control centre of an electric utility, air traffic controllers, medical life support systems, etc

Above procedure is known as hot swap (or live insertion, or hot plug, or hot insertion)

Hot swap is also a feature of USB devices It allows an external drive, network adapter or other peripheral to be plugged into a computer without having to power down the computer first

Hot swap is really a system design issue It costs money to support therefore one must first perform a careful system analysis before proceeding

Suppose hot swap has been deemed to be necessary One must then consider the question: Must the system continue to function during hot swap?

If NO, then all that is required is a simple method to safe the software and the hardware that the module controls If YES, then one must examine each module to determine how its possible failure and replacement can be handled Specifically, one has to consider whether the system is to be fault tolerant, i.e. it will continue to function as if there is no malfunction in any of its modules; or whether the system is to have high availability, i.e. it will continue to function but with reduced capabilities

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Fault tolerant systems are expensive to implement since they require redundant modules, and logic to detect and replace the faulty module with the spare module or one of the spare modules

Another question that one must ask when designing systems with hot swap is: Is the purpose for supporting hot swap to enable repair, reconfiguration, or both?

Supporting hot swap for repair means the system can detect a failed module, take it off-line, notify the operator, and when the module is replaced, qualify the new module for system operation and bring it smoothly back on-line Reconfiguration can be accomplished as either replacement, enhancement, or both. Replacement means replacing a functioning module that is close to its use-by-date. Enhancement means replacing the module with a better module. It can also mean adding more modules to the system

5.2 Hot Swapping in a Bus System

Goal is to perform card insertion or extraction and maintain data integrity on the system bus, while preventing damage to components on the host system or on the inserted/extract card

Hot swapping can be done with components that provide different levels of bus isolation

In the first level, the components should be constructed such that they will not be damaged in an unpowered card while connected to a live bus. Moreover, their input and output pins if connected to the bus must not load down the system bus, and the outputs must remain in the high impedance state and have a power-off disable feature that eliminates current paths to VCC due to the diodes and parasitic elements In the second level, we require in addition, circuitry on the component that will keep its bus outputs in high impedance during power-up or power-down In the third level, we further require circuitry that will pre-charge the bus to a chosen voltage level in order to reduce glitches caused by the bus impedance and capacitance at the hot swap interface

The aforesaid 3 levels of isolation will be discussed in more details in the sequel

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We begin by considering the construction of a typical IC as shown in Fig. 13

Fig. 13 Diodes at the inputs and outputs of a typical IC

D1 is integrated into most CMOS devices for electrostatic discharge (ESD) protection. Its function is to limit the positive voltages at the circuit input D2 is implemented in most devices to limit undershoot due to line reflections (see later), and for some ESD protection D3 is implemented in most CMOS devices for ESD protection. In bipolar devices, D3 is a parasitic diode, except for bipolar devices with opencollector or tri-state output where they can be eliminated D4 is a collector-to-substrate or drain-to-substrate parasitic diode. In bipolar devices, a Schottky diode is often integrated to limit undershoot arising from line reflections, while in CMOS devices, an additional diode is often incorporated for ESD protection

The difficulties with the device of Fig. 13 when used in a hot swap application are:

If the device is unpowered and if either the input or output is inserted into an active bus, current will flow through D1 or D3, possibly damaging them or the active system. Also, the bus voltage will be disrupted by being momentarily pulled down to the inactive VCC During extraction or power-down, D1 and D3 present a path to VCC and can pull down the bus voltage to the decaying VCC level

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Most bus interface devices now have D1 and D3 removed They also have a power-off disable circuitry to protect the output parasitic diode D3 Such devices meet the first level of isolation required for hot swapping

For the second level of isolation, most bus interface devices now also include a power-up/power-down tri-state circuit to keep the outputs in high impedance during power sequencing, as shown below

Fig. 14 Power-up/power-down tri-state circuit

During power-up, the collector of Q1 follows VCC which is interpreted as a HIGH at the NOR gate input. This disables the output buffer regardless of the voltage on the enable ( OE ) or data pins. As VCC rises, the Q1 baseemitter junction becomes forward biased thus turning on Q1 and pulling the collector of Q1 LOW and the NOR gate input LOW. Depending on the signal at the OE pin, the output buffer can now be enabled or disabled, as required for normal operations During power-down, Q1 remains on to keep one input of the NOR gate LOW, keeping control of the output buffer to the OE pin. When VCC drops below a certain threshold voltage, Q1 turns off and the power-up/power-down circuit keeps the output buffer disabled

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Finally, we consider the third level of isolation When an unpowered card is plugged into an active bus or backplane, the input capacitance of the individual signal lines at the interface must be charged to the instantaneous voltage on the corresponding bus line. These additional currents can distort the signal that is being transmitted on that bus line at that instant Fig. 15 shows the equivalent circuit that describes the above situation where Cs is the capacitance of the unpowered modules driver, traces, and connector, Ls is the inductance of the connector contact and circuit trace, Vi is the initial voltage of the module connector pin, and Vq is the quiescent voltage on the bus prior to live insertion

Fig. 15 RLC model of live insertion event

By solving the circuit shown in Fig. 15, it can be shown that a glitch can occur on the bus, and if the amplitude and width of the glitch is sufficient, a receiver on the bus can interpret the glitch as a valid signal and bus errors will occur

Fig. 16 Glitch on bus signal line due to live insertion

The size and width of the glitch can be minimised by reducing the voltage difference between Vi and Vq . This can be achieved by applying a pre-charging
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voltage to the cards signal lines as it is being inserted into the active bus. Since Vq can be HIGH or LOW, a pre-charge voltage somewhere near the middle of HIGH and LOW is normally chosen Fig. 17 gives the simplified schematic of a pre-charging circuit

Fig. 17 Simplified pre-charging circuit

See Reading List, Philips CBT6800 and TI SN74ABTE16245, for the data sheets of two bus interface devices

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Apart from the signal lines, one must also consider the disturbance on the power supply lines of the bus caused by the insertion/extraction of a card When an unpowered card is inserted, current will surge into the card (inrush current) thereby causing a (negative) glitch on the power lines Likewise, when a powered card is extracted, the supply current to the card will be interrupted suddenly thereby causing another glitch (positive) Power supply glitches can be overcome by including a power conditioning IC on the card. This IC controls the rise and fall times of VCC on the card as the card is being inserted or extracted

Finally, by considering the current flows to and from the devices on a card as the card is being inserted or extracted, one can conclude that the cards bus connector pins should be staggered as shown below

Fig. 18 Bus connector with staggered pins

Thus, during insertion, Ground is connected first, followed by a signal to precharge the signal lines, then VCC , and when all devices on the card have been properly powered-up, the signal lines In the case of extraction, the output signal lines are first put into the high impedance state. The signal lines are then disconnected, followed by the power lines. This ensures the signal lines are in a known state (high impedance) when they are disconnected

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Ground Bounce

6.1 What is Ground Bounce?

Ground bounce occurs when the output of a logic device on a logic chip switches from a 1 to a 0, and a disturbance is observed in the otherwise constant output voltage of another logic device on the same chip

Fig. 19 below shows a circuit model that helps explain above phenomenon Note careful distinction between the ground and power supply lines of the board, and the ground and power supply lines that run inside the chip
Board VCC
Inductance of package pin, bond wire, etc.

Digital IC Chip Chip VCC v1(t) = 1

Board GND

v i1(t)

vo1 (t)

VIH VIL

v2(t)

v3(t)
v i2(t) vo2 (t) i(t)

Board GND

Chip GND
vG (t)

CL

Board GND Fig. 19 Circuit model of ground bounce

Suppose initially (i) (ii) (iii) Input of quiet device v i 1(t ) is held high such that v o1(t ) is at 1 Input of active device v i 2 (t ) is at 1 such that v o 2 (t ) is at 1; and
vG (t ) = 0 , i.e., chip ground is at same voltage potential as board ground

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At t = 0 , input of the active device switches from 1 to 0 Following sequence of events will then take place (i) Output of the active device will start to conduct such that v o 2 (t ) is effectively connected to the chip ground, and the charge that was stored in CL will start to be discharged through the active device, i.e., i (t ) will start to flow where
i (t ) = CL dv o 2 (t ) dt

(1)

(Minus sign appears since we define i (t ) to flow out of the positive terminal of CL ) (ii) Change in i (t ) will cause a voltage vG (t ) to develop across the parasitic inductor L
vG ( t ) = L di (t ) dt

(2)

v o2 ( t )

i (t ) = CL

d dt

v o2 ( t )

0
d v G ( t ) = L dt i ( t )

v i1( t ) = v1( t ) vG ( t )

v3 ( t ) = v o1(t ) + v G (t )

Fig. 20 Waveforms due to active device switching from 1 to 0

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As can be seen from Fig. 20, 1 to 0 transition in output of the active device can cause a ripple to appear in v 3 (t ) , output of the quiet device
Ground bounce is bounce in the chip ground relative to the board ground

Ground bounce can become particularly severe if a number of devices on the same chip switch their outputs from high to low simultaneously In this situation, the output sink currents are summed together as they flow out of the chip through the inductance in the chips GND pin. For example, two devices switching simultaneously will almost double magnitude of the bounce relative to when only one device is switching

6.2 Potential Ill-Effects of Ground Bounce

v i 1(t ) is voltage at input gate of the quiet device relative to the chip ground. It determines logic state of the quiet device

A potential problem is that the dip in v i 1(t ) can cause the output of the quiet device to switch momentarily to 0 if v i 1(t ) drops below the input low threshold of the quiet device

Another potential problem is with v 3 (t ) , input voltage of the device that is connected to the output of the quiet device Assuming the chip ground of the receiving device is at the same voltage potential as the board ground, the dip in v 3 (t ) can cause the receiving device to switch momentarily to 0 if v 3 (t ) drops below its input low threshold voltage

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6.3 Cures for Ground Bounce

Ground bounce is unavoidable, but there exist techniques to reduce it

From IC manufacturers perspective (i) From Eq. (1), we see peak value of i (t ) can be reduced by slowing down falling/rising edge of the output voltage of the active device This can be achieved through a proper design of the output stage of the active device (ii) From Eq. (2), we see vG (t ) can be reduced by reducing di (t ) dt But i (t ) must flow through output stage of the active device. Therefore, as with first technique, di (t ) dt can be reduced through a proper design of the output stage of the active device (iii) From Eq. (2), we see vG (t ) can also be reduced by reducing L Techniques to achieve this include: (a) reduce length of the GND pin through surface mount chip packaging; (b) reduce length of the bond wire by, for example, providing multiple GND pins on the chip or relocating the GND pin so that it is more centrally located with respect to the devices on the chip; (c) minimise shared inductance on the chip by connecting the ground of the devices to the common GND pin through a star connection Note however that, reducing L does not necessarily reduce ground bounce to the extent one might expect from Eq. (2). This is because by reducing L , one gets a corresponding increase in the edge rate of v o 2 (t ) . (iv) With reference to the plot of v i 1(t ) in Fig. 20, we see that by providing separate driver and logic GND pins on the chip, we can prevent the bounce from appearing in v i 1(t )

From circuit designers perspective (v) If a chip has many logic devices, try not to switch them simultaneously

(vi) Keep the load as close as possible to the chip to minimise the loop inductance (vii) Try not to connect a capacitive load to a logic devices output directly. Insert a (small) resistor between them to damp down the offending current i (t )

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(viii) Use multi-layer boards with power supply and GND planes. Solder the chips power pins directly to the planes to ensure lowest possible power line inductance (ix) Use decoupling capacitors, preferably one per chip and located close to the ground pin. Purpose of the capacitors is to filter out the bounce ripples in the supply lines before they affect other chips on the board (x) Avoid sockets because of their relative large inductances

6.4 VCC Bounce VCC bounce is dual of ground bounce

It occurs when output of the active device switches from 0 to 1

During VCC bounce, current flow from VCC , through output stage of the active device, to charge up CL (see Fig. 19) Sudden surge of current through the inductance in the VCC pin will cause the chips internal VCC line to dip down first, then pulse up

Aforesaid bounce in the chip VCC will result in a momentary change to the quiet devices input threshold voltages Bounce in chip VCC will also affect stability of the quiet devices output voltage These momentary changes may change the state of the logic devices driven by the quiet device

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