'US00902698252 2) United States Patent (10) Patent No: US 9,026,982 B2 Liao 4s) Date of Patent: May 5, 2015 (64) WIRING BOARD DESIGN SYSTEM AND. 66) References Cited WIRING BOARD DESIGN METHOD US. PATENT DOCUMENTS (71) Applicant: Simplify Design Automation, Ine. Sunnyvale, CA (US) 6385,758 BL* $2002 Kikuchi etal gio aouiioneto39 AL* 32011 Kumagai eal To 12 Dor2o2s4K21 Al* 102012 Babe 76136, (72) Inventor: Zen Z. Liao, San Ramon, CA (US) POREIGN PATENT DOCUMENTS (73) Assignee: Simplify Design Automation, Inc, Sao Ramoa, CA (US) » 2005-26702 A 972008 (4). Notice * citod by examiner Subject to any dislaimer, the term of this pateat is extended of adjusted under 35 Pee oie Primary Examiner — Brian Ngo 74) Ainorney, Agent, or Firm — Westerman, attr, (21) Appl. Nos 14/196,665: Daniels & Adrian, LLP 4.2014 on, ABSTRACT An object ofthe present invention ist provide witing board ‘design system aad wiring bound design method to determine (22) Filed: Mi Prior Publication Data US20140250118 1 Sep. 4,2014 ‘seomponent anda wiring pattem in real-time when designing ‘a wiring ona eicuit board, The wiring bound design system Related US. Applicaton Data provides aloud service fora terminal which s used by users via a network. When to arrange components on the circuit (60) Provisional application No. 61/772,269 filed on Mar. board. while pushing out automaticaly wirings which are 4.2013. ‘overlapped with the components on the arranging position, the wiring board design system secures @ space on that arrange the component, The wiring processing is performed ‘aulomatically andthe fine adjustment such as rotation, move- G1) Incl Gor 1750 (2006.01) (2) tet of ananged components is perfomed atomically i GO6F 17/5077(2013.01) _ocessary. The procestng for equalization fs performed 0 a (58) Field of Clasitcation Search {oboe egal wring densi on Be cl bond : "16/126, 137,136,115 Sec aplication ifr complte such hor. 12.Clalns 17 Drawing hess i anf Tomei ~~ swererat ByU.S. Patent May 5, 2015 Sheet 1 of 17 US 9,026,982 B2 FIG. |US 9,026,982 B2 Sheet 2 of 17 May 5, 2015 U.S, PatentU.S. Patent May 5, 2015 Sheet 3 of 17 US 9,026,982 B2 FIG.3A. Circuit board Component A — O00 Wiring] Component B FIG.3B. Lb Circuit boardU.S. Patent May 5, 2015 Sheet 4 of 17 US 9,026,982 B2 FIG.4A Circuit board Component A | OO OOOO 209000 Component ¢ Ooo O° | — Wiring O00 Oo OO00000 FIG 4B Cireuit board DOOOOO] component A Wiring] Component. B~| Component B OO OO OO0000US 9,026,982 B2 U.S. Patent May 5, 2015 Sheet 5 of 17 FIG.SA Component Al Component. BI Component Ct Component D1 \ \ Gomponent A2 Component At Component A2 Component B2 FIG.SB Component BI Component 62 Component Ct Gomponent D2 Component D1 Component B2 \ Component: 62 Component D2U.S. Patent May 5, 2015 Sheet 6 of 17 US 9,026,982 B2 FIG.6A Component A Component B Component ¢ Wiring Wiring Uy FIG.6B iring W Component A Component B age s WiringU.S. Patent May 5, 2015 Sheet 7 of 17 US 9,026,982 B2 FIG.7 |_—conponent A L—Wiring Wiring LLEELTrT ee _~Component BU.S. Patent May 5, 2015 Sheet 8 of 17 US 9,026,982 B2U.S. Patent May 5, 2015 Sheet 9 of 17 US 9,026,982 B2U.S. Patent May 5, 2015 Sheet 10 of 17 US 9,026,982 B2U.S. Patent May 5, 2015 Sheet 11 of 17 US 9,026,982 B2 FIG.11 User logs in a user terminal oe Sanna User authentication Step 1 Step 2 Step 3 Stop 4 [Main screen displayed in a wiring board design service | Stop 5 = out Gannnunne ——— f ows veeenietee ae ermine dowMay $2018 Sheet 12 of 17 US 9,026,982 B2 FIG.12 To select a circuit board Stept00 To arrange a component on a specific position on the circuit board To process by the component Stepto1 ranging part Wiring processing part to process wiring between components Steploz Constrsint processing part Stepl03 Fine adjustment by the component arranging part and Steplo4 ‘the wiring processing part e To store/output wiring board design data Stopt05U.S, Patent May $2018 Sheet 13 of 17 US 9,026,982 B2 FIG.13 To obtain component information Step 120 To specify overlapping a component and a wiring at an arranging position Step 121 “To pulling out the overlapped wiring from the arranging position of the component. To rearrange, To secure 2 space to arrange @ component Step 122 To display arranging processing “Tho arrangoment sucooeded! Reason of cannot arrange” Stop 123, the entire wiring Step 124 To process by a constraint processing part Step 125 Signal interference simulation Step 126US 9,026,982 B2 Sheet 14 of 17 May 5, 2015 U.S, Patent FIG.14A 3. s 2 . Ee a a see BEEbEEEENerE | = BEF RGREEN Sty BPGGEGee Eek ~S . Bebbbie asec See sesigacosce S Ress Pr fl4lal 200U.S. Patent May 5, 2015 Sheet 15 of 17 US 9,026,982 B2 FIG.15 [step 200 To arrange 9 component on a circuit board Stop 201 yes The component. and wiring are overlapping Step 202 To eliminate the overlapping of the ‘component. and wiring To pick ot wir ine Torrotate the eomponant T terminal having ‘the sane signal with the component terminal is arranged? Step 208 ta Step 205 To spectTy oF approve the conmecting object of the termina! Step 204 To change or approve the comecting object of the termina! To start the caloulation of @ wiring route ‘Step 208 To select an algorithw for calealating @ wiring route ca Stop 208 2 component Step 208 i tional ly? No Fine adustment by the component eranging par ond wiring processing part Step 210 Stop 211 To store/autput crcut board design dataUS 9,026,982 B2 Sheet 16 of 17 May 5, 2015 U.S, Patent Lefer 9T OIA ~ 29hU.S. Patent May 5, 2015 Sheet 17 of 17 US 9,026,982 B2 FIG.I7AUS 9,026,982 B2 1 WIRING BOARD DESIGN SYSTEM AND WIRING BOARD DESIGN METHOD. TECHNICAL FIELD ‘The present invention i related 1 a system and a method Jor designing a wiring board to determine eomponent and a ime when designing a wiring on 3 be performed by using other dedicated software. Because the signal interference simulation is not @ main purpose of the present invention, the detailed explanation is omitted, [Wiring Algorithm] ‘Various algorithms are able wo use as the algorithm forthe \wiring processing. An algorithm for finding a route erween ‘wo points in pin soften used forthe wiring processing for the wiring of the circuit board. For example, typical algo- rithms published in the nen literatures ac used forthe wiring processing ofthe circuit board wiring Various algorithms and theie published hiteratures: Lee Algorih: C.¥, Lee, “An algorithm for path connections ‘and iis applications”, IRE Trans, Eleewonic Comput EC-10(), 1961, p 346368. Hadlock algorithm: Hadlock, “A shortest path algorithm for sid graphs,” Networks, 1977, Soukup Algorithm Soukup, "Fast maze router” DAC-8. ‘Combined breadh--rst and depth- rst search, Mikami Tabuchi algorithm: Mikami Tabuchi,"A computer rogram for optimal routing of printed ereuit connectors? THIP, H47, 1968. Hightower algorithm: Hightower, “A solution to Tine-routing problem on the continuous plane.” DAC-69, Next, here explsined an example ofthe wiring algorith ‘used in the present embodiment of the present invention to determine the wiring rote ofthe wiring board by calculation For example, Loe algorithm, Rip-up-and-eroutc wiring ‘mechanism, ec. can be exemplified as the wiring algorithm used in the present invention. The wiring algorithm of the embodiment of the present invention is not restricted to these algorithms, and also can use known optional algorithms such as abovesmentioned witing algorithms [Explanation of Lee Algorithm] ‘The outline of Lee algorithm willbe described with refer- cence of FIGS. 144 and 143 as an example of « wiring algo- thm use for calculation of wiring route of the wiring board of the present embodiment of the present iavention. Here scribed a procedure to finda route between Wo points of a point Sanda point T drawn on a circuit board 200 shown in FIGS, 14A and 14B, Lee algorithm can find certainly the shortest route connecting 1Wo given points, However, if the circuit board 200 becomes large and the ssumber of componeats increases, there was a disadvantage that the caleulation required a huge amount of memory and ‘using it inthe industry was dificul. ln dhe present inveation becatse the ealeulation speed is inereaed by asing a cloud ‘computing and a server having high processing eapacity. the ‘aletlation spesd is high andthe response timetatheend-user fan be reduced, Therefore, forthe end-user, i can overcome the disadvantages that Lee algorithm required huge memory ‘andthe response time was slow util output the ealeuation results and it becomes no need to consider about thereof Leealgorithm for finding a route between to points com prises of the next stops. First, it stars. from a initialization ‘ep. Inthis step, the wiring board is divided into plural areas For example, as shown FIG. 144 and FIG. 148, the wiring ‘oats dvided into squares with the same sie of horizontal and vertical sides Here, the route from the start point Sto the ‘al point Tis ealeulated. Ia the figure, the square, havingUS 9,026,982 B2 17 ‘obstacles tobe avoided inthe route, has hutchings by slanted solid lines. Fach squares has a given number Irom the start point to the goal point. Fins, the point S i selected and ths square is given “0”. Bach squares given aumbers ws going frm the point Sto the next square. For example, as shown in FIG. 14A, the square next tothe point Sis given "I" therefore squares have "I". ‘This is figured out that this isa distance from the S point Going forward toa next square from the next square having “1°, adits applied by "2". Thisis repeated uatl aching the point T of the goal point. The squares showing the obsieles not be given numbers Therefore, applying numbers tothe squares means a die tance from the point S and it coatiaues until reaching to the point Tof the goa! point or an squares to apply numbers. To eneralize, a square that exists next o the square having mark and has sy marks givensa mark “i+. When reaches to the point T, the process applying numbers to the squares is ‘cancelled and a process for bute determination is started. > ‘When to detemnine a oute from the point T to the point S, while adding a number, one smaller than the numberof the Point T, ta 8 path, it contioues until reaching tothe point S. Inthe figure, thisrouteisillustrated by thearrow, Whea this {is applied tothe wiring ofthe presen inveation, the point Sof the stat point andthe point T of the goal point ae the (Wo points fora route calculation. For example the point Sand the point T correspond the terminals of the component A and the ‘component Bt respectively. ‘The hatched) squares showing ‘obstacles correspond to newly arranged components, already frranged components, wirings, area that cold nt be wired ‘andthe ike, Although, in this example, the eirevit board 200 js divided into squares, but con be divided into any quad angles or tangles inseod of squares and the explanation is ‘omitted becouse its way ofa route decision isthe same, A detailed procedure ofa searching ofa wiring routing of the wiring board design is shown in FIG. 18. Firs, a compo- nent is arranged inthe ctenit boaed of the wiring board (Step 200), Its confirmed whether wirings that are already wired ‘existin the arranging postion ofthe component (Step 201) In ‘ther words, its confirmed whether the component that are ditionally aranged and the wiings that are already wired fre overlapped. If not overlapped, moves to Step 203. If ‘overlapped, a processing is performed to overcome the over- Tapping (Step 202), For example, a processing to obtaina space for arranging ‘component by pushing out the wirings that are overlapped the ‘component snd wings around thea, a peoeessing for rot Jing the component and the lke are performed. The situations Pushing out the wirings overlapped the component and wir- Ings around them are shown in FIGS. 3, 38,4 and 4B and about them are explained in detail in their explanation. ‘component hus one or more terminals for connecting 10 & ‘wiring, anda connecting object connecting to this terminal by Wiring is determined. In the program. itis the wiring teminal ‘withthe same atributes as that ofthe terminal ofthe added ‘component, in ther words, that of the teminalinpotting oF ‘outpting the same signal asthe inpotting or outputting sg> nals ofthe terminal ‘Ths, itis confinmed whether tis temninal and the terminal having the same signals are already atranged on the wiring board (Step 203). Iraconnecting abject forthe terminal the ‘ditional component exists, this is approved oF changed (Step 204), If @ connecting object for the terminal of the ‘additional component does not exist, connecting object for the terminal of the additional component is designated and approved (Step 208). Thereby, the calculation of a wiring 0 o 18 outed started (Step 206) First, the ealculation of the wiring restarts frou selecting algorithms touse inthe ealeuation (Step 207), ‘The algorithm used inthe wiring toute can use any wiring processing algorithm above-mentioned. And, fora specific component or a special-purpose wiring board, although a special lgorithm can he used, but because the purpose of the present invention is not intended to invent like these lgo- rithms, the detailed explanation is omitted. When the algo- thm is selected, the wring route calculation stats according to the selected algorithm (Step 208). When the wiring route calculation finished and the wiring route ofthe component is ‘determined, itis confiemed whether the next component is arranged (Step 209) ‘fa component is arrange aklitonally, above-mentioned pracessings of Steps 200-208 are repeated. When the arang- ‘ng the component and the wiring route are determined, the component aminging part and the wiring processing part perform the fine adjustment for the component arranging and ‘the wiring route (Step 210), As he fine adjustments fnished the component arrangement and the wiring route are deter ‘mined finally: Thea, the hoard design data ofthe Wiring board §s saved (Step 211), Accordingly, the hoard design data ofthe ‘Wiring board can be output inthe preserbed format he ine adjustment ofthe above Step 210 is performed by ‘the constraint processing prt 25 (See F1G. 2) while confirm: ‘ng constrains and the like ofthe wiring board. And, the fine ‘adjustment includes a processing so thatthe wiring route be ‘equalized as much as possible, For this, the fine adjustment can recalculate a route. After determining the wieing route ‘iighly by using fast response algorithms forthe elculation of the Wiring route, dedicated algorithms with high accuracy ‘an be used fr the detailed calewlation. {[Sereea Example] FIG. 16 isasctecn example showing a situation of design ing a wiring using the wiring board design vystem 1 of the present invention. Phesereen 160shownin FIG. 16shovs the situation receiving the wiring board design serviee after eon- ectng the wiring board design system Taf the present inven- ‘ion and isa sereen example cisplayed on a sereen ofthe user terminal 3. The screen 160 is an interface screen of a user receiving this witing board design serve. ‘The screen 160 comprises of a design area 161 for design ing a wiring board, an area 162 for displaying layers, status, storing destination, etc of the wiring board which is Jesign- ing, a menu area 163 for displaying a menu, tools, ete. Inthe area 162 can display necessary tools and the like for the ‘wiring bord design, These menu and tools ae using a gen- eral-purpose method to display them and the detailed expl ‘ation js omitted. Inthe example showing in FIG. 16, cireit board 164 is displayed in the design arca 161 and a plurality ‘ofeompomnents such as components 165,166, 167,169 onthe cirouit board 164 are arranged and displayed, ‘A terminal 168 ofthe component 167 anda terminal 1700f ‘the component 169 are connected by a wing 171, Here, the wiring 171 is overlapped as shown by an arrow 172. This \wirig 171 is showing a situation connecting these temninals ‘immediately after atranged the component 167 and the com poneat 169, As described below, this overlapped Wiring is eliminated by the wiring processing. FIG. 17A and FIG. 17B fare screen examples showing processes ofthe witing process ‘of the components and illustrating a part of the circuit board 164 showin FIG. 16, “Theaverlapped wiring 171 isillastated in thecircuit board 164 of FIG. 16 is calculated a Wiring route bY the wiring processing part 24 (Sce FG. 2) andthe overlapped wiring is eliminated. This situation is shown by a wiring 172 in FIG.US 9,026,982 B2 19 YA. After that, similarly, by the wising processing part 24 and the constraint processing part 28 (See FIG. 2), the fine adjustment of the wiring i performed and ifnecessary aroute ‘calculation ofthe rewiring is performed, In this fine adjust ment, the homogenization ofthe density of the wiring, the ‘optimization of the arrangement of the components and the like are performed. The situation after this optimization is ihstrated in FIG. 175 ‘A wiring 173 shown in FIG. 17% has the equal density in ‘comparison with the wiring 172 shown in FIG. 17. And, the ‘component 167 which is moved tothe upper right side ofthe space thas shows in FIG. 17A aad the wiring is rewired saccontingly, {About Security] The wiring board design system 1 of the frst embodiment ‘ofthe present invention provides a eloud environment using the server2 and the cloud database 5 connected othenetwork 4 In the cloud environment, the user terminal 3 receives the ‘wiring board design data fom te server 2 by using functions Tor connecting the network 4 Torthe business use, a security system is essential for users be fully satisfied. A security system based on a common Interface driver disclosed in Japanese Patent No. 5,055,492 Capanese Patent Application Lsid-open No, 2002-28878), US. Pat, No. 7,730,497, U.S. Pat. No. 7,395,581 and the amily patents canbe usd as thus security system, The eo mon interface driver is a program located between a fund- ment software and a device driver layer of an operating system and is operating in a kerel mode, “The common interlace diver is 9 technology 10 contol scading and receiving data between the fundamental software ‘and the device drivers and it realizes a high-level contol funetion. Especially, it is widely used fora prevention tech- nology’ ofelectonic information leaking from an electronic ‘compiler and can be applied to the circuit board design sys= ‘em 1 ofthe present invention. The common interlace driver technology can be applied to the user terminal 3 and can prevent a data leakage, “The common interface driver, a driverware and an infor: mation security system “4h Eye” (Registered Trade mark), NonCapy (registered Trade Mark), an theikefor preventing an information leakage using these technologies are systems provided by theScience Park Cosporaion (Head olive: Zama City, Kanagawa Perfeture, Japan). The present invention is not an iavention for such information security system and ‘more explanation is omitted. About these information secu Fily systems are deseribed in detail on the Homepage of Science Park Corporation and in abovesmentioned patent teratures te [Others ‘The present invention makes possible by a backbone that ‘comprises of high-spocd automatic wiring algorithm, data Structure and algorituns for pushing out the wiring with dhe ‘components automatically and high-speed. And, the “Auto- matic wiring” includes not only connecting signal terminals but also parallel shift of « component and wiring for the ‘density equalization. Namely, when some of components are arranged and a component is aranged additionally on the cireuit board which is wired simultaneously, the wiring $s pushed out automatically and the fine adjustment is per Jormed s0 a the components and wirings being equally. “The wiring processing part 24 calculates the ratio of all, ‘wirings on the eireuit board to the dimension ofthe circuit, board and the variation of the wiring ean be obtained. The wiring processing can be performed so as this variation is ‘minimized, in other words withthe equal wiring density, by the wiring processing part24 or the constraint processing part 0 o 20 26. In this time, processings of rotations of components or ‘movements of atranging postions of the components and processings of obtaining the variation of the wiring are per formed repestely ‘As mentioned above, since the component arrangement and the wiring performed simultancously the wieing com: pleted if the component arrangement completed. The ef tency made huge improvement tht the conventional meth- ‘ds tat perfoem wiring after the arrangement. Further, itean ‘exim arrangements aad wirings belore that time contin ‘ously in eourse of the calculation, iF necessary it ean be easy to revaleulate. Thus, the success rte of one shot completion ‘becomes considerably high. Inthe conventional wiring board design system, when to arrange components adlitonaly, if there is wiring inthe desired arranging positon, the compa ‘ent must be arranged after erasing the Wiring. ‘On the other hand, in the wiring hoard design systemof the present invention, when to arrange additionally anew com- poneat, an existing wiring (wired beforehand) is pushed aut fand a space for aranging a component is ereated, In the present embodiment ofthe wiring board design system, ba cally although the designer determines a position to arange ‘anew component, the difference ofthe density (unequal) may ‘occur in some areas in the wiring (existing and new. In this situation, the wiring processing part 24 (See FIG. 2) and the Tike make the wising as equal as possible by moving the arranged components automatically. Although, the present example isan example for designing 1 printed cireuit board (PCB), but also ean be applied for designing IS (LSD, IC package. And, in the wiring board {design system 1 ofthe present invention although the arrang- ing work of components is assumed to be manual tasks of signers, but automatic arranging algorithms can be emibed- sea. INDUSTRIAL APPLICABILITY ‘The present invention may be utilized in elds requiring ‘complex eicuitdesiun or wiring board design for a printed circuit board, LSI or the ike “The invention claimed is: 1. A wiring board design system for designing a wiring board by arminging a component on a circuit board, whereia suid system comprising: ‘an information obisining part for obtaining information ‘concerning a singe layer ora multiple layer said circuit board, said component having one or more connection ‘terminal, and a wiring connecting sad connection ter- minal of sad component from an input means or select ing or obtaining from a memory means: ‘component seraaging pat for arranging sad componcat input orselected by said information obtaining partinan appropriate position on suid cireuit board ‘wiring processing pan for determining a sring route to ‘aid component or herwcen suid components arranged by said component arranging part and ‘an output part for ourputing design data of said wiring board including said wiring route, ‘wherein to determine by calculating said wing route by said wiring processing part at everytime of said arrang- ing of suid component ora plurality of said components ‘arranged by sid component atranging part, and ‘wherein when o push out said wiring, said wiring processing part draws a figure of an ellipse ora quadrangle by the shape of sad component ata specific distance of at least or more distance that does not affect said component fom said Wiring: obtains across pointUS 9,026,982 B2 2 ofa tangent line and said figure, sid tangent Tine is drawn from a tenninal of ssid wiring to said igure: draws a fist new wiring from said ross point (0 said terminal; and draws a second new wiring between said ‘ross points if plurality of sid eross points; wherein Said first new wiring and said second new wiring ‘becomes together said pushing witing. 2. The wiring board design system acconding to claim 1 ‘wherein when to determine said wiring route by calculating aller said arranging of ssid componct, if ssid component ‘overlaps with said wising whieh is determined beforehand, ‘aid wiring processing part secures space for arranging std ‘component by pushing out said overlapped wiring 3. A wiring board design system for designing a wiring board by arranging a component on a cieuit board, wherein said system compris ‘an infomation obtaining part for obtaining information ‘concerning single layer or a multiple layer ssid circuit ‘boar, sid component having one or more connection {erminal, and @ Wiring connecting said connection ter- ‘minal of sid component from an input means or select- ing or obtaining from a memory means; ‘component arranging pat for arranging sid component input or selected by said information obtaining part inan propriate position on said circuit board; ‘asvinigg processing part for determining 8 wiring route to ‘aid component or between said components arranged by ssid component arranging part; and an output par for outputing design data of said wiring ‘board including said wiring rote, ‘wherein to determine by calculating sad wiring route by ‘sid Wiring processing part a every time of sid arang- ing of sid component ora plurality of said components arranged by ssid component arranging part, and wherein said wiring processing part caletlates the var tion of ratio ofall said wiring on sad circuit board an area of said circuit board, rotates said component or :moves said arranging position of sad component auto~ ‘matically so as to be the equal wiring density and sai Wiring processing is performed repeatedly. 4. The wiring board design system aeconding to claim 3, ‘wherein when to determine said wiring route by calculating aller said arranging of ssid componct, if ssid component ‘overlaps with said wising whieh is determined beforehand, ‘aid wiring processing part secures spoce foraranging si ‘component by pushing out said overlapped wiring $. A wiring board design method for designing a wiring board by arranging components on a etcuit board, wherein said method comprising the next steps of ‘obiaining, by Using a compute, from an input means oF ‘selecting or oblaining from a memory means informa tion eonceming to wiring for connecting sad a single layer ora multlayer circuit board, said component hav- ‘ng one or more connection terminal, and, suid connec tion terminal of said component arranging, by using 8 compte, said component, which is input or selected, in an appropriate position on said circuit board; setermining, by using a computer, a wiring route to said ‘component arranged or between said components by 2 ‘wiring processing pat; and ‘oupatting, by using acomputer, design data of said wiring ‘hoard ineliding sad wiring roe, ‘wherein when to push out said wiring, said wiring process ing part draws figure of an ellipse or a quadingle by the shape of ssid component ata specific distance of at Teas or more distance that does not affet said eompo= 0 o 2 ‘nen fom said Wiring; obtains across point ofa tange line apd said figure, said tangent line is drawn from a terminal of ssid wiring to said figure; draws fist nes ‘wiring from said eross point to sid terminal, and deaws a second new wiring between said cross points if a plurality of ssid eross points: whercin said fist now ‘wiring and said second new wiring becomes together said pushing wiring. 6. The wiring board design metho! seconting to elaim 8, ‘wherein whea to determine said wiring oute by ealeulating afer said aeranging of stid component, if said component ‘overlaps with said wiring Which is determined beforehand « space for arranging said component is secured by pushing out sid overlapped wiring by std wiring processing part. 7. A wiring board design method for designing « wiring board by arranging components on a circuit board, where suid method comprising the next steps of: ‘oblaining, by using a computer rom an inpt means or selecting or obtaining from @ memory means informa- lion conceming to Wiring for connecting suid a single layer ora multilayer circuit board, said component hav ing one or more connection terminal, and, said connec tion terminal of said component arranging, by using a compiter, said component, which is inpot or selected, in an appropriate position on said circuit boards, detemining, by using @ computer, a wiring route to said ‘component strange or between said components by 2 ‘wiring processing par; and ‘outputting, by using computer, design data of sad wiring board inchiding sid wiring mute, wherein said wiring processing part calculates the varia- tion of ato ofall said wiring on said circuit board to an area of said circuit board, rotates said component or ‘moves said arranging position of sad component auto- ‘matically so as to be the equal wiring deasity and said ‘wiring processing is performed repented, 8. The wiring board design method aevordng to elaim 7, ‘whercin when to determine said wiring oute by eleulating After said arranging of said component, if said component ‘overlaps with said wiring which is determined belorchand, space for arranging sad component is secured by pushing o ‘id overlapped wiring by said wiring processing part. 9. wiring board design system for designing a wising board by armnging a component on a circuit board, wherein said system comprising: ‘an information obtaining part for obtaining information ‘concerning a singe layer ora multiple layer said circuit board, said component having one or more connection terminal, and a wiring connecting sad connection tet~ ‘minal of aid componeat from an input means or select- ing or obtaining from a memory means: ‘component arranging part for arranging said component inp orselected by said information obtaining partinan appropriate position on suid eirenit board ‘wining processing pat for determining a sring route to ‘aid component or herWcen suid components arranged by sald component arranging part; and ‘an output part for ourputing design data of said wiring board including said wiring mute ‘wherein to determine by calculating said wing route by said wiring processing part at every ime of said atrang- ingof sid component ora plurality of said components ‘arranged by said component arranging pat, wherein said wiring board design system comprising: ‘user terminal for performing designing said wiring board by being operated by a user,US 9,026,982 B2 23 a server comprising of sad information obtaining part, said component arranging part, said wiring process- ing part and said output part; ad ‘communication nctwork for providing data commni= ‘alion between sid user terminal and said server and ‘wherein when to push out said wiring, said wiring processing part draws figure of an ellipse or 3 uakrangle by the shape of said component at a specific distance of atleast or more distance that doesnot affect ‘sid component from said wiring: obtains 4 cross point of a tangent line and said figure, seid tangent Tine is drawn from a temninal of said Wiring to said igure: draws a fist new wiring from sid cross point to said terminal; and draws a second new wiring between suid cross points ifs plrality of sid eross points: wherein ssid fist new wiring and said second new wiring becomes together sad pushing wiring. 10, The wiring boand design system according fo claim 9, wherein said wiring board design system compris base storing dats conceming constraints of sid circuit board said component an sad Wiring for use in designing of said ciruit board. 11. A wiring board design system for designing a wiring boar by arranging a component on a cireuit Board, wherein sai system comprising: ‘a information obtaining part for obtaining information ‘eancerning a single layer or a multiple layer sai circuit ‘hoard, sid component having one or more connection datas 3 ‘terminal, and a Wiring connecting said connection ter- 30 ‘minal of said component from an input means or select- ing or obtaining from a memory means; 2 4 component arranging pat for ranging said compones inpot orselected by said information obtaining partinan appropriate position on said eienit board: ‘wiring processing pert for determining a string mute to ‘sid component or hetwcen ssid componenis strange by said component arranging part; and ‘an output part for ourputing design data of said wiring ‘board including said wiring route, ‘wherein to determine by calculating said wiing route by said wiring processing part at everytime of said arrange ingof suid component ora plurality of sai components arranged by said component arranging pat, ‘wherein said wiring board design system comprising: ‘user terminal Tor performing designing Sid wiring hoard by being operated by a user, 4 server comprising of said information obtaining part, said component arranging part, said wiring process ag part ad said output part and ‘communication nctwork for providing data communi- ‘cation between said usee terial and said server, and ‘wherein said wiring processing part caleuates the vari tion of ratio ofall said wiring on sad eizcut board to an area of said circuit board, rotates said component or moves said arranging postion of said component sto ratically so as to be the equal wiring density and said ‘wiring processing is performed repeatedly. 12, The wiring board design system according to claim 11 ‘wherein Said wiring board design system comprising:a date base storing data concerning constraints of sid circuit board ssid component and ssid wiring for use in designing of said cirouit bord