a085 Mlcroprocessor Architecture

Architecture Microprocessors end Microcontrollers 2-4

RST 6.5 TRAP

d NTR. INTR RST 5.5 RST 7.5 SOD

lnternupt control Serial./Ocontrol;

nd hence
8-bit internal dala bus

an detect
signals
SSors are Temipofary Ihstriciói WReg ZReg
Accumülatör register
Elao realster register FBRég Reg
DReg EReg

handling tack pofater

TAithiate Ansticlion
decoder
Progtan
eninter
ontroller. and
ALUY maghlne Anctenmenter
emory or Decrenenter
address atch
+t5V
POWER
ing I/0 SUPPLYGND
Tning and.control
CLK BAddess
IN X, Address
buiffer bute
CONTROL STATLSDMA
GEN0

CLK OUT ALE S

HOLD RESET IN AD, -ADo
RD A15 -Ag
2CE READY WR So IO/M HLDA
RESET OUT
Address bus Data /Address
bus

Fig. 2.2.,1 Architecture of 8085

Temporary
1719 P2.2.1 Register Structure register
W
Reg Z Reg
register structure of
The Fig. 2.2.2 shows the
lag Beg
8085. (See Fig. 2.2.2 on next page)
register model is
The shaded portion of this
latch 8085. It includes
called programmer's model of DReg a Roo
E, H and L) one
Bix 8-bit registers - (B, C, D, 16-bit RegLReg
accumulator, one flag register and two StackPalnterSP
registers are
registers (SP and PC). Al these they are
accessible to programmer and hence
included in the programmer's model. Fig. 2.2.2 Register structure of
registers- Temporary, Wand Z 8085
The remaining
programmers; they are
are not accessible to the
operations.
used by microprocessor for internal, intermediate
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 Microprocess
Microprocessors and Microcontrollers 2-5
8085 MIlcroprocessor Architesture
CY-Car
Use of W and Z registers serves as

The CALL instruction is used to transfer program control to a subprogram or flag is set.
and loads the
subroutine. This instruction pushes the current PC contents onto the stack
stored in the W and Z
given address into the PC. The given address is temporarily control is
Thus the program
registers and placed on the bus for the fetch cycle.
instruction exchanges the
transferred to the address given in the instruction. XCHG
and Z registers are used
contents of H with D and L with E. At the time of exchange W c) Instruc
for temporary storage of data. opcode of
memory r
1, General purpose registers : The CPU
B, C, D, E, H and L are 8-bit general
purpose registers can be used as a separate 8-bit further se
and HL, HL pair also functions as a data
registers or as 16-bit register pairs BC, DE d) Progra
pointer or memory pointer. earlier, m
2. Special purpose registers : sequentia
stores the
tri-state eight bit register. It is extensively used in
a) Register A (Accumuiator) : It is a operations, as well as in, input/output (I/0)
the PC
arithmetic, logic, load and store logical operations is stored in processO
and
operations. Most of the times the result of arithmetic byte ins t
as accumulator.
the register A.. Hence it is also identified incremer
the
It is an 8-bit register, in which five of
b) Flag Register (Program status word) :
counter
flags : S (Sign flag), Z (Zero flag), AC
bits carry significant information in the form of instructic
flag), as shown in Fig. 2.2.3.
(Auxiliary Carry flag), P (Parity flag), and CY (Carry e) Stack
Dy D6 Ds D4 D P2 D1 D
tempora
S of the m
Fig. 2.2.3 Flag register
operations, if bit D, of the
S-Sign flag : After the execution of arithmetic or logical
2:2.2
the number will be viewed as
result is 1, the sign flag is set. In a given byte if D, is 1, The
as positive number.
negative number. If D, is 0, the number will be considered arithme
ALU is zero and flag
Z-Zero flag : The zero flag sets if the result of operation in subtrac
register content becomes and E
resets if 'result is non zero. The zero flag is also set if a certain
decisio
zero following an increment or decrement operation of that register.
i.e.,
AC-Auxiliary Carry flag: This flag is set if there is an overflow out of bit 3 2.2.3
BCD
carry from lower nibble to higher nibble (D bit to D, bit). This flag is used for
operations and it is not available for the programmer. The
P-Parity flag : Parity is defined by the number of ones present in the accumulator. timing
After an arithmetic or logical operation if the result has an even number of ones, Th
about
i.e. even parity, the flag is set. If the parity is odd, flag is reset. IO/M

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 Microprocessors and Microcontrollers 2-6. 8085 MicroprocessOr Arohitecture
Architecture
CYCarry flag :This flag is set if there is an overflow out of bit 7. The carry flag also
covos as a borrow flag for subtraction. In both the examples shown below, the carry
Pgram or flag is set.
loads the ADDITION SUBTRACTION
Vand Z 1001 1011 89 H 1000 1001
98 H
ontrol is + 75 H + 0111 0101 AB H 1010 1011
ges the Carry 110H |1 0001 0000 Borrow 1 DE H 11101 1110
re used
c) Instruction Register : n a typical processor operation, the processor first fetches the
on the address bus and
opcode of instruction from memory (i.e. it places an addressaddress on the data bus).
memory responds by placing the data stored at the specified
is
te 8-bit The CPUstores this opcode in a register called the instruction register. This opcode
alternatives.
a data further sent to the instruction decoder to select one of the 256
As mentioned
d) Program Counter (PC) : Program is a sequence of instructions. executes them
earlier, microprocessor fetches these instructions from the memory and
a given time,
sequentially. The program counter is a special purpose register which, ofat 8085
Since address is 16-bit,
ed in stores the address of the next instruction to be fetched.
instruction. How
(/O) the PC is 16-bit. Program Counter acts as a pointer. to the nextinstruction; for one
of the
ed in processor increments program counter depends on the nature
for two byte instruction it
byte instruction it increments programn counter by one, increments program
increments program counter by two and for three byte instruction it
the the address of the next
AC counter by three such that program counter always points to
instruction.
memory in the RAM where
e) Stack Pointer (SP) : The stack is a reserved area of the address
used to hold the
temporary information may be stored. A 16-bit stack pointer is
of the most recent stack entry.

he 2:2.2 Arithmetic Logic Unit (ALU)

as eight bit variables. The
The 8085's ALU performs arithmetic and logical functions on addition and
arithmetic unit performs bitwise fundamental arithmetic operations such as
8 as complement, AND, OR
subtraction. The logic urit performs logical operations such looks after the branching
es and EX-OR, as well as rotate and clear. The ALU also
decisions.

2.2.3 Instruction Decoder and Machine Cycle Encoder

information to the
The instruction decoder decodes the opcode and accordingly gives
timing and control circuit.
the information
The 8085 executes seven different types of machine cycies. It gives
on the Sp, S and
about which machine cycle is currenty executing in the encoded form
IO/M lines. This task is done by machine cycle encoder.
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 MicroprocOSSOrs nd Microcontrollers 1 10 Microprocessor Based Systermns
Based Systerms

he instruction
oder decodes Registers
it.
Tempa
sor performs réglster-s,
Ternp Parallel
regiater Accumulator
lusive - OR. 6pors
General
purpose
4 gives data registers
rd is sent to Stack
ALU; pointer Serial
e result is
Program
Counter
of certain
ations are StatuS hstructöp
tegister register
eferred to
iterupt
rts of the RAM
address Rrogram
different addres
egistr
struction egister
struction and,
contro cOunter

with a RAM EPROMI

address ROM

Internal memory
Fig. 1.4.1 Block diagram of
ReviewQuestion microcontroller
1. Draw and explain the block
diagram ofa microcontroller.
cient. 1,5. Comparison between Microprocessor and Microcontroller
OM), GTU Winter-15,19
orts
Sr. NoR
Microproressof Microontroller
ler

lso d4Miregister
roprocesso
clockand
kand
COntains ALUUcontol únirMictoconrolletcont
ContainsueroprocesS
he
nd
and timingcircait)differentmenory
interrúpt (ROM arnd
circuit.,rcuit and peripheralRAM),deyices
I/O nterfactng
such as
28 AD cOnvee serjal Gtimer etc
tö movex dataIthas one
hetwpermémov ándCPUg or two
gata between mentoty nstritctons
attlcpU
tomove

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Mlcroprocossors and Mlorocontrollera 2-9 8086 Mloroprocos4or Archltocturo

2.3 8085 Pin Functions

GTU :Summer-03,04,O5,06,08,13,14,16,17,18,19, Winter,1316.18,19
Fig. 2.3.1 (a) and (b) shows 8085 pin configuration and functional pin diagrarn of 8085
respectively. The signals of 8085 can be classified into seven groups according to their
functions.
X.

X
4oVcc
39HOLD
Sariall sID
ports
RESET OUTI sDNetHLDA signas
initiated
Extemally
SOD
SID 5kd
37CLK(OUT)
36 RESET IN
TRAP
RST 7.5
TRAPC6U38READY RST 6.6
RST 5.5
RST 7.5 C 7 3 a O o M INTR Ko Kadarosaa
RST 6.5 C8ax33s,
READY
RST 5.59 32 RD HOLD
INTR 1
808BA
WR RESETIN
acknowiedgment
slgnal
External -ALE
INTA C17k2130ALE -So Control
AD, 2 29 S INTA and
HLDA 10/M status
AD, JA1s -RD signals
AD, WR
signals
Clock
AD,C152g A3 ReseloutJ
AD,16 O25DA12 Power
Vcc(+ 5v) supply
ADs ,24A11 CLKOUT GND
ADA18 23A40
AD,9. 220Ag
Vss 20. 21A

Fig. 2.3.1 (a) Pin configuration Fig. 2.3.1 (b) Functional pin diagram
b) Data bus and address bus
a) Power supply and frequency signals.
c) Control bus d) Interrupt signals
e) Serial I/0 signals ) DMA signals
g) Reset signals

2.3:1: Power Supply and Frequency Signals

i) Vcc i It requires a single +5 V power supply.
Ii) Vss Ground reference.
is connected at these
iil) X4 and X2 (Input) : A +tuned circuit like LC, RCoT crystal therefore, to
two pins. The internal clock generator divides Oscillator frequency by a2,frequency of
have
operate a system at 3 MFz, the crystal of tuned circuit must
6 MHz.
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 MicroproO00sSors and Mlcrocontrollers 2- 10 B086 MioroprooesAOr Arohteoture
dde
cturo signal is uSed as a systerm clock for ofhar
v) CLK OUT (Output) : This frequency,
the oscillator
frequency is half
Address Bus
2.3.2 Data Bus and
D85 bus (Do - D,) is multiplexed with she
A) AD, to AD, (Tnput/Output) : The 8-bit dataDuring
bus. first part of the machine
eir Jowwer half (An - Ay) of the 16-bit addres8
(T.) lower 8bits of memory address or 170 address appear on the bus, Diin
lines are used as a bi-direciona
rermaining part of the machine cycle (12 and T3) these
data bus.
l6-b1t address apPpears on the address linea
B) A to As.(Output) The upper halfof the 1B.his
A16. These lines are exclusively used tor the most significant 8 bits of the
As to
address lines.

Signals
2.3.3 Control and Status
: We know that AD, to AD, lines are
A) ALE (Address Latch Enable) (Output) during T, of the
of address (Ao Az) is available only
multiplexed and the lower half
necessary during T, and T, of machine
machine cycle. This lower half of address is also lower half
memory or I/0 port. This means that the
cycle to access specific location in available
address must be latched in T; of the machine cycle, So that it is
of an done by
of lower half of an address bus is
throughout the machine cycle. The latching
ALE signal from 8085.
using external latch and
and WR (Output) : A low on RD indicates that the data must be read from
B) RD indicates that the
selected menmory location or I/0port via data bus. A low on WR
the
memory location or I/0 port via data bus,
data must be written into the selected
indicates whether I/0 operation or memory
C) 1O /M S, and S, (Output) : I0/M
carried out. &; and Sp indicate the type of machine cycle in progress.
operation is being
microprocessor to sense whether a peripheral is
D) READY (Input):It is used by the processor waits. It is thus used to synchronize
the
ready or not for data transfer. If not,
slower peripherals to the microprocessor.
2.3.4 Interrupt Signals
5.5,
five hardware interrupt signals : RST
Hardware Interrupts (Input) : The 8085 has
RST 7.5, TRAP and INTR. The microprocessor recognizes interrupt requests on
RST 6.5,
instruction execution.
these lines at the end of the current
: The INTA (Interrupt Acknowledge).signal is used to indicate that
INTA (0utput)
interrupt.
the processor has acknowledged an INTR

knowladge
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2.3.5 Serial /O Signals

A) SID (Serial IIP Data) (Input) : This input
by bit from the external device. signal is used to accept serial data bit
B) SOD (Serial OP Data) (Output) :
This is
transmission of serial data bit by bit to the external an output signal which enables the
device.
2.3.6 DMA SIgnal
A) HOLD(Input) : This
of address bus, data bus andsignal indicates that arnother master is requesting for the use
control bus.
B) HLDA (Output) : This active high
signal is used to acknowledge HOLD request.
2.3.7 Reset Signals
A) RESET IN (Input) : A low on
this pin
1) Sets the program counter to zero
(O000H) and clears the INTE flag.
2) Resets the interrupt enable and
HLDA flip-flops.
3) Tri-states the data bus, address bus and control
(Note : Only during RESET is active). bus.
4) Affects the contents of
B) RESET OUT (Output) : This processor's internal registers randomly.
active high signal indicates that
reset. This signal is synchronized to the processor is
devices connected in the system. processor clock and it can be used to reset being
other
Review.Questions
1. Write about the pin
configuration of 8085 processor and explain them in detail.
2. Explain the signals used in DMA
operation in 8085.
3. Draw the pin diagram of 8085
4. Draw the pin dingram of 8085 microprocessor.
5. Explain the functions of the
microprocessor and list the qlassification of signals.
following pins : i) ALE ii) READY ii) WR iv) HOLD and HLDA
6. Explain the functiong of the
7. Discuss the function of
following pins of 8085 :) 10/M ii) So and S;
following pins : i) READY ii) RESET iii) HOLD io)
8. Draw and explain the pinout INTR
diagram of the 8085 microprocessor.
9. Explain the need of X, and X, pins of the 8085 :GTU:Summer-06, Marks8/IT
microprocessor ?
10. Why does ALE gohigh in start of
every Machine cycle ?
GTU::Summer-03/ Marks 2,CE
11, What is tmportance of .GTU; Summer-04,Märks 2; CE
READY signal?
12. Explain the functions of SID and
SOD pins. GTUSümmer-04,. Marks:2, CE:
GTU: Summer-04, Marks 4, CE
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 Introduction to Instructions
and Assambly Language Programs
Microprocessors endMicrocorntrolers 4-32

instructions.
mnchine control
13. Giue exenples for instructions, arithmetic instructions, logic instructions and
14. Give luo exanples for data transfer
branch instructions. microprocessoT.
suitable examples the data transfer instructions in 8085
15. Describe toith explaining about the various types of
operations.
the 8085 instruction st,
16. Disc1uss in detail about
4.3 Addressing Modes
.and
programming flexibility for each microprocessor is the number
Part .of .the memory. The
different kind of ways the programner can refer to data stored 'in the
addressing
access -data are referred to as
ditterent way3 that a microprocessor can
modes. The 8085 has 5 addressing modes. These are :
1. Immediate 2. Register
3. Direct 4. Indirect
5. Inplied
1. 1mmediate addressing mode :
in an immediate addressing mode, 8 or 16 bit data can be specified as a part of
instruction. In 8085, the instructions having T letter fall under this category. T indicates
immediate addressing mode.
Example
MVI A, 20H Moves 8 bit immediate data (20H) into accumulator
MVI M, 30H ;Moves 8 bit immediate data (30H) into the
;memory location pointed by HL register pair.
LXI SP, 2700H ; Moves 16 bit immediate data (2700H) into SP.
LXI D, 10FFH ;Moves 16 bit immediate data (10FFH) into DE
-;register pair (D= 10H and E = FFH).
2. Register addressing mode:
The register addressing mode specifies the source operand, destination operand, or
both to be contained in an 8085 registers. This results in faster execution, since it is not
necessary to access memory locations for operands.
Example :
MOV A, B :Moves the contents of register Binto the accumnulator.
SPHL ;Moves the contents of HL registerpair into stack pointer.
ADD C ;Adds the contents of register C into the contents of accumulator
;and stores result in the accumulator.

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 Infroduelilon to instrictions
Microprocessors and Microcontrollers 4-23 and Assembiy Language Programs Microprocessors and Microcon
3. Direct addressing mode:
By incrementing or d
The direct addressing mode specifies the 16 bit address of the operand writhin the
we can change the inde
instruction itself. The second and third bytes of instruction contain this 16 bit address.
Review Questions
Example:
LDA 2000H ; Loads the 8bit contents of memory location 1. With example expl
2000H into the accumulator. 2. What are the differ
SHLD 3000H Stores the HL register pair into two consecutive memory
locations. Lower byte i.e. the contents of L register into menorY 4.4 Assembiy La
: location 3000H and higher byte i.e. the contents of H register
into memory location 3001H. Let us define a p
4. indirect addressing mode : language prograrm to
involved in this prog
In indirect addressing mode, the memory address where the operand located is " Load wo ex
specified by the contents of a register pair.
Add numbers
Example: Store he resu
LDAX B :Loads the accumulator with the contents of These tasks carn
; memory location pointed by BC register pair. shown in the Fig. 4.
MOV M, A ;Stores the contents of accumulator into the
Next job is to
memory location pointed by HL register pair. instruction/s for ea
5. Implied Addressing Mode :
In implied addressing mode, opcode specifies the address of the operands.
Task 1instruction
Example :
MVI A, 20H
CMA : Complements contents of accumulato. MVI B, 40H
RAL ; Rotatesthe contents of accumulator left through carry.
Note : Task 2 instructio
Many of the advanced processors support addressing mode called index
addressing mode. In this mode, the address of the operand within the memory is ADD B
generated by adding the offset/displacement to the register specified in the instruction. Task 3 instructio
The offset/displacement is also a part of the instruction. In 8085 such addressing mode
is not available. However, we can implement such kind of STA 2200H ; Store
program structure, by using HLT ;Stop
memory pointer (HL register), any other register pair and a instruction sequence given
below : We want to e
LXI H, Baseadd in the same seqt
;Loads the base address
LXI B, Offset/Displacement ;Loads the offset or displacement
DAD B ;Gives the addition of HL and BC in HL
4:4:1 Assem
MOV A, M
register pair.
;Load the data from memory in the Once the ass
accumulator
machine langua
each asseml:iy
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 MicroprocOssors and Microcontrollors 5-20

waveforms the fetch and execute cycle with reference f

6. What is instruction cycle ? Explain us/ng Marks 7
GTU; Winter 12,
clock.
instruction qycle. GTU:Snmer 14, Marks 3.
7. Explain T-State, machine cvcle and
8. Draw and explain the memory read cycle of 8085. GTU: July 04,06, Marks 4
9. Drav and explain the memony urlte cycle of 8O85.
cycles of 8085.
10. Dra and explatn the O end ond orite
ench of the follonoing cycles 1
11. Indicnte the souree and destination of dntn for
) Memory orite ii) Memory rend it)
1/O write in) /O read.
the
1OM, S, and Sn slgnals of 8085. List out the information provtded by
12. Explain the purpose of
varims combinations of these signals tn a table. the timing
machine cycle and instruction cycle n 8085 nicroprocess0r. Draw
13. Define T-state, GTæ:Sunner-17, Marks 7
diaçam for the instructions OUT GA
GTU: Winter-15, 18, Sumner-18
5.2 Timing Diagram for MOV Instruction

5.2.1 Timing Diagram for MOV r, r Instruction

diagram for the MOV r, r ínstructions. These instructions
Fig. 5.2.1 gives the timing Program counter gives address on
low-order
opcode fetch machine cycle.
require only OPCODEFETCH
T2 T3

CLK

PCH PC=PC+
BgArdeVUnspe
A1s-Ag VMemony Addre

PC,
AD, -ADo

ALE

IO/ MSo -S4

RD

r Instruction
Fig. 5.2,1 Timing dlagram for MOV r,
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 A o e o r enc ARAOrOntler aO85 Timing Diagrams
6- 21 BOBS Timing Disgrans Mlctoproce tsors onc Microcontrotarn 5-22

and high-onder nddress bus The opcode of the VEMOp WRITE

instruction is read into the OcODE FETCH
minoprocessor from the nddresned nemory location and is decoded.
5.2.2 Timing Diagram for MOV r, M Instruction
Pig. 52.2 shows the timíng diagram of MOVr, M
the contents from mnemory location pointed by HL
instruction. This instruction copies MOVNA
specihed withir the
register pair into the register Addtass ATCrActass

instruction. This OPCODE CETCH MEMORY READ MOV

ínstruction requires two AD, - AD,
machine cycles. CLK Table 5.2.3
1. Opcode fetch : ALE

Program counter places PCHi PC PC" 1; Hrea.

MOVAAL M
address on low-order A.. -A YighrdotVunnp
: VHigh-ord0t Io/M So- S
MemoryASdross eGoMemary Addre CMOV BM
and high-order address MOV
PC Lrea. (Mem. MOV DM,
bus. The opcode at thís AD,-ADo Pota
MOVEM
MOV H./M
memory location (e.g. FMOV M WR
TEH of MOV A, M) ALE
Table 5,2.2
Fig. 5.2.3 Timing diagram for MOV M, r Instruction
read into the
microprOCeSsor and is 10 / So S, Review:Questions
decoded. 4 T-states are
required for this 1. Draw anã explain the timing diagram for MOV r, r instructior.
machine cycie. Program 2. Draw and explain the timing dagram for MOV r, M instruction.
counter is incremented Fig. 5.2.2 3. DraU anc explain the timing diagramn for MOV M, r instruction.
by one. 4. Explain tue execution of MOV C, M instruction using timing diagram.
2. Memory read : HL register pair gives address on low-order and high-order GTUWinter: 15, Marks 7
address bus, The data at this addressed memory location is read into the specified 5. Drauw and explain the timing diagram of instruction MOVC, A in 8085.
GTUSummes18, Marlks 7
register of the microprocessor. Program counter is incremented by one.
GTUWinter-18, Marks 4
6. Prepare a timing diagram for instruction MOV A.B.
5.2.3 Timing Diagram for MOV M, r Instruction
5.3 Timing Diagram for MVI Instruction
GTU:Summer-19
Fig. 5.2.3 shows the timing diagram of MOV M, r instruction. This instruction copies
the contents fromn the specified register into the memory location pointed by HL register Fig. 5.3.1 shows the timing diagram of MVI I, data.
pair. This instruction requires two machine cycles. These instructions directly load a speciied register with a data byte specifed
within
high-order
1. Opcode fetch : Program counter places address on low-order and the instruction. They require the following machine cycles.
address bus. The opcode at this memory location (e.g. 77H of MOV M, A) is read into on low-order and
machine cycle. 1. Opcode fetch : Program counter gives the memory address
the microprocessor and is decoded. 4 T-states are required for this high-order address bus. This machine cycle is required for reading the opcode into the
Program counter is incremented by orne.
microprocessor and decode i:. Program counter is incremented by one.
frorn the
2. Memnory write : This machine cycle is required for writing the data
specified register into the memory location specified by the HI. register pair.
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 Microprocessors and Mlcrocontrollers 5-23 8085 Timing Diagrams Microprocessors and

2. Memory read :This machine cycle reads the data from addressed memory location Review Question
into specified register of the microprocessor.
1, Draw and e
OPCODE FETCH MEMORY READ
T4 T2 T 5.4 Timing
This instructio
CLK address is given
PC =PC:1 POA PC* PC + 1
1. Opcode fe
address bus.The
A15-Ag ghordar
Memory Address eciaMecnoty Accress the microproces
PCL PCL
Program counter
AD,- ADo Eow-order:
Nemory Opcode Low-Qrdafke: MVIAdala 3E 2. Memory
AddreS5 Data MVIBdata.06 high order add
MMCdata' oEr
MVID, data 16*
MVILE dala 1E
addressed outp
ALE MVIH; data 26
MVI Ly.dala 2E

Table 5.3.1
10/M S, - So joM=0,S=1, S,3jOIM=0,s-0,
SX A

RD
AD

Fig. 5.3.1

ins Fig. 5.3.1 shows the timings required for different signals. Table 5.3.1 gives the
instructions for which the timing diagrams are same. Only difference is in opcode.
AC
dat ACI, data.. ADI, data.. ANI, data.. CPI, data.. ORI, data.. SBI, data.. SUI, data., XRI,
data..
con These instructions perform logical operation specified in the instruction with the
contents of accumulator and the data within the instruction. They require the following
machine cycles.
1. Opcode fetch : Program counter gives the memory address on low-order and
high-order address bus. This machine cycle is required for reading the opcode into
2 Review Q
the microprocessor and decode it. Program counter is incremented by one.
2. Memory read : This machine cycle reads the data from addressed memory location 1. Dre
and after performing specified logical operation result is stored in the accumulator.

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 MioroprooesSOrs And Microcontrollers 6-6 8051 Microcontroller Architecture

Register B 16-bit DPTR

In addition to accumulator, an 8-bit
B-register is available as a general purpose OPH DPL Memory
register. It is used for the hardware
3)
(32+) 16 Address
multiply/divide operation. 8-bit 8-bit

6.2:3 Data Pointer (DPTR)

The data pointer (DPTR) consists of a high byte (DPH) and a
function is to hold a l6-bit address. It may be manipulated as a 16-bitlow byte (DPL). Its
two independent 8-bit registers. It serves as a base data register or as
register in indirect jumps, lookup
table instructions and external data transfer. The DPTR does
not have a single interrmal
address; DPH (83H) and DPL (82H) have separate internal addresses.
6.2.4 The Program Counter
The 8051 has a 16-bit program counter.. It is used to
location from which the next instruction is to be fetched.
hold the address of memory

6.2.5 8051 Flag Bits and the PSW Register

The Fig. 6.2.2 shows the bit pattern of Program Status
also known as flag register. Word (PSW) of 8051. PSW is
B B Bs BA B, B, B Bo
CY AC FO RS1 RSO OV P

Flg. 6.2.2
The 8051 consists of following flags.
CY-Carry Flag : This flag is set if there is an overflow out of bit 7. The
also serves as a borrow flag for carry flag
subtraction. In both the examples shown below,
the carry flag is set.
AC-Auxiliary Carry Flag : This flag is set if there is an overflow out of bit 3 i.e.,
carry from lower nibble to higher nibble (D, bit to D, bit).
ADDITION
SUBTRACTION
9B H 1001 1011
+ 75 H 89 H 1000 1001
+ 0111 0101 AB H
Carry 110 H 10001 0000 1010 1011
Borrow 1 DE H n1101 1110
" FO -
Available for user for general purpose.

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 MI Microprocessors and Microcontrollers 6-7 8051 Microcontroller Archltecture

Even though there are 128 memory locations intended to be occupied by them, the
ba
basic core, shared by all types of 8051 microcontrollers, has only 21 such registers. Rest
of of locations are intentionally left unoccupied in order to enable the
fu manufacturers to
further develop microcontrollers keeping them compatible with the previous versions.
Fig. 6.2.3 shows special function bit addresses.
Direct Hardware
Bit address
byte registar
address
(MSB) (LSB) symbol
OFFH

OFOH
7 0 F5 F4F3F2 EFO B

OEOH ACC

ODOH DZSDO PSW

OB8H IP

OBOH B7B6: B5| B4 B3B2 B1 B0 P3

OA8H AC AB AA Ae A8 IE

OAOH AZAB A5 A4 AO P2

SCON

90H P1

88H 8 8EB0 BC8B8A| 89 88 TCON

80H 87-8685 84B38281 80 PO

Fig. 6.2.3 SFR bit address

Table 6.2.1 contains a list of all the SFRs and their addresses and their value in binary
at reset.

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 Microproc9sSOrsand Mlcrooontrollers 6- 10 8051 Microcontroller Architecture

Voc + 5V
PO.O (A DSN
ROAD
POR tAD)
Port 1
Port 0
PO4 ADA
RO5AD
RST
P3.C(RXDi EA (Vpp)
ALE (PROG)
R3.2 NTO
PSEN
Port 3 28

P25 (A13)
M6
Port 2

Oscillator
signals
9
GND

Fig. 6.3.1
Pin-out of 8051
The 8051 has 32
I/O
aio 3). AlI four ports arepins configured as four eight-bit parallel ports (P0, P1, P2
output (or both). All bidirectional ie. each pin willI be configured as nput
port-pins are
consists of a latch, an output multiplexedexcept the pins of port 1. Each port
Port 0 driver and an input
(Pins 3239) : Port 0
input buffers
buffer.
byte of-the of port Oare used topins can be used as I/O pins. The output drives and
external0 can memory access external memory. Port 0outputs the low order
read. Thus, port
Port (Pins 1 -8) :
1 address,time
be used as a mltiplexed with the data being written or
multiplexed address//data
data bus.
Port 2(Pins 21 Port 11 pins can be
ontroller Architecture Mieroprocessors nnd Mieroeortroters 4051 Microeontroller Architecture

Summer-16, 18 Byte
addres8
ss up to 64 K ayte
addrass
aternal program 1E
1D

Bank 3
1B

19
18

17 B
16 R
16
14
Bank 2
13
12 R
11
10 B, B B, 8, B B, 8,
OF
0E
0D 68
0C
Bank 1
0B
OA

08
07
06 37G534s33
05

Bank 0
04
272625
03
02 R
01
00

er, The Register Bit addresses Byte General purpose

bank addresses
ntermal
Fig. 6.7.2 Organlzation of internal RAM of 8051
6.7 6.7,1.1 8051 Reglster Banks (Working Reglsters)
T The first 32-bytes from address 00H to 1FH of intenal RAM
onstitute 32 working
regis registers. They are organized into four banks of eight egisters each The four register
bank banks are numbered 0 to 3 and are consists of eight registers
named Ro to Ry.
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 icroprocessors and MicOcontrollers 10- 10 B081 Serlal Port ond Programming

5. Explan full duplex, half duplex and smplex serial data transfer.
6. WAat is asynchronous serial communication ?
7. Explain the format of asynchronous serial communication.
8. Exzriain the function of RS232C pins of DB-9 connector.

10.3 8051 Serial Communication GTUSummer-16/17M8719Winter-17

The serial port of 8051 is full duplex, means it can transmit and receive
Simultaneously. It uses register SBUF to hold data. Register SCON controls data
communication, register-PCON controls data rates and pin RxD (P3.0) and TxD (P3.1) do
e data transfr.
SBUF is an 8-bit register dedicated for serial communication in 8051. Its address is
9H. I can be addressed like any other register in 8051. Writing to SBUF loads data to
te transmitted and reading SBUF accesses received data. There are two separate and
distinct registers, the transmit write-only register and the receive read-only register. This
illustrated in Fig. 10.3.1.
RxD
(P3.0) SBUE
Shitregistor CEK Weite onlý TxD
(P3.1)

Baud rate clock

Baud rate clock (Transmit)
(Receive) SBUE
REaconly)

8051 internal bus

Fig. 10.3.1
The way in which SBUF is used for the transmission and reception of the data during
erial communication is explained below.
Transmission : When a byte of data is to be transmitted via the TxD pin, the
SBUF is loaded with this data byte. As soon as a data byte is written into SBUF, it
is framed with the start and stop bits and transmitted serially via the TxD pin.
Reception : When 8051 receives data serially via RxD pin of it, the 8051 deframes
it. The start and stop bits are separated out from a byte of data. This byte is
placed in SBUF register.
t pattern of $CON register
The 8051 provides four programmable modes for serial data comnunication. A
articular mode can be selected by setting the SM0 and SM1 bits in SCON. The mode
lection also decides the baud rate. The Fig. 10.3.2 shows the bit patterns for SCON.

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 (MSB) (LSB)
7 3

SMO SM1 SM2 REN TB8 RB8 TI PI

Symbo Position NAme and signiicance

SMO SCONZ Seral por MOJEContp bir9kNAP

SMSSCON6Serlapàrt Mbde?cortoebia

SM2
artwarototspentotoraneftK
saON4
orenblectBaeserialtdaa

RRR CON2Recee Bit8

etcleaYed:bad

SCONT RrarSiitnergyprag
SetbyhEateeA

SCON0REeronfarrubis

Barcway
Noleae ofSMOsM1 28eectswP

Fig. 10.3.2 SCON-serlal port control/status raglster

pattern of PCON register.
(MSB) (LSB)
7 6 5 4 3

SMOD GF1 GrO PD IDL

wwwwe

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 ticroorocasso eng MicTOCnntroliert 13-3
ApDlicetions end Design of Microcontroller Bosed Mcroprocessors and Microcontrallers 13-4
Systers ApgicatHons and Dosign of Werocontrolar Sased
while (1) Setsms
I* tap9at continuously /
/ Maka P2.0 ágh /
delay ( ) / wait for some timo /
P2^0 * Make P20 Low /
EO delay ( ) wait for sometime /
npn
transistor prp
805 transistor void delay ()
B051
unsigned int a,b;
for (a = 0; a < 100; a
++)
(a) LED for (b 0; b < 500: b ++);
intertace in current source mode (b) LED interface in current sink mode
Fig. 13.1.2
Example 13.1.1 Writëar ALP to flash the LED Example 13.1.3Corsider hatswith As cortected üifh
COnneted to port P2.0. RsQthatphenifispeSsed logisg s2Sa0a porprn P32
Por POusing comUgn ancde coufguraton Draw
Soiution: Algorithm 1 Algorithm 2 thtesfacitg creutgA
Step 1: Make P2.0 High
Step 2 : Wait for some tine Step 1 : Complerment P2.0
Step 3: Make P2.0 LOW Step 2 : Wait for sorme time en2dsuitdacast
Step 4 : Wait for some time Step 3 : Repeat steps 1 and 2 Solution : GTU : Winter-13, Maks
Step 5: Repeat steps 1 through step 4
Program 1:
ORG C000H
BACK: SETB P2.0
Make P2.0 high
ACALL Delay Wait for SOme time
CLR P2.0
Make P2.0 low
ACALL Delay Wait for some time
SJMP BACK repeat SW
Program 2:
ORG 000OH
BACK : CPL P2.0
CALL Delay Complement P2.0
Watt for some time Flg. 13.1.3
SJP BCK #include <reg 51.h>
sbit SW = P3^2;
Example 13.1.2 rite anB051CoRLam to fl4sh the L¸D, mnecte topart P2.0. vold main (void)
Solution :
# include <reg 51.h> SW = 1;
void delay (void): || Conñgwa P3.2 as an input
void ain () while (1)

if (sW==0)
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 Microprocosaora ond Mlcrocontrollers 13-0 Appllcatlons ond Dotlgn of Mlerocontroler Basod Systams

NEXT2: JNC NEXT3 If tomp>81 goto NEXT3

SKIP : SETB P0.0 Here temporature in betwegn 109 and 80
ÇLR PO,1 So RED s OFF and GREEN is ON.
SJMP BACK
NEXT3 : CLR PO.0 Here temperature > 81 s0 make
SETB P0.1 RED ON and GREEN OFF
SJMP BACK Repeat
END

Review Questions
1. What is sourcing and sinking currents ?
2. With adiagram explain how LED can be tnterfaced to 8051.
13.2 Interfacing Multiplexed 7-Segment Display
GTU Winter.07,13,15,19, Summer-16,17,18
Seven-segment display : Seven-segment displays are generally used as mumerical
indicators. and consists of a number of LEDs
arranged in seven-segments as shown in the
Fig. 13.2.1.
Any number between 0 and 9 can be indicated Dh
by lighting the appropriate segments. Fig. 13.2.1 Seven-segment display
The seven-segments are labelled to g and dot is
labelled as h. By forward biasing different LED segments, we can display the digits 0
through 9. For instance, to display 0, we need to light up a, b, c, d, e, and . To light up
5, we need segiments a, f, g, Cand d.

e
Dh Oh

(0) (1) (2) (3) (4)

Dh Oh
d d

(5) (6) (7) (8) (9)

Fig. 13.2.2
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 Based Systamg
MicroprooBs3Ors end Microcontrollers 13-7 Applications end Design of Microcontroler

These 7-segment displays are of two types:

Common anode type
" Common cathode type
connected together as shown in
in common anode, all anodes of LEDs are
connected together, as shown in
Fig. 13.2.3 (a) and in common cathode, all cathodes are
Fig. 13.2.3 (b).
Vec o

C E G
A

(a) Common anode type

D E
mo

(b) Common cathode type

Fig. 13.2.3 Internal dlagram of 7-segment LED

13.2.1 Interfacing LED Displays
Static display
a +5V
Fig. 13.2.4 shows a circuit to drive
9+5 V
R
anode
single, seven-segment, common
LED aisplay. For common anode, when w

anode is connected to positive supply, a BCD

low voltage is applied to a cathode to inputs C4
turn it on. Here, BCD to seven-segment
decoder, IC 7447 is used to apply low GND 9
voltages at cathodes according to BCD
input applied to IC 7447. To limit the
current through LED segments resistors Fig. 13.2.4 Clrcuit for driving single
Connected in series with the seven-segment LED display
are
segments. This circuit connection is
being passed through the display at all
referred to as a static display because current is
times.
of the resistor in series with the segment can be calculated as follows:
The value
=0
We know, Ver - drop across LED segment - IR

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Microprocessors and Microcontrollers 13- 10 Applications and Dosign of Microcontroller Based Systems Microp

Subr

AGA

Fig. 13.2,6

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 description tor LOD module
The Fig. 13.3.1 shows the interfacing of a 20 character x 2 line LCD
module with the
8051. As shown in the Fig. 13.3.1, the data lines are connected to the
port 1
control lines RS, R/W and E are driven by 3.2, 3.3 and 3.1 lines of port 3, of 8051 and
The voltage at VE pin is adjusted by a potentiometer to adjust the contrast ofrespectively.
the LCD.
P1.0 DB Voc
P1.1 DB,
P1.2 20 character 2Tine
DB2
P1.3
P1.4
DB3 VEE
P1.5
DBA display.
DBE module.
P1.6
P1.7 DB |Vss
8051 DB7
RS RW
P3.2

P3.3

P3.4

Fig. 13.3.1 Interfacing LCD module with 8051

The display can be controlled by issuing
Table 13.3.2 lists the command available for proper commands to the LCD module. The
LCD module.
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key isa! impo
13.4.1.It is between A
Table key is in
change,
that, when does not
output output. +5 V
and B, bouncing of key that Fig. 13.4.2
preventing we can say
words during
In otherdoes not
output not change debouncing.
does
eiminating key
traneiton period,
using Software
13.4.2 Key Debouncing press is found, the
eoftware technique, when a key
ms before it accepts the key as an
In the
/microcontroller waits foT at least 10
microprocessor/ state. Fig. 13.4.3 shows the
settle key at steady
period is sufficient to
input Thts 10 ms debounce technique.
Aowchart with key
Interface
13.4.3 Simple Keyboard
interface.
Fig 13.44 shows simple keyboard
+5 V

w
0

K,

8051
Input K5

Fig. 13.4.4 Simple keyboard interface

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 Microprocessors and Microcontrollers 13-28 Applcations and Deslgn of Microcontroller Based Sysloms

3kR 28
TUUTUTUUUUID 4 Analog
Analog inputs
5
inputs
6

Address
SOC !

EOC ALE
0808/
DB3 DB7
OUTPUT CONTROL DB6
CLK DB5
Voc DB4
REF + DBO
GND 6) REF
DB1 DB2

Fig. 13.5.1 Pin diagram of ADC 0808/0809

Operation
ADC 0808/0809 has eight input channels, so to select desired input channel, it is
necessary to send 3-bit address on A, B and C inputs. The address of the desired
channel is sent to the multiplexer address inputs through port pins. After at least 50 ns,
this address must be latched. This can be achieved by sending ALE signal. After another
2.5 uS, the start of conversign (SOC) signal must be sent high and then low to start the
conversion process. To indicate end of conversion ADC 0808/0809 activates EOC signal.
The microprocessor system can read converted digita! word through data bus by
enabling the output enable signal after EOC is activated. This is illustrated in Fig. 13.5.2.
A
Address
50 ns+
ALE
e25 us
SOC
EOC

DBO Valid data

DB,

OE

Fig. 13.5.2 Timing waveforms for ADC 0808

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