Analysis of Low Power SRAM Design with Leakage

Control Techniques
Pavankumar Bikki Manoj Kumar Reddy T Muppa Annapurna Sayana Vujwala
Department of Electronics and Department of Electronics and Department of Electronics and Department of Electronics and
Communication Communication Communication Communication
NIT Andhra Pradesh NIT Andhra Pradesh NIT Andhra Pradesh NIT Andhra Pradesh
bikkipavan@gmail.com India India India
As the technology scales down in CMOS, issues like short
Abstract- In today’s digital era, memory is an inevitable part channel effects, stability of data storage and leakage currents
of any integrated device. Also it has a major part in the total circuit arise. Among the sources of leakage currents sub threshold
power. As the growing concern for portable devices is increasing
day by day, the nano-technology is grabbing the eyes of the chip
(‫ܫ‬௦௨௕̴௧௛ ሻis the major leakage component because of the low
makers. But the drain of power in portable devices which mainly threshold voltage we use in nano-CMOS technology. The
contains static random access memory (SRAM) units is inversely intensity of this leakage current is dependent on many factors
proportional to the technology used. In order to balance this trade such as supply voltage, temperature, dimensions and process
off various leakage reduction techniques have been proposed. In parameters like ܸ௧௛ (threshold voltage). Besides there are also
this paper we propose a hybrid circuit which involves biasing and other source of leakage currents like Gate oxide tunnelling
power gating techniques to improvise the reduction in leakage
power. Simulations have been carried out in Symica DE using 32 leakage, Reverse-bias, Junction leakage, Gate induced drain
nm technology. The hybrid circuit in HOLD state is compared leakage, Gate current due to hot-carrier injection [4][5], which
with some of the existing low power designs for leakage power and are shown in fig.2.
static noise margin (SNM).The hybrid-1 and hybrid-2 reduced the ‫ܫ‬௧௢௧௔௟ି௟௘௔௞ ൌ ‫ܫ‬௦௨௕̴௧௛ ൅ ‫ܫ‬௚௔௧௘ ൅ ‫ܫ‬௝௨௡௖௧௜௢௡  (1)
power leakages by 88.32% and 85.63% respectively and the SNM
is increased by 2 times by hybrid-1 while hybrid-2 maintained the
same SNM as that of the basic 6T SRAM cell.

Key words— Leakage current, low power, power gating,

biasing, SRAM, SNM, hybrid circuit.

I. INTRODUCTION
Static Random Access Memory commonly known as
SRAM is a type of RAM that holds data in static form but only
as long as the power is supplied. An SRAM is typically made
of two cross coupled inverters retaining either of the two stable
states 0 and 1 and two access transistors to be used while Fig. 1. Basic 6T SRAM cell
reading and writing operations. To store one memory bit it
requires six metal oxide semiconductor field effect transistors Basic 6T SRAM cell has limitations of power dissipation
(MOSFET). An SRAM has three different states of operations. and stability of the data during read and write operations. This
They are HOLD, READ and WRITE modes [1]. paper mainly concentrates on static power dissipation with
different techniques that reduces power dissipation like body
In fig.1, if the word line is kept low, the access transistor get biasing, power gating in section 2, analysis of various read
disconnected from the bit lines. The two cross coupled inverters decoupling circuits like 8T SRAM, PFC, PPN, PNN circuits
will continue to reinforce each other as long as they are which are used to stabilise data during read and write operations
connected to the supply. This is the operation in HOLD state. in section 3, demonstration of the hybrid circuit in section 4,
Whereas in READ and WRITE modes, the world line is given simulation results with tables, SNM values and graphs of
high such that there is an access between cross coupled leakage currents in section 5, Conclusions drawn from this
inverters and bit lines. The read cycle is started by pre charging paper in section 6.
both the bit lines to high voltage. The word line WL which is
asserted to high voltage will enable both the access transistors
which causes one of the bit lines voltage to slightly drop due to
the inverter storing 0 as data. A sense amplifier which senses
the voltage levels will determine whether the stored data is 0 or
1. The write cycle begins by applying voltage value to be
written into the bit lines. If we wish to write a 1 into the SRAM
cell we have to set bit line bar to 0 and bit line to 1. WL is
asserted a high voltage then and the value that is to be stored in
the cell will be latched in [2] [3]. Fig. 2. Sources of leakage currents in a MOSFET

978-1-7281-1034-9/19/$31.00 ©2019 IEEE

400
 C. Power Gating
Leakage
Power gating is another efficient technique to reduce
Dynamic
leakages. In this scheme the introduction of external header and
footer transistors almost minimises the leakage currents as they
eliminate the path which is existing between the supply rail and
ground rail. M. Powell et al. has proposed a power gating
technique using a sleep transistor in the ground path calling it a
Gated-ܸௗௗ , which is shown in fig. 5. This design is basically to
introduce a gating between the supply and the ground rail. This
transistor gates the cells power such that the sleep transistor is
switched on in active state and switched off in ideal state. This
scheme significantly reduces the leakage currents besides
Fig. 3. Dynamic and Static leakages with various technologies [17]
improving the performance [12][13]

II. POWER GATING AND BODY BIASING

TECHNIQUES
In this section various power reduction techniques involving
body biasing and power gating are discussed. Generally the
body terminal of the MOSFET is connected to supply voltage
in case of PMOS and to the ground in NMOS. In order to
control the threshold voltage, the body and source junctions are
to be forward or reverse biased [6]. Dynamic and Static
leakages with various technologies are shown in fig. 3.
A. Reverse body bias
In order to create a reverse junction between the body and
the source terminals, the body voltage of PMOS should be Fig. 5. Gated- ܸௗௗ Power gating scheme
greater than ܸௗௗ  and the body voltage of NMOS should be
lesser than ୋ୒ୈ . Self-reverse biasing in NMOS and PMOS III. READ DECOUPLING CIRCUIT
are shown in fig.4. This increases the width of depletion layer. SRAM faces the problem of data instability while reading
RBB is widely used in memory cells to reduce the latch up the data from bit lines i.e. if the node Q stores a bit 0 and the
problem and damage to memory data [7]. It reduces the sub- bit line is pre charged to a high voltage, then the voltage
threshold leakage besides increasing the body voltage. Thus discharges from the bit line to the ground through the
RBB reduces the leakage current in total. But RBB is less corresponding NMOS. While discharging, if the voltage at node
effective to control leakages in short channel devices and also Q increases beyond ܸ௧௛ of NMOS of the other inverter the node
in low threshold devices [8]. voltage at Q bar is shorted as it gets switched on due to this the
data stored at node Q bar changed to 0 and to 1 at node Q. In
order to solve this issue of instability of data, an extra circuit is
added (read decoupling circuit as shown in fig. 6) which isolates
read and write operation of the SRAM cell. Due to the addition
of these transistors to the SRAM cell there is an increase in read
SNM and also in the leakage currents which is a trade-off. This
trade off can be overcomed by stacking transistors in read
Fig. 4. Self-reverse biasing in NMOS and PMOS decoupling circuit which decreases static leakages like sub-
threshold leakages to some extent [14].
B. Forward body bias
In order to create a forward junction between the body and
the source terminals, the body voltage of PMOS should be
lesser than ܸௗௗ  and the body voltage of NMOS should be
greater than ܸீே஽ . This decreases the width of the depletion
layer. FBB reduces the ܸ௧௛ of high threshold devices and helps
in improving the circuit performance because of its smaller
switching capacitance. Larger junction capacitances are formed
by the FBB devices due to the reduction in depletion between
the source and drain regions [9][10]. But FBB is ineffective in
controlling the leakage currents because the source and the
body junction forms a forward bias. The short circuit current Fig. 6. Read decoupling circuit- 8T SRAM
increases at lower ܸ௧௛ because of larger junction capacitance
and gate capacitance [11].

401
A. PFC 10T SRAM cell
10T SRAM cell is proposed to improve the cell stability and
reduction in leakages, known as PFC 10T SRAM cell as shown
in fig. 7. In this design it was proposed that addition of two more
transistors called feedback cutting transistors which cut the path
existing between the supply and ground rail reduces the
leakages. These two additional transistors are controlled by two
control signals CS1 and CS2 such that they improve the speeds
of READ and WRITE operations, SNM and leakage power of
the cell. But the drawback is that the layout area of the cell is
about 1.45 times higher than that of the basic 6T SRAM cell
[15].
Fig. 7. PFC 10T SRAM cell Fig. 8. PPN 10T SRAM cell
Fig. 9. PNN 10T SRAM cell
B. PPN 10T SRAM cell
PPN 10T SRAM cell has P-P-N combination of a two
inverters as shown in fig 8. Which can be used for ultra-low
voltages i.e. as low as 285 mV besides maintaining ultra-low
leakages in the cell, maintaining high immunity to the bit-line
leakages which are data-dependent on maintaining a balanced
SNM. In this circuit, the method of stacking can be observed
which acts as a source of leakage reduction in MOSFET. This
design also occupies more area than the basic 6T SRAM cell as
it contains four additional transistors [16].
C. PNN 10T SRAM cell
A proposed SRAM cell which is useful in robust operations
maintained at sub threshold voltages without the use of boosting
circuitry. This proposed 10T PNN circuit as shown in fig.9.
Basically consists of two access ports used for differential
access and a dual footed latch. To operate in HOLD state, all
the signals used to control the three different states are turned
off so that the access transistors are disconnected. This bit cell
turns out to have higher write stability and hold ability besides
maintaining low leakages [17].
IV. PROPOSED 7T HYBRID SRAM CELLS
This hybrid circuits are implemented on the basis of results
obtained by analysing both biasing and gating techniques
individually. In power gating, different combinations like footer
off, footer on, header on, header on and footer on, header on and
footer off are implemented and the circuit with best reduction in
power, leakage currents along with improving the static noise
margin is selected.
Fig. 10. Hybrid circuit 1
Fig. 11. Hybrid circuit 2
In the next step, the analysis of body biasing in different
combinations of previously existing combinations like
providing body biasing to the transistors which are circled in
fig.10, fig. 11, fig. 12 and fig. 13 is carried out and among all
reverse body bias to the source and body of the MOSFETS gave
best leakage current reduction. The circuit with best
performance and leakage reduction is taken out and further used
to implement the hybrid circuit. Thus the hybrid circuits use the
techniques of both body biasing and power gating in the aim to
reduce various leakage currents like reverse bias junction
leakages, sub-threshold leakages and creating a gating between
the supply and ground rails. Also it has increased the
performance of the cell by increasing the static noise margin
(SNM). Analysis of some of the existing read decoupling
circuits is carried out and these results are compared with the
results of basic 6T SRAM cell and with the hybrid circuits.
402

Fig. 12. Reverse Body biasing
applied to M2 and M3
Fig. 13. Reverse Body biasing
applied to M2, M3 and M4
Since we have analysed the circuits in HOLD state taking 1
at node Q and 0 at node Qbar. In table 2, case 4, reverse biasing
M1 prevents the transition at node Q from 1 to 0 through it and
M4 prevents the transition at node Qbar from 0 to 1 due to Vdd.
Same is the reason in case 3. Whereas in case 1 and case 2, even
though M2 and M3 reduces leakages source and body, there is
a direct path at node Q and Qbar to between their respective
change their respective states.
These combinations which gave minimum leakages in the
above techniques are combined to form hybrid circuits
consisting of a footer off transistor attached to a SRAM cell
with M1 and M4 reverse biased and the other combination. The
following tables show the leakages in different combinations.
Table 3. Comparative results of power dissipation and SNM in HOLD state

Circuit SNM(mV) Power(uW) Leakage

currents(uA)
6T SRAM cell 48.8 0.598 0.498
Read decoupled- 378.8 0.246 0.205
8T[14]
PFC 10T[15] 378.8 0.672 0.560
PPN 10T[16] 488 1.258 1.048
Fig. 14. Reverse Body biasing applied Fig. 15. Reverse Body biasing PNN 10T[17] 342.2 0.449 0.375
to M1, M2, M3 and M4 applied to M1 and M4
Hybrid – 1 97.7 0.069 0.059
V. SIMULATION RESULTS Hybrid – 2 48.8 0.086 0.073
The proposed designs are analysed using Symica DE using
32nm technology and supply voltage at 1.2V. All the circuits Stability of the data is defined from the Static Noise Margin
are simulated considering the HOLD state of SRAM cell. These (SNM) of the circuit. SNM is termed as to how much extent it
analysis have shown that the power gating techniques are can accept the noise without manipulation of data stored in cell.
efficient when there is a footer transistor that is switched off and Hence SNM of the cell should be as high as possible. It can be
when there is a header on and footer off condition. While estimated by inserting the largest possible square in the loop
analysing body biasing combinations it is found that the SRAM formed by voltage transfer curves (VTC) of the two CMOS
cell gave minimum leakages when the transistors M1 and M4 inverters as shown in the fig 16. SNM is defined as the side-
are reverse biased and when all the four cross coupled length of the square, given in volts.
transistors are reverse biased.
Table 1. Comparative results of power dissipation using power gating

Circuit Number of Power(uW) Leakage

transistors currents(uA)
Header on 7T 0.601 0.501
Footer on 7T 0.759 0.630
Footer off 7T 0.214 0.178
Header on and 8T 0.217 0.181
footer off
Header on and 8T 0.759 0.632
Footer on
Fig. 16. Butterfly curve for the SRAM cell

Table 2. Comparative results of power dissipation using body biasing The temperature versus leakage graphs are as shown in fig.
17. It is observed that the leakages are very low in both the
Circuit- Number of Power(uW) Leakage hybrid circuits when compared to the basic 6T SRAM cell.
Modifications transistors currents(uA) Supply voltage versus leakage current in hold state as shown in
M2 and M3 6T 125.79 104.85 fig.18 the leakage current at the voltage source shows that the
M2, M3 and M4 6T 125.36 104.47 hybrid circuits are least affected by the supply voltage variation
M1, M2, M3 and M4 6T 0.072 0.062 whereas the basic 6T SRAM cell suffers the most.
M1 and M4 6T 0.302 0.253

403
 2000
Read Decoupled 8T
PPN 10T
Leakage Currents (nA)
1500
Hybrid 1
Basic 6T
1000
500
0 [3]
0 10 20
Fig. 17. Temperature versus leakage currents
3000
Current Leakage at VDD (nA)
Read decoupling 8T
2500
PPN 10T
hybrid 1
2000
Basic 6T
1500
1000
500
0 Ground Cache for Deep Submicron”. IEEE Journal of Solid State Circuits
0 0.5
Fig. 18. Supply voltage versus leakage current in hold state
The SNM which determines the stability of the data stored
in the cell should be as high as possible. The SNM of the
implemented hybrid- 1 and hybrid- 2 are found to be 97.7mV
and 48.8mV respectively whereas the SNM of the basic 6T
SRAM cell is found to be 48.8mV. It is observed that there is a
great reduction in power dissipation in the proposed hybrid-1
and hybrid-2 when compared to basic 6T SRAM cell and the
other circuits analysed in this paper. The power dissipation is
reduced to an extent of 88.32% in hybrid-1 and 85.63% in
hybrid-2. The Static Noise Margin which determines the
stability of the circuit has increased by 2 times in hybrid-1 and
maintained same by hybrid-2 besides maintaining minimum
power leakage by both the hybrid circuits.
VI.
This paper started with the description of 6T SRAM cell and
various leakage currents that effect the functionality and
stability of the SRAM cell that occurs with the scaling down of
technology. It also included different leakage reduction
techniques like body biasing, power gating and how the leakage
varies with different combinations of power gating and body
biasing techniques. Also, it contains the effect of read
decoupling circuits and leakages in HOLD state. It is observed
that the proposed circuits i.e. hybrid-1 has the leakage power
which is 8.56 times lesser than the basic 6T SRAM cell i.e.
88.32% reduction in power dissipation and hybrid-2 has the
leakage power which is 6.96 times lesser than the basic 6T
SRAM cell i.e. 85.63% reduction in power dissipation. Also
hybrid-1 increases the stability by 2 times whereas hybrid-2
PFC 10T maintained the same stability that of basic 6T SRAM cell. This
PNN 10T paper can further be used to explore some other leakage
reduction techniques in Static Random Access Memory
Hybrid 2
(SRAM).
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