International Conference on Communication and Signal Processing, April 3-5, 2014, India

Analysis of Leakage Current and Leakage

Power Reduction during Write operation in
CMOS SRAM Cell
K. Khare, R. Kar, D. Mandai, and S.P. Ghoshal

deep submicron technology

<100nm
Abstract-Leakage power is a major issue for short channel Decreased threshold voltage and thinner gate oxide also
devices. As the technology is shrinking (i.e., 180nm, 90nm, 45nm. increases the leakage current [2]. This paper gives the idea of
etc.) the leakage current is increasing very fast. So, several
basic 6T SRAM design technique and how much power is
methods and techniques have been proposed for leakage
reduction in CMOS digital integrated circuits. Leakage power
consumed with it. 6T SRAM cell basically consists of four
dissipation has become a sizable proportion of the total power cross-coupled transistors. There are two NMOS access and
dissipation in integrated circuit. This paper demonstrates the driver transistors. In the next part, ST SRAM model is
ideas of 6T, 8T and lOT models with sleep transistors. This designed. In this method there are two extra NMOS transistors
proposed SRAM cells give the advantages over basic 6T, 8T and
connected in series called 'stack' approach [3]. Leakage power
lOT transistor models. The SRAM cell with sleep transistor
is reduced as compared to basic 6T SRAM cell due to increase
shows better leakage reduction approach than stack approaches.
Here in this paper Analog environment virtuoso (cadence)
in the threshold voltage of the NMOS device. Next, 10T­
simulator is used for analysis of the power associated with CMOS transistor circuit is designed. In this method there are S cross­
SRAM cell for 180nm technology. coupled transistors and leakage is drastically reduced in an
exponential manner with the increase of threshold voltage. In
Index Terms---6T-SRAM cell, Leakage current and leakage
the later part, this paper describes comparison of conventional
power, Proposed 6T, 8T and lOT transistor models, Sub­
models with the proposed models.
threshold leakage reduction.
The rest of this paper is organized as follows. Section II gives
I. INTRODUCTION the brief idea of the previous research on sub-threshold
leakage reduction for various SRAM models, section III

F 65nm),
OR the most recent CMOS feature sizes (e.g., 90nm and
describes the basic SRAM models using 6T, ST and lOT
leakage power dissipation has become an
transistor model. In section IV, proposed low leakage SRAM
overriding concern for VLSI circuit designers.
models are shown. Here the leakage is reduced by the sleep
For the DSM (Deep submicron technology) circuit, the size of
transistors connected with pull-up and pull-down network. In
CMOS integrated circuits is shrinking day by day. So, the
the section V, the result part is discussed and compares
power dissipation is a major issue for the short channel devices
leakage current and leakage power for various SRAM cells.
and the performance of digital integrated circuits is challenged
The section VI demonstrates the conclusion of this paper and
by higher power consumption [1]. On the other side, scaling of
gives the idea that which model is better for low leakage
the transistor improves the density and functionality of a chip.
reduction.
Scaling also results in higher speed of operation and improves
the performance of the device. Scalling-> lower technology node
II. PREVIOUS WORK
shrink of size
K. Khare is the student of Electronics and Communication Static power consumption is a major concern in nanometer
Engineering Department, National Institute of Technology, Durgapur, technologies. There are many sources of sub-threshold leakage
West Bengal, 713209 INDIA (e-mail: kapilkhare2012@gmail.com). flow in MOS transistors.
R. Kar is with the Electronics and Communication Engineering
Department, National Institute of Technology, Durgapur, West Bengal The authors in [4] examine the various SRAM cell models
713209 INDIA (e-mail: rajibkarece@gmail.com). (ST, 9T and lOT) associated with the conventional 6T SRAM
D. MandaI is with the Electronics and Communication Engineering cell. The result section of this paper shows that the leakage
Department, National Institute of Technology, Durgapur, West Bengal
713209 INDIA (e-mail: durbadal.mondal@ece.nitdgp.ac.in).
power is drastically reduced in the sleep transistors approach
S.P. Ghoshal is with the Electrical Engineering Department, National as compared to the stack approach. Thus, this paper concludes
Institute of Technology, Durgapur, West Bengal 713209 INDIA (e-mail: that leakage reduction through sleep transistor method gives
spghoshalnitdgp@gmail.com).
the best performance over the other models. The drawback is
the same as mentioned above that the increased area and

97S-1-4799-335S-7114/$31.00 ©2014 IEEE +-IEEE

Advancing Technology
for Humanity

523
spacing problems arise.
In the thesis [5] other techniques like forced sleep approach,
forced stack approach, sleep stack approach and sleep keeper
approach are used to optimize the leakage reduction in basic
6T SRAM cell model. The result section concludes that the
forced sleep approach is the best one because it reduces almost
88% sub-threshold leakage power as compared to the simple
sleep transistor model. The biggest advantage of this method is
it consumed low area and delay as compared to the other
models.
additional stack transistors below the NMOS transistors. The
additional stack NMOS M7 and M8 transistors increase the
threshold voltage (Vth) in order to reduce the sub-threshold
current so that the leakage power will be reduced. Some
leakage reduction models based on stack effect are in [10].
In Fig. 2 six transistors (M2, M3, M5, M6, M7 and M8) are
cross-coupled. Initially, assume Q is '0' and QB is '1'. The bit
line BL=1 and BLB=O. The word line WL is high in write
operation. After simulation, the node voltage Q would be '1'
and the QB would be '0'. This is a write '1' operation [11].

1
III. CONVENTIONAL SRAM MODELS

A. Conventional 6T SRAM Cell Design

Static Random Access Memory (SRAM) is a type of
semiconductor memory and it is volatile in nature. SRAM t--+---i QB
t------i----i
contains a latching circuitry to store each bit (0 or 1). The
basic 6T SRAM memory cell is shown below [6]. In Fig. 1
there are four cross-coupled MOS transistors (M2, M3, M5,
and M6). Two NMOS pass transistors (M l and M4) are used
to control the access to the cell during read and write
operations and these are connected through the bit lines and
word line [7]. Here there are two nodes Q and QB which store
Fig. 2. 8T SRAM.
two alternate bits 0 and land vice-versa. For the accurate and
proper operation of the SRAM cell, the sizes of the transistors C. 1 OT SRAM Model
are designed properly. In lOT SRAM model there are two PMOS (M5 and M6) and
8l WL
BLB
two NMOS (M9 and MI0) transistors connected to the
conventional 6T SRAM circuit in a 'stack' form. In Fig. 3,
eight transistors (M2-M3, M5-M6, M7-M8 and M9-MIO) are
cross-coupled. The pairs of M5-M6 and M9-MI0 are called
leakage control transistors. Here two leakage control
transistors NMOS (M9 and MIO) and PMOS (M5 and M6) are
connected with two symmetrical invertors. Here in Fig.3 drain
terminals of both the transistors (M7 and M2) or, (M8 and
M3) are connected to the nodes Q and QB and produce output
voltages, respectively. By the properties of leakage control
transistors (M5-M6) and (M9-MI0), they will work near its
cut-off region, so their resistances will be lesser than their OFF
resistances, thus allowing a little conduction [12]. Even though
Fig. I. Basic 6T SRAM Cell. the resistances are not as high as their OFF state resistances,
they increase the resistance from Vdd to ground path,
1) 6T SRAM Write Operation controlling the flow of lower leakage currents, resulting in
For the proper write operation, bit line BLB is kept at '1' leakage power reduction [13].
and bit line BL is kept at '0'. The word line will always be
high for the proper read and write operation. By choosing the
BL
proper sizes of the transistors, the BLB and BL line data
would be transferred to nodes QB and Q, respectively [8]. For
the write operation, assume that ' l' is stored at node Q and '0'
is stored at node QB. The transistors M l and M5 are 'ON' and
transistors M3 and M4 are in 'ON' state [9]. If we select
BLB= 1 and BL=O then these node voltages (' l' and '0') are
transferred to the nodes (QB and Q), respectively.
According to size: ( :l ( :J ( : (1)
>
1 >

B. 8T SRAM Model
Fig. 3. lOT SRAM.
This is similar to that of 6T SRAM cell except that there are

524
 IV. PROPOSED Low LEAKAGE SRAM CELLS
In this section instead of stack transistors sleep transistor
approach is used. Sleep transistors are the two extra transistors
connected to the SRAM load circuit.
A. 6T SRAM with sleep transistors
Solutions for leakage reduction are required at both process
technology and circuit levels [14]. One of the methods at
circuit level to reduce the leakage power is by adding two
sleep transistors in 6T SRAM circuit. According to the
placement of sleep transistors PMOS (M7) and NMOS (M8),
two types are considered.
The type-I circuit shown in Fig. 4. In the active mode,
PMOS M7 gate input (S') is kept low and NMOS M8 gate
input (S) is kept high. So, both the sleep transistors are turned
'ON'. So, according to the pass transistors property, source
nodes of two PMOS SRAM load transistors are at Vdd.
Similarly, the source nodes of two NMOS SRAM load
transistors are at '0'. In the stand-by mode, both the sleep
transistors (M7 and M8) are turned 'OFF'. So, leakage power
is reduced in a stand-by mode when sleep transistors are in
cut-off state [15].
Bl
BLB
gnd
7TTTT
Fig. 4. 6T SRAM with sleep transistors (type - T).
Next, type-II case is considered. The placement of the
NMOS (M8) and PMOS (M7) sleep transistors are
interchanged. So, the modified circuit is shown in Fig. 5.
WL
Bl
BLB
7777Td
Fig. 5. 6T SRAM with sleep transistors (type - II).
525
In the active mode of operation, both the sleep transistors
NMOS (M8) and PMOS (M7) are turned on. According to the
NMOS and PMOS pass transistors' property; the voltage at the
source node of M8 would be Vdd-Vth whereas the voltage at the
source node of M7 would be �Vth. In the stand-by mode of
operation both the sleep transistors M8 and M7 are turned off
and these transistors provide very high impedance paths
between Vdd to ground and a very small sub-threshold leakage
current flows.
B. 8T SRAM with Sleep Transistors
In this section, method of 8T transistors with sleep
transistors is discussed. Here two sleep PMOS (M7) and
NMOS (M8) transistors are connected with pull-up (M5 and
M6) and pull-down (M2 and M3) networks, respectively, in
Fig.6. In the basic 8T model, the leakage reduction is due to
increase in threshold voltage (Vtlt) and Vtlt is increased due to
stack effect of NMOS (M8 and M9) transistors in pull-down
network.
Fig. 6. 8T SRAM with sleep transistors (type - I).
For the type-I circuit, in the active mode, both the sleep
transistors (M7 and M10) are turned 'ON'. So, M7 passes full
supply swing (Vdd) and MI0 passes full ground voltage ('0').
In the stand-by mode both transistors PMOS (M7) and NMOS
(M lO) are in 'OFF' state and leakage is reduced. When both
the word lines WL are high, write operation will start. This
model has reduced sub-threshold leakage power more as
compared to the basic 8T SRAM cell.
Now, for the type-II circuit, the positions of NMOS (MI0)
and PMOS (M7) are interchanged. In active mode of operation
both the sleep transistors M7 as well as the MI0 are turned on.
So, the source terminal voltage of the NMOS (MI0) would be
� (Vdd- Vth) and the source terminal of the PMOS (M7) would
be �Vth. In stand-by operation the basic SRAM load circuit is
disconnected from the supply voltage. So, due to the higher
impedance path is formed between V dd to ground, a very small
sub-threshold leakage current flows. The technique is called
forced sleep technique.
 ground. When the input signal (S· = 1 ) is high, the output is
� Vth Thus smaller leakage current Ids will flow through the
'

transistors and leakage is reduced.

BL

Fig. 7. 8T SRAM with sleep transistor (type- II).

C. lOT SRAM with Sleep Transistor

Fig. 9. lOT SRAM with sleep transistors (type- II).
Here two PMOS M5 and M6 transistors and two NMOS M9
and MIO transistors are connected in stack form. There are V . RESULTS AND DISCUSSIONS
eight cross-coupled transistors connected serially. There are
In this paper Cadence virtuoso simulator is used to fmd out
two sleep transistors (M l land MI2).
the sub-threshold leakage reduction in CMOS SRAM cell
For the type-I circuit (Fig. 8), there are two sleep transistors
models with 180nm technology. Table-I shows, leakage
(Mi l and MI2). The PMOS sleep transistor (MI2) is
current is very high for the basic SRAM models (6T, 8T and
connected between supply voltage and SRAM load and
lOT). For the type- II SRAM models with sleep transistors
NMOS sleep transistor (Mi l) is connected between SRAM
yields far better performance over the basic SRAM models and
load and ground terminal [16]. The circuit is shown in Fig. 10.
better performance over the type-I models. Similarly, the 8T
In the active mode, both the sleep transistors Mi l and MI2
SRAM type-II model yields almost 98% leakage current and
are turned on by putting s'=o and S= l. Thus, the drain node of
power reduction over basic 8T SRAM models and for lOT
MI2 becomes 'I' and drain node of Mi l becomes '0'. In the
model, type-II model yields almost 99% reduction of leakage
stand-by mode, both the sleep transistors are turned off. So,
current and leakage power over basic lOT SRAM model.
the basic 8T SRAM load circuit is disconnected from the
supply voltage (Vdd) and ground. Thus, the small leakage
TABLE I
current flows in this mode. COMPARISON OF LEAKAGE POWER FOR VARIOUS CELLS
Circuit Total Write Leakage Total Write Leakage
(I80 nm Current Power
Technology) (pA) (pW)

Basic 6T SRAM 82.26 148.1

BL Cell [18]
6T SRAM with 3.84 6.914
sleep transistors
type-I
6T SRAM with 0.251 0.452
sleep transistors
type-II
8T SRAM cell 19.39 34.9
model
[19]
"'777'T"T'T" 8T SRAM with 3.73 6.721
Fig. 8. lOT SRAM with sleep transistor (type- I). sleep transistors
type-I
In type-II (Fig.9), the NMOS sleep transistor (Mi l) is 8T SRAM with 0.218 0.392
sleep transistors
connected to Vdd and the PMOS sleep transistor (MI2) is
type-II
connected to ground [17]. During active mode both NMOS lOT SRAM Model 12.77 22.99
and PMOS sleep transistors (Mi l and M12) are turned "ON". [20]
lOT SRAM with 2.92 5.25
So, NMOS (MI l) transistor is connected to Vdd (S=I). During
sleep transistors
sleep mode, it is not efficient in passing Vdd so when the inputs type-I
are low, the output voltage is reduced to (Vdd-Vth) . Smaller
� lOT SRAM with 0.1915 0.344
leakage current Ids will flow through the transistors and the sleep transistors
type-II
stack transistors also. The PMOS (MI2) is connected to

526
It is noted that, type-II models give better sub-threshold
leakage reductions as compared to the corresponding type-I
models. For type-I circuits in active mode, both sleep
transistors are turned on. Hence the drain node of PMOS sleep
would be Vdd and drain node of NMOS would be ground
voltage. In stand-by mode, this makes the two transistors
PMOS sleep as well as the NMOS sleep transistors enter into
cut-off state. Due to the cut-off sleep transistors PMOS and
NMOS, the potential at drain node of NMOS sleep is
increased and the potential at drain node of PMOS sleep is
dropped. So, the sources to body potentials (VSb) of both the
sleep transistors are increased. Thus, according to (2), the
threshold voltages are increased, so leakages are reduced in
both the circuits.
V; = VTO ( JI- 2<PF
+ + VSbl- JI2<pFI ) (2)
Next, for type- II circuits in all cases (6T, 8T and 10 T), the
PMOS sleep transistor is connected in the pull-down and
NMOS sleep transistor in the pull-up path. In active mode,
both the sleep transistors PMOS and NMOS are turned on. So,
source node of NMOS is at lower potential (Vdd-Vllt) than Vdd
and the source node of PMOS is at lower potential (�Vlh) than
the ground voltage. Thus, the potential differences across drain
to source nodes of NMOS as well as PMOS sleep transistors
are obtained. Due to potential difference, the current through
each circuit reduces and power dissipation also reduces. But in
stand-by mode, both the sleep transistors PMOS and NMOS
are turned off and these transistors provide very high
impedance path between Vdd to ground and leakage currents
are lowered. The power dissipation during this standby mode
of operation is the lowest. Thus, lOT SRAM with sleep
transistor model (type-II) yields the best sub-threshold leakage
reduction approach as compared to the corresponding models.
VI. CONCLUSION
Study of the results show that, lOT SRAM specially type-II
with sleep model is the best technique and it yields more than
98% leakage power reduction as compared to the basic lOT
SRAM cell and almost 99% leakage power as over the basic
6T SRAM cell, which is the major advantage of short channel
devices. The sleep circuits reduce leakage power when these
operate in "stand-by mode" due to inefficient passing of the
voltages (pass-transistors property). In this paper as the
number of transistors increase (8T, 9T and lOT) leakage
power reduces but area and delay also increase more and
more. Hence the authors conclude the proposed SRAM
circuits specially type- II circuit, used for low power designs
can be used for low power applications.
VII. REFERENCES
[I] Y. Taur and 1. H. Ning, "Fundamentals of Modern VLSi Devices",
New York, USA: Cambridge University Press, 1998, ch. 3, pp. 120-
128.
[2] Kim. N, Austin. T, Baauw.D, Mudge. T, Flautner. K, HU. J, Irwin.
M, Kandemir.M, and Narayanan.V, "Leakage Current: Moore's Law
Meets Static Power", iEEE Computer, vol. 36, pp. 68-75, December
2003.
527
[3] International Technology Roadmap for Semiconductors by
Semiconductor Industry Association, 2002. [Online] Available:
http://public.itrs.net.
[4] Soumya Gadag, Raviraj D. Chougla, "Design and Analysis of 6T
SRAM Cell with Low Power Dissipation", International Journal of
Engineering Research and Application (IJERA), vol. 2, Issue 6, pp.
1695-1698, Nov.- Dec. 2012.
[5] Tajrian Izma, Parag Barua, Md. Rejaur Rahman, and Priyanka
Sengupta, "Novel Approaches to Low Leakage and Area Efficient
VLSI Design" Ph.D thesis, Dept. Electrical and Electronics Eng.,
BARC Univ., Dhaka, August 2011.
[6] Neeraj Kr. Shukla, Shilpi Birla, R.K Singh, and Manisha Pattanaik,
"Speed and Leakage Power Trad-off in Various SRAM Circuits",
international Journal of Computer and Electrical Engineering
(IJCEE), Singapore, vol. 3, No.2, Apr. 20 l l, pp. 244-249.
[7] Keivan Navi, Roshanak Zabihi, Majid Haghparast, Touraj Nikobin,
"A Noval Mixed Current and Dynamic Voltage Full Adder", World
Applied Sciences Journal, vol. 4, no.2, pp. 289-294, 2008.
[8] A Deepak Lourts, and L. Dhulipalla, "Design and implementation of
32nm FINFET based 4*4 SRAM cell array using I-bit 6T SRAM",
International Conference on Nanoscience, Engineering and
Technology (ICONSET), pp. 177-180, 28-30 November 2011.
[9] Kavita Khare, Nilay Khare, Vijendra Kumar Kulhade, and Pallavi
Deshpande, "VLSI Design and Analysis of Low Power 6T SRAM
Cell Using Cadence Tool", International Conference on
Semiconductor Electronics (ICSE), pp. 117-121, Malaysia,
November 2008.
[10] S. Narendra, V. DE, S. Borkar, D.A Antoniadis, and AP.
Chandrakasan, "Full-Chip Subthreshold Leakage Power Prediction
and Reduction Techniques for Sub-0.18um CMOS," iEEE Journal of
Solid-State Circuits, vol. 39, no. 2, pp. 501-510, February 2004.
[II] Z. Chen, M. Johnson, L. Wei and K.Roy, "Estimation of Standby
Leakage Power in CMOS Circuits Considering Accurate Modeling of
Transistor Stack", international Symoposium on Low Power
Electronics and Design, pp. 239-244, August 1998.
S. Mutoh, TDouseki, and Y.Matsuya, "IV Power Supply High-speed
[12]
Digital Circuit Technology with Multithreshold-Voltage CMOS,"
iEEE J. Solid-state Circuits, vol. 30, pp. 847-854, Aug., 1995.
[13] Atluri. Jhansi rani, K. Harikishore, Fazal Noor Basha, and V.G.
Santhi Swaroop, "Designing and Analysis of 8 Bit SRAM Cell with
Low Subthreshold Leakage Power" International Journal of Modern
Engineering Research (IJMER), vol.2, Issue.3, pp. 733-741, May­
June 2012.
[14] M.Powell, S.H. Yang, B. Falsafi, K. Roy and TN. Vijay Kumar,
"Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep
Submicron Cache Memories", International Symposium on Low
Power Electronics and DeSign, pp. 90-95, July 2000.
[15] Andrei Povlov, O. Semenov and Manoj Sachdev, "Sub-quarter
micron SRAM cells stability in low-voltage operation: a comparative
analysis", iEEE International Integrated Reliability Workshop Final
Report, pp. 168-171, 21-24 October 2002.
[16] M. Johnson, D. Somasekhar, L. Chiou, and K. Roy, "Leakage
Control with Efficient Use of Transistor Stacks in Single Threshold
CMOS", iEEE trans. on VLSi Systems, vol. 10, no. I, pp. 1-5,
February 2002.
[17] J.c. Park, V. J. Mooney m, and P. Pfeiffenberger, "Sleep Stack
Reduction of Leakage Power," Proceeding of the International
Workshop on Power and Timing Modeling, Optimization and
Simulation, pp. 148-158, September 2004.
[18] Paridhi Athe and S. Dasgupta, "A Comprarative Study of 6T, 8T and
9T Decanano SRAM cell", iEEE Symposium on industrial
Electronics and Application (ISIEA 2009), vol.2, pp. 889-894, Kuala
Lumpur Malaysia, Oct. 4-6, 2009.
[19] Weijie Cheng, Baolong Zhou, Huarong Zheng, and Yeonbae Chung,
"Stack- Transistor Based Differential 8T SRAM Cell for Embedded
Memory Application", iEEE International Conference on Electron
Devices and Solid State Circuit (EDSSC 2012), pp. 1-2, Bangkok,
Dec. 3-5, 2012.
[20] A Feki, B. Allard, d.Turgis, J. Lafont, and L. Ciampolini, "Proposal
of a new ultra low leakage lOT sub-threshold SRAM bitcell",
international SoC Design Conference (ISOCC 2012), pp. 470-474, ,
Jeju Island, Nov. 4-7, 2012.