library ieee;

use ieee.std_logic_1164.all;

entity tanmay_DeMorg1_LHS is

port(A:in std_logic;

B:in std_logic;

C:out std_logic);

end tanmay_DeMorg1_LHS;

architecture tanmay_DeMorg1_LHS_arch of tanmay_DeMorg1_LHS is

begin

C<=NOT(A AND B);

end tanmay_DeMorg1_LHS_arch;
library ieee;

use ieee.std_logic_1164.all;

entity tanmay_DeMorg1_RHS is

port(A:in std_logic;

B:in std_logic;

C:out std_logic);

end tanmay_DeMorg1_RHS;

architecture tanmay_DeMorg1_RHS_arch of tanmay_DeMorg1_RHS is

begin

C<=(NOT A) OR (NOT B);

end tanmay_DeMorg1_RHS_arch;
library ieee;

use ieee.std_logic_1164.all;

entity tanmay_DeMorg2_LHS is

port(A:in std_logic;

B:in std_logic;

C:out std_logic);

end tanmay_DeMorg2_LHS;

architecture tanmay_DeMorg2_LHS_arch of tanmay_DeMorg2_LHS is

begin

C<=NOT(A or B);

end tanmay_DeMorg2_LHS_arch;
library ieee;

use ieee.std_logic_1164.all;

entity tanmay_DeMorg2_RHS is

port(A:in std_logic;

B:in std_logic;

C:out std_logic);

end tanmay_DeMorg2_RHS;

architecture tanmay_DeMorg2_RHS_arch of tanmay_DeMorg2_RHS is

begin

C<=(NOT A) AND (NOT B);

end tanmay_DeMorg2_RHS_arch;