BASIC STEPS OF IC FABRICATION

Integrated Circuit (IC)

An Integrated Circuit (IC) is also called as chip or microchip. It is a semiconductor
wafer in which millions of components are fabricated. The active and passive components such
as resistors, diodes, transistors etc and external connections are usually fabricated in on
extremely tiny single chip of silicon. All circuit components and interconnections are formed
on single thin wafer (substrate) is called monolithic IC. IC is very small in size. It require
microscope to see connections between components. The steps to fabricate IC chips is similar
to the steps required to fabricate transistors, diodes etc. In IC chips, the fabrication of circuit
elements such as transistors, diodes, capacitors etc. and their interconnections are done at same
time. It has so many advantages such as extremely small size, small weight, low cost, low
power consumption, high processing speed, easy replacement, etc. IC is the principal
component in all electronic devices. IC can function as amplifier, oscillator, timer, counter,
computer memory etc.
The manufacturing of Integrated Circuits (IC) consists of following steps
1.Wafer production
2.Expitaxial growth
3. Etching
4. Masking
5.Doping
6.Atomic diffusion
7.Ion implantation
8.Metallization
9.Assembly and packaging

Steps for IC fabrication

Wafer production
The first step is wafer production. The wafer is a round slice of semiconductor material
such as silicon. Silicon is preferred due to its characteristics. It is more suitable for
manufacturing IC. It is the base or substrate for entire chip. First purified polycrystalline
silicon is created from the sand. Then it is heated to produce molten liquid. A small piece of
solid silicon is dipped on the molten liquid. Then the solid silicon (seed) is slowly pulled from
the melt. The liquid cools to form single crystal ingot. A thin round wafer of silicon is cut
using wafer slicer. Wafer slicer is a precise cutting machine and each slice having thickness
about .01 to .025inches. When wafer is sliced, the surface will be damaged. It can be
smoothening by polishing. After polishing the wafer, it must thoroughly clean and dried. The
wafers are cleaned using high purity low particle chemicals. The silicon wafers are exposed to
ultra-pure oxygen.
 Epitaxial growth
It means the growing of single silicon crystal upon original silicon substrate. A uniform
layer of silicon dioxide is formed on the surface of wafer.
Masking
To protect some area of wafer when working on another area, a process
called photolithography is used. The process of photolithography includes masking with a
photographic mask and photo etching. A photoresist film is applied on the wafer. The wafer is
aligned to a mask using photo aligner. Then it is exposed to ultraviolet light through mask.
Before that the wafer must be aligned with the mask. Generally, there are automatic tools for
alignment purpose.
Etching
It removes material selectively from the surface of wafer to create patterns. The pattern
is defined by etching mask. The parts of material are protected by this etching mask. Either wet
(chemical) or dry (physical) etching can be used to remove the unmasked material. To
perform etching in all directions at same time, isotropic etching will be used. Anisotropic
etching is faster in one direction. Wet etching is isotropic, but the etching time control is
difficult. Wet etching uses liquid solvents for removing materials. It is not suited to transfer
pattern with submicron feature size. It does not damage the material. Dry etching uses gases
to remove materials. It is strongly anisotropic. But it is less selective. It is suited to transfer
pattern having small size. The remaining photo resist is finally removed using additional
chemicals or plasma. Then the wafer is inspected to make sure that the image is transferred
from mask to the top layer of wafer.
Doping
To alter the electrical character of silicon, atom with one less electron than silicon such
as boron and atom with one electron greater than silicon such as phosphorous are introduced
into the area. The P-type (boron) and N-type (phosphorous) are created to reflect their
conducting characteristics. Diffusion is defined as the movement of impurity atoms in
semiconductor material at high temperature.
Atomic diffusion
In this method p and n regions are created by adding dopants into the wafer. The wafers
are placed in an oven which is made up of quartz and it is surrounded with heating elements.
Then the wafers are heated at a temperature of about 1500-2200°F. The inert gas carries the
dopant chemical. The dopant and gas is passed through the wafers and finally the dopant will
get deposited on the wafer. This method can only be used for large areas. For small areas it
will be difficult and it may not be accurate.
 Ion implantation
This is also a method used for adding dopants. In this method, dopant gas such as
phosphine or boron trichloride will be ionized first. Then it provides a beam of high energy
dopant ions to the specified regions of wafer. It will penetrate the wafer. The depth of the
penetration depends on the energy of the beam. By altering the beam energy, it is possible to
control the depth of penetration of dopants into the wafer. The beam current and time of
exposure is used to control the amount of dopant. This method is slower than atomic diffusion
process. It does not require masking and this process is very precise. First it points the wafer
that where it is needed and shoot the dopants to the place where it is required.
Metallization
It is used to create contact with silicon and to make interconnections on chip. A thin
layer of aluminum is deposited over the whole wafer. Aluminium is selected because it is a
good conductor, has good mechanical bond with silicon, forms low resistance contact and it
can be applied and patterned with single deposition and etching process.
Making successive layers: - The process such as masking, etching, doping will be repeated for
each successive layers until all integrated chips are completed. Between the components,
silicon dioxide is used as insulator. This process is called chemical vapor deposition. To make
contact pads, aluminum is deposited. The fabrication includes more than three layers separated
by dielectric layers. For electrical and physical isolation, a layer of solid dielectric is
surrounded in each component which provides isolation. It is possible to fabricate PNP and
NPN transistor in the same silicon substrate. To avoid damage and contamination of circuit,
final dielectric layer (passivation) is deposited. After that, the individual IC will be tested for
electrical function. Check the functionality of each chip on wafer. Those chips are not passed
in the test will be rejected.
Assembly and packaging
Each of the wafers contains hundreds of chips. These chips are separated and packaged
by a method called scribing and cleaving. The wafer is similar to a piece of glass. A diamond
saw cut the wafer into single chips. The diamond tipped tool is used to cut the lines through
the rectangular grid which separates the individual chips. The chips that are failed in electrical
test are discarded. Before packaging, remaining chips are observed under microscope. The
good chip is then mounted into a package. Thin wire is connected using ultrasonic bonding. It
is then encapsulated for protection. Before delivered to customer, the chip is tested again. There
are three configurations available for packaging. They are metal can package, ceramic flat
package and dual in line package. For military applications, the chip is assembled in ceramic
packages. The complete integrated circuits are sealed in anti-static plastic bags.
Representation of Different Elements

N-MOS FABRICATION
Step-I:- A thin wafer cut from pure silicon crystal into which P-Type impurities are introduced.

Step-2:- A layer of 𝑆𝑖𝑂2 is deposited all over the surface of the Silicon wafer. 𝑆𝑖𝑂2 is used to
protect the wafer surface & provides insulation on to which other layers may be deposited &
patterned.

Step-3:- The surface is covered with photo resist which is deposited on silicon wafer.
Step-4:- The photoresist layer is then exposed to ultraviolet light through a mask which defines
those regions into which diffusion is to take place together with transistor channels.

Step-5:- The areas exposed to UV light gets harden & the remaining areas gets unaffected. The
unaffected areas are etched away together with 𝑆𝑖𝑂2 layer, so that the wafer surface is exposed
for diffusion.

Step-6:- A thin layer of 𝑆𝑖𝑂2 layer is grown over the entire surface & polysilicon metal is
deposited on the top of 𝑆𝑖𝑂2 layer to form gate structure. A photoresist is deposited over the
entire the polysilicon layer and expose UV light through the mask2.

Step-7:- The thin oxide is removed to expose the areas into which the impurities are to be
diffused to form drain & source. Diffusion is achieved by heating the wafer to a high
temperature and passing a gas containing the desired n-type impurity.
Step-8:- A Thick oxide 𝑆𝑖𝑂2 is grown all over the surface and photoresist material is placed
on it. Expose the UV light through mask-3 on the selected areas of the polysilicon gate, drain
and source areas and etched to create the contact cuts.

Step-9:- The whole chip is deposited with the metal over the surface to a thickness of 1µm to
form required connections.

The final NMOS structure is

Summary of N-Mos Fabrication:-

Mask-1: - Pattern 𝑆𝑖𝑂2 to expose silicon surface where diffusion layers & their path, drain &
source, gate arrays are required. This mask is called thin ox mask or diffusion mask.
Mask-2: - Pattern ion implantation where depletion mode devices are to be produced. This is
called self-aligning mask.
Mask-3: - Deposit polysilicon overall the surface & then patterned. Diffuse 𝑁 + regions into
the areas where thin oxide has been removed. Transistor drain & source are self aligned with
respect to gate structure.
Mask-4:- Grow thick oxide & then etch for contacts.
Mask-5: - Deposit the metal & patterned.
Mask-6: - Required for over glassing process.
 PMOS FABRICATION
STEP 1: -
A thin layer of silicon wafer is convernted into N-type material by doping with Phosphorous
material.
STEP 2: -
A thick of layer of silicon dioxide(sio2) is grown on entire p-type substrate.
STEP 3: -
The surface is now covered with a photoresist which is deposited over the thick layer of sio2.
Step 4: -
The photoresist layer is then exposed to ultraviolet light through a mask which defines those
regions into which diffusion is to take place together with transistor channels.
Step 5: -
These areas are etched away together with the underlying silicon dioxide so that the wafer
surface is exposed in the window defined by the mask.
Step 6: -
The remaining photoresist is removed and a thin layer of Si02 (0.1 micro meter typical) is
grown over the entire chip surface and then polysilicon is deposited on top of this to form the
gate structure. A photoresist is deposited over the entire the polysilicon layer and expose UV
light through the mask2
Step 7: -
Diffusion is achieved by heating the wafer to a high temperature and passing a gas containing
the desired P-type impurity (for example, Boron).
Note: The polysilicon has an underlying thin oxide which acts as a mask during diffusion. This
is called self-aligning.
Step 8: -
A Thick oxide (Si02) of 1(micro meter) thickness is grown over all and photoresist material is
placed on it. Expose the UV light through mask-3 on the selected areas of the polysilicon gate,
drain and source areas are etched to create the contact cuts.
Step 9: -
Now a metal (aluminum) is deposited over its surface of 1(micro meter) thickness. Again a
photo resist material is grown all over the metal and Expose the UV light through mask-4 are
etched to from the required interconnection pattern.
The final structure of the PMOS is

CMOS FABRICATION
The CMOS can be fabricated using different processes such as
1. P-well Process.
2. N-well Process.
3. Twin Tub Process.
4. Silicon On Insulator (SOI)

P-well Process
1. P-Well Process starts with N-Substrate which is deposited with 𝑆𝑖𝑂2 through Oxidation
Process. The 𝑆𝑖𝑂2 layer is subjected to photolithography process to provide required area for
P-Well. The P-Type impurities are diffused into N-Substrate through the exposed region to
form P-Well.

2. The alignment of gate of c-mos transistor is preferred whose gate regions are formed before
the formation of source & drain regions using ion implantation. The poly silicon is used to form
gate structure using chemical deposition process.
3. The P-Type impurities are diffused into N-Substrate to form P-Mos Transistor through
mask.

4. The N-Type impurities are diffused into P-Well to form N-Mos Transistor through mask.

5. Final structure of C-Mos transistor in P-Well process is

N-well Process
1. N-Well Process starts with P-Substrate which is deposited with 𝑆𝑖𝑂2 through Oxidation
Process. The 𝑆𝑖𝑂2 layer is subjected to photolithography process to provide required area for
P-Well. The N-Type impurities are diffused into P-Substrate through the exposed region to
form N-Well.
2. The alignment of gate of c-mos transistor is preferred whose gate regions are formed
before the formation of source & drain regions using ion implantation. The poly silicon is
used to form gate structure using chemical deposition process.

3. The P-Type impurities are diffused into N-Well to form P-Mos Transistor through mask.

4. The N-Type impurities are diffused into P-Substrate to form N-Mos Transistor through
mask.

5. Final structure of C-Mos transistor in N-Well Process is

 TWIN TUB PROCESS
In this process both N-Well & P-Well for N-Mos & P-Mos transistors respectively are formed
on the same substrate.
The main advantage of this process is
Provide separate optimization of the n-type and p-type transistors.
Making it possible for threshold voltage , body effect parameters and the
transconductance are independently optimized.
This is done through a lightly doped epitaxial layer which is deposited or grown on the
substrate.

Steps: -
1. N or P type substrate is taken initially.
2. Lightly doped Epitaxial layer is deposited above N or P type substrate.
i. Electrical properties of this layer is fixed by dopant and its concentration
ii. The main aim of this step is to deposit high purity silicon layer.
N-well formation.
i. A thick layer of 𝑆𝑖𝑂2 is grown over the substrate and photo resist is grown over it.
ii. Apply the masking procedure where the N - well is created
iii. Etching process is involved to remove a thick layer of 𝑆𝑖𝑂2 where it requires N-
Well.
iv. Ion implantation is occurred with phosphorous element to create the N-Well.
P-Well Formation.
i. A thick layer of 𝑆𝑖𝑂2 is grown over the substrate and photo resist is grown over it.
ii. Apply the masking procedure where the P - well is created
iii. Etching process is involved to remove a thick layer of 𝑆𝑖𝑂2 where it requires P-
Well.
iv. Ion implantation is occurred with Boron element to create the P-Well.
5. A thin layer of 𝑆𝑖𝑂2 is deposited over it.
6. A polysilicon material is grown all over the surface.
7. Polysilicon gates are formed for N-well and P-well by using the masking procedure.
8. P diffusion is formed in N-well and N diffusion is formed in P- well
9. Metallization process is done to create the interconnection at G, S, D, SUB of P and N-well.
 Silicon on insulator (SOI)
Instead of silicon as substrate, to improve the process characteristics such as latch-up and
speed, an insulating substrate was designed.
The SOI Cmos process have different advantages which includes
Closure packing of P & N Mos Transistors.
Absence of Latch-up problems.
Lower parasitic substrate capacitances.
In SOI Process a thin layer of single crystal silicon is epitaxially grown on an insulator &
various masking, doping technologies are applied to form P & N devices. SOI refers to placing
a thin layer of silicon on top of an insulator such as silicon oxide or glass. The transistors will
be built on top of this thin layer of SOI.

Advantages of SOI Technology

1. Due to the absence of N & P Wells, dense transistor structures are formed.
2. Lower substrate capacitances provide the possibility for fast circuits.
3. No field inversion problems exist.
4. There is no conducting substrate which reduces the body effect.
5. Since there exists isolation for P & N Mos transistors
The latch-up condition is removed.
Radiation tolerance is increased.

SOI Fabrication Steps

Step-1: - A thin film of very lightly doped n-type Silicon is grown over an insulator, Sapphire
(Aluminium Oxide – 𝐴𝑙2 𝑂3) or 𝑆𝑖𝑂2 is commonly used insulator.

Step-2: - The etching process is used to etch the silicon except where N & P regions are
required.
Step-3: - The P-Diffusion areas (P-Islands) are formed by masking the N-Islands with a
Photoresist. P-Type impurities are implanted to form the P-Islands. These P-Islands will
become N-Channel devices.

Step-4: - The P-Islands are covered with Photo resist & N-Type dopants are implanted which
forms the N-Islands. These serve as P-Channel devices.

Step-5: - A thin gate oxide is grown all over the surface to act as insulation for gate terminal.

Step-6:- The polysilicon is deposited & patterned over the oxide. This defines the polysilicon
layer to act as gate structure.

Step-7: - In the P-Island, N-Doped source & drain of N-Channel device is grown and implanted
by covering N-Island with photoresist.
Step-8: - In the N-Island, P-Doped source & drain of P-Channel device is grown and implanted
by covering P-Island with photoresist.

Step-9:- A layer of phosphorus glass or some other insulator such as silicon dioxide is then
deposited over the entire structure. The glass is etched as contact–cut locations. The
metallization layer is formed using aluminium over the entire surface and etching it to leave
only the desired metal wires. The aluminium will flow through the contact cuts to make contact
with the diffusion or polysilicon regions.

Bi-CMOS Technology
Bi-CMOS transistor is combination of BJT & CMOS. The CMOS is used for generating
the logic & BJT is placed at the output to increase the fanout. The BJT is able to produce high
output currents. So, the use of buffers and tristate devices at the output in CMOS logic are
removed.
The advantages of Bi-Polar over the CMOS Logic are
• Higher switching speed
• High gain & output currents.
• Better noise performance & high frequency characteristics
• Improved I/O speed applications.
The advantages of CMOS over the Bi-Polar Logic are
• Higher noise margin
 • Lower static power consumption
• High packaging density
• High yield with large complex applications.
On combining Bi-Polar & CMOS i.e Bi-CMOS Technology is designed. In this
technology CMOS logic is used for functional behaviour & Bi-Polar totem pole configuration
with high output current is used for loads connected at the output.
The advantages are
• Improved speed when compared to CMOS Technology.
• Lower power consumption when compared to BJT.
• More compatible I/O which is suitable for TTL, ECL …
• Latch-up immunity is increased.
• Increased performance compared to both CMOS & BJT.
The disadvantages are extra processing steps are required which are more complex. So the
fabrication cost is very high.

Bi-CMOS Fabrication
For fabricating the Bi-CMOS transistor there is difficulty in extending the fabrication
to include BJT & MOS transistor on the same substrate. The production of NPN transistor with
high performance can be achieved by extending N-Well CMOS processing to include extra
steps to add two additional layers
• 𝑛+ Sub-Collector.
• 𝑝+ base layers.
The NPN transistor is formed in N-Well & additional 𝑝+ base region is located in the
N-Well to form base region. The second layer called buried 𝑛+ sub collector (BCCD) layer is
added to reduce N-Well resistance which improves the quality of BJT.
 MOS Transistor Switches
A MOS transistor is a voltage-controlled resistance. The input at the gate controls the
flow of current between drain and source. This MOS transistors can be modelled as electrical
control switches depending on gate voltage.
For a switch LOGIC-1 is a high voltage which is normally 𝑉𝐷𝐷 .
For a switch LOGIC-0 is a low voltage which is normally 𝑉𝑠𝑠 .

For a NMOS Switch, the switch is closed or ON when the source & drain are connected.
This occurs when there is logic ‘1’ on gate terminal and logic ‘0’ on the gate ensures open or
OFF.
NMOS switch is perfect when a ‘0’ is to be passed. (Strong 0)
NMOS switch is imperfect while passing a’1’. (Weak 1)
 For a PMOS Switch, the switch is closed or ON when the source & drain are connected.
This occurs when there is logic ‘0’ on gate terminal and logic ‘1’ on the gate ensures open or
OFF.
PMOS switch is imperfect when a ‘0’ is to be passed. (Weak 0)
PMOS switch is perfect while passing a’1’. (Strong 1)

Note: - NMOS switch produces a STRONG ‘0’ & PMOS switch produces STRONG ‘1’.
By combining PMOS & NMOS in parallel a transmission gate switch is produced.

When A= ‘1’, both the transistors are ON and input is passed to output. It produces STRONG
‘0’ & STRONG ‘1’.
By combining PMOS & NMOS in series a CMOS gate switch is produced.
When Vin= ‘1’, NMOS transistor is ON, Vout= ‘0’. When Vin= ‘0’, PMOS transistor is ON,
Vout= ‘1’.
If two N-Switches are placed in series, an AND gate is generated.
If two P-Switches are placed in series, an NOR gate is generated.

If two N-Switches are placed in parallel, an OR gate is generated.

If two P-Switches are placed in parallel, a NAND gate is generated.

MOS DESIGN EQUATIONS

Ids vs Vds RELATIONSHIPS
The concept of MOS transistors depends on Gate Voltage which induces the charge in the
channel between source & drain. The induced charges in the channel causes to move from
source to drain under the influence of 𝑉𝑑𝑠 . The charge induced depends on 𝑉𝑔𝑠 and 𝐼𝑑𝑠 depends
on both 𝑉𝑔𝑠 and 𝑉𝑑𝑠 . The charge induced is 𝑄𝑐 in the channel.
𝑄𝑐
∴ The current 𝐼𝑑𝑠 = where 𝜏 is Transit time of electron in channel.
𝜏
𝐿
The electron transit time 𝜏 = 𝑣

The electron velocity 𝑣 = 𝜇𝐸𝑑𝑠

where 𝜇 𝑖𝑠 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛 𝑚𝑜𝑏𝑖𝑙𝑖𝑡𝑦
𝑉𝑑𝑠
𝐸𝑑𝑠 𝑖𝑠 𝑒𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝐹𝑖𝑒𝑙𝑑 𝑏𝑦 𝑉𝑑𝑠 =
𝐿
𝐿 𝐿 𝐿2
𝜏= = = − − − − − −→ (1)
𝑣 𝜇 𝑉𝑑𝑠 𝜇𝑉𝑑𝑠
𝐿
Case-1: - Non-Saturated Region
The charge induced in the channel is due to the voltage difference between the gate and
channel. i.e 𝑉𝑔𝑠 . The voltage along the channel varies with the distance from source and since
𝑉𝑑𝑠
the device is not saturated, the voltage variation is approximately equal to .
2

The effective gate voltage 𝑉𝑔 = 𝑉𝑑𝑠 − 𝑉𝑡 .

𝑄
Since the flux density 𝐷 = 𝜖𝐸 = 𝐴
𝑄𝑐
∴ 𝜖𝑖𝑛𝑠 𝜖0 𝐸𝑔 = ⟹ 𝑸𝒄 = 𝝐𝒊𝒏𝒔 𝝐𝟎 𝑾𝑳𝑬𝒈 → (2)
𝑊𝐿
𝑉 𝑉
𝑉𝑔 − 𝑑𝑠 (𝑉𝑔𝑠 −𝑉𝑡 )− 𝑑𝑠
2 2
The electric field 𝐸𝑔 = =
𝐷 𝐷
𝑉
(𝑉𝑔𝑠 −𝑉𝑡 )− 𝑑𝑠
2
The charge induced 𝑄𝑐 = 𝜖0 𝜖𝑖𝑛𝑠 𝑤𝐿 𝐷
𝑉𝑑𝑠
(𝑉𝑔𝑠 −𝑉𝑡 )− 2
𝑄𝑐 𝝐𝟎 𝝐𝒊𝒏𝒔 𝒘𝑳
𝐷
The current 𝐼𝑑𝑠 = = 𝐿2
𝜏
𝜇𝑉𝑑𝑠

𝝐𝟎 𝝐𝒊𝒏𝒔 𝑤 𝑉𝑑𝑠
𝐼𝑑𝑠 = 𝜇 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]𝑉
𝐷 𝐿 2 𝑑𝑠
𝝐𝟎 𝝐𝒊𝒏𝒔
Let 𝑘 = 𝜇
𝐷
𝑤 𝑉𝑑𝑠
∴ 𝐼𝑑𝑠 = 𝑘 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]𝑉
𝐿 2 𝑑𝑠
𝑤
Let 𝛽 = 𝑘 𝐿

𝑉𝑑𝑠 2
∴ 𝐼𝑑𝑠 = 𝛽 [(𝑉𝑔𝑠 − 𝑉𝑡 )𝑉𝑑𝑠 − ]
2
𝝐𝟎 𝝐𝒊𝒏𝒔 𝒘𝑳 𝝐𝟎 𝝐𝒊𝒏𝒔 𝒘𝑳𝝁 𝑤𝐿
The gate capacitance 𝐶𝑔 = = =𝑘
𝐷 𝐷𝜇 𝜇
 𝐶𝑔 𝜇
∴𝑘=
𝑤𝐿
𝑤 𝐶𝑔 𝜇 𝑤 𝐶𝑔 𝜇
∵𝛽=𝑘 = ( )= 2
𝐿 𝑤𝐿 𝐿 𝐿
𝑪𝒈 𝝁 𝑽𝒅𝒔 𝟐
∴ 𝑰𝒅𝒔 = [(𝑽 𝒈𝒔 − 𝑽 𝒕 )𝑽 𝒅𝒔 − ]
𝑳𝟐 𝟐
𝐶𝑔
The gate capacitance per unit area 𝐶0 = 𝑤𝐿

𝐶𝑔 = 𝐶0 wL
𝐶0 𝑤𝐿𝜇 𝑉𝑑𝑠 2
⟹ 𝐼𝑑𝑠 = [(𝑉𝑔𝑠 − 𝑉𝑡 )𝑉𝑑𝑠 − ]
𝐿2 2
𝑪𝟎 𝒘𝝁 𝑽𝒅𝒔 𝟐
∴ 𝑰𝒅𝒔 = [(𝑽𝒈𝒔 − 𝑽𝒕 )𝑽𝒅𝒔 − ]
𝑳 𝟐
Case-2: - Saturation Region
The saturation region starts with 𝑉𝑑𝑠 = 𝑉𝑔𝑠 − 𝑉𝑡
2 2
𝐶0 𝑤𝜇 2 (𝑉𝑔𝑠 − 𝑉𝑡 ) 𝐶0 𝑤𝜇 (𝑉𝑔𝑠 − 𝑉𝑡 )
∴ 𝐼𝑑𝑠 = [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]= ( )
𝐿 2 𝐿 2
2 2
2 (𝑉𝑔𝑠 − 𝑉𝑡 ) (𝑉𝑔𝑠 − 𝑉𝑡 )
∴ 𝐼𝑑𝑠 = 𝛽 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ] = 𝛽( )
2 2
2 2
𝐶𝑔 𝜇 2 (𝑉𝑔𝑠 − 𝑉𝑡 ) 𝐶𝑔 𝜇 (𝑉𝑔𝑠 − 𝑉𝑡 )
∴ 𝐼𝑑𝑠 = 2 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ]= 2 ( )
𝐿 2 𝐿 2

There is no 𝑉𝑑𝑠 term in the current 𝐼𝑑𝑠 in saturation region which indicates the current is
independent of 𝑉𝑑𝑠 .
 Threshold Voltage
The gate structure of MOS transistor consists of charges stored in the dielectric layer
and in the substrate and at the interface. The threshold voltage 𝑉𝑇 is the sufficient voltage to
neutralize these charges and to ON the inversion due to Electric Field 𝐸𝑔 under the gate. 𝑉𝑇 is
the minimum voltage required to invert the charge under the gate to establish a channel from
source to drain.
The equation for threshold voltage is 𝑉𝑇 is
𝑄𝐵 − 𝑄𝑠𝑠
𝑉𝑇 = ∅𝑚𝑠 + 2∅𝑓𝑁
𝐶0
Where 𝑄𝐵 = 𝑐ℎ𝑎𝑟𝑔𝑒 𝑝𝑒𝑟 𝑢𝑛𝑖𝑡 𝑎𝑟𝑒𝑎 𝑏𝑒𝑙𝑜𝑤 𝑡ℎ𝑒 𝑜𝑥𝑖𝑑𝑒 𝑙𝑎𝑦𝑒𝑟.
𝑄𝑠𝑠 = 𝑐ℎ𝑎𝑟𝑔𝑒 𝑑𝑒𝑛𝑠𝑖𝑡𝑦 𝑎𝑡 𝑠𝑖: 𝑠𝑖𝑂2 𝑖𝑛𝑡𝑒𝑟𝑓𝑎𝑐𝑒.
𝐶0 = 𝑔𝑎𝑡𝑒 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒 𝑝𝑒𝑟 𝑢𝑛𝑖𝑡 𝑎𝑟𝑒𝑎.
∅𝑚𝑠 = 𝑤𝑜𝑟𝑘 𝑓𝑢𝑛𝑐𝑡𝑖𝑜𝑛 𝑏𝑒𝑡𝑤𝑒𝑒𝑛 𝑔𝑎𝑡𝑒 𝑠𝑖𝑙𝑖𝑐𝑜𝑛 𝑠𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒
∅𝑓𝑁 = 𝑓𝑒𝑟𝑚𝑖 𝑙𝑒𝑣𝑒𝑙 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙 𝑏𝑒𝑡𝑤𝑒𝑒𝑛 𝑖𝑛𝑣𝑒𝑟𝑡𝑒𝑑 𝑠𝑢𝑟𝑓𝑎𝑐𝑒 & 𝑏𝑢𝑙𝑘 𝑠𝑖𝑙𝑖𝑐𝑜𝑛.
For perfect working of MOS transistor, the source and substrate are to be at same
potential. If source and substrate are not at the same voltage because of the interconnections,
the internal parameters of MOS transistors are changed. Generally, the threshold voltage is
affected if the source and substrate are at different potentials. The work function ∅𝑚𝑠 is –ve &
almost negligible.
𝑄𝐵 −𝑄𝑠𝑠
So, the magnitude and sign of threshold voltage depends on and ∅𝑓𝑁 for any
𝐶0

MOS transistor.

𝑄𝐵 = √2𝜖0 𝜖𝑠𝑖 𝑞𝑁(2∅𝑓𝑁 + 𝑉𝑠𝐵 )

 𝐾𝑇 𝑁
The fermi level ∅𝑓𝑁 = ln 𝑛
𝑞 𝑖

𝑄𝑠𝑠 = (1.5 𝑡𝑜 8) × 10−6 𝑐⁄𝑚2

Where 𝑞 = 𝑐ℎ𝑎𝑟𝑔𝑒 𝑜𝑓 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛

𝑁 = 𝐶𝑜𝑛𝑐𝑒𝑛𝑡𝑟𝑎𝑡𝑖𝑜𝑛 𝑜𝑓 𝑖𝑚𝑝𝑢𝑟𝑖𝑡𝑖𝑒𝑠 𝑖𝑛 𝑡ℎ𝑒 𝑠𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒.
𝑛𝑖 = 𝑇ℎ𝑒 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛 𝐶𝑜𝑛𝑐𝑒𝑛𝑡𝑟𝑎𝑡𝑖𝑜𝑛
𝐾 = 𝐵𝑜𝑙𝑡𝑧𝑚𝑎𝑛 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡.
𝑇 = 𝑇𝑒𝑚𝑝𝑒𝑟𝑎𝑡𝑢𝑟𝑒
𝑉𝑠𝐵 = 𝑆𝑜𝑢𝑟𝑐𝑒 𝑡𝑜 𝑠𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒 𝑏𝑖𝑎𝑠 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
In general, the threshold voltage is
𝐷 1
𝑉𝑇 = 𝑉𝑡 (0) + √2𝜖0 𝜖𝑠𝑖 𝑞𝑁(𝑉𝑠𝐵 )2
𝜖0 𝜖𝑖𝑛𝑠

Body Effect
During the operation of MOS transistor the source & substrate are maintained at same
potential. If due to interconnections the source & substrate are not maintained at same potential
then the MOS transistor will have different characteristics.

Since the source and substrate are not at the same potential the depletion region formed
below the gate increases. As the substrate becomes more negative more holes are attracted to
the substrate leaving a large negatively charged ions behind the gate i.e the depletion region
becomes wider. The threshold voltage is a function of total charge in the depletion region.
Thus, as the substrate voltage decreases the depletion charges increases which increases the
threshold voltage. This is called BODY EFFECT. Body effect refers to the change in the
transistor threshold voltage resulting from a voltage difference between the transistor source
and body. It is also knowing as Back gate effect.
 Transconductance (𝒈𝒎 ) & Output Conductance (𝒈𝒅𝒔 )
The Transconductance 𝑔𝑚 is the ratio of output current to input voltage.
𝛿𝐼𝑑𝑠
𝑔𝑚 = /𝑉𝑑𝑠 = 𝑘
𝛿𝑉𝑔𝑠

𝑄𝑐 𝛿𝑄𝑐
To calculate 𝑔𝑚 , Consider 𝐼𝑑𝑠 = ⇒ 𝛿𝐼𝑑𝑠 =
𝜏 𝜏𝑑𝑠

𝐿2 𝜇𝑉𝑑𝑠 𝛿𝑄𝑐
∵ 𝜏𝑑𝑠 = ⟹ 𝛿𝐼𝑑𝑠 = → (1)
𝜇𝑉𝑑𝑠 𝐿2
The charge induced 𝑄𝑐 = 𝐶𝑔 𝑉𝑔𝑠 ⟹ 𝛿𝑄𝑐 = 𝐶𝑔 𝛿𝑉𝑔𝑠
𝜇𝑉𝑑𝑠 𝐶𝑔 𝛿𝑉𝑔𝑠
∴ 𝛿𝐼𝑑𝑠 =
𝐿2
𝛿𝐼𝑑𝑠 𝜇𝐶𝑔
𝑔𝑚 = = 2 𝑉𝑑𝑠
𝛿𝑉𝑔𝑠 𝐿
𝜇𝐶𝑔
In saturation region, 𝑔𝑚 = (𝑉𝑔𝑠 − 𝑉𝑡 )
𝐿2
𝛿𝐼𝑑𝑠
The output conductance 𝑔𝑑𝑠 =
𝛿𝑉𝑑𝑠

𝑉𝑑𝑠 2
𝐼𝑑𝑠 = 𝛽 [(𝑉𝑔𝑠 − 𝑉𝑡 )𝑉𝑑𝑠 − ]
2
𝛿𝐼𝑑𝑠 𝛽
= 𝛽(𝑉𝑔𝑠 − 𝑉𝑡 ) − (2𝑉𝑑𝑠 )
𝛿𝑉𝑑𝑠 2
= 𝛽(𝑉𝑔𝑠 − 𝑉𝑡 ) − 𝛽𝑉𝑑𝑠
Figure of Merit
It is the measure of frequency response & switching speed of MOS transistors.
𝒈𝒎
Mathematically 𝝎𝟎 = 𝑪𝒈

𝜇𝐶𝑔 𝜇 𝜇
Since 𝑔𝑚 = 𝑉𝑑𝑠 ⟹ 𝜔0 = 𝐿2 𝑉𝑑𝑠 = 𝐿2 (𝑉𝑔𝑠 − 𝑉𝑡 )
𝐿2

The switching speed depends on gate voltage above the threshold voltage, Carrier
mobility and inversely proportional to square of channel length. A fast circuit requires high 𝑔𝑚
thereby figure of merit is very high for high performance circuit. Generally, 𝜇𝑛 > 𝜇𝑝 , therefore
N channel MOSFET has high speed characteristics.
 Channel Length Modulation
The equations which describe the behavior of MOS transistors assumes the channel
length as constant during its operation. These equations also consider the carrier mobility as
constant. As 𝑉𝑑𝑠 increases, the effective channel length decreases when the MOS Device is in
saturation. The variation of channel length ‘L’ with the variation of 𝑉𝑑𝑠 is called Channel
Length Modulation.
Mathematically 𝐿𝑒𝑓𝑓 = 𝐿 − 𝐿𝑠ℎ𝑜𝑟𝑡

𝜖𝑠𝑖
𝐿𝑠ℎ𝑜𝑟𝑡 = √2 {𝑉 − (𝑉𝑔𝑠 − 𝑉𝑡 )}
𝑁𝑞 𝑑𝑠
𝑊
The reduction in channel length increases ratio thereby increasing 𝛽 as the 𝑉𝑑𝑠 increases. In
𝐿

this condition the MOS transistor will have a finite impedance instead of infinite output
2
𝑊 (𝑉𝑔𝑠 −𝑉𝑡 )
impedance. The current value is 𝐼𝑑𝑠 = 𝑘 (1 + 𝜆𝑉𝑑𝑠 ) where 𝜆 is channel length
𝐿 2

modulation factor.

N-MOS INVERTER
An inverter is basic requirement for producing logic circuits. These are required for restoring
the previous logic levels in many devices and sequential devices for NAND & NOR gates. The
basic inverter requires a transistor with source connected to ground and a load resistor
connected from drain to power supply 𝑉𝑑𝑑 . The output is taken from drain & input is connected
to gate and ground.

But a resistor is not conveniently produced on a silicon substrate which occupies a large area
even for small values of resistance. So, some other form of load resistance is required. The
suitable load is depletion mode transistor as shown.
 In the above inverter circuit, depletion mode transistor is pull up transistor & enhancement
mode N-Mos transistor is pull down transistor. For depletion mode transistor, the gate is
connected to source such that it is always in ON Condition since 𝑉𝑔𝑠 = 0. As 𝑉𝑖𝑛 exceeds the
threshold voltage of enhancement mode N-MOS transistor, the current begins to flow and
output decreases. Further increase in 𝑉𝑖𝑛 will cause pull down transistor out of saturation and
becomes resistive.

When 𝑉𝑖𝑛 = 0, the enhancement mode transistor acts as open circuit. So 𝑉𝑜𝑢𝑡 is pulled up
to 𝑉𝑑𝑑 through the depletion mode transistor.

When 𝑉𝑖𝑛 is high, the enhancement mode transistor acts as short circuit. So 𝑉𝑜𝑢𝑡 is pulled
down to ′𝑙𝑜𝑔𝑖𝑐 0′.

𝑉𝑑𝑑
When 𝑉𝑖𝑛 = , both the transistors are in saturation. In this condition 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 .
2

If 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 then the meeting point of input & output is called 𝑉𝑖𝑛𝑣 .
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 = 𝑉𝑖𝑛𝑣 = 0.5𝑉𝑑𝑑
To obtain transfer characteristics of N-Mos Inverter superimpose the characteristic curve of
depletion mode transistor at 𝑉𝑔𝑠 = 0 with the output characteristics of enhancement mode
transistor.
The transfer characteristics of NMOS Inverter is

This curve is shifted by the variation of ratio of pull up to pull down impedance.

Determination of Pull up to Pull down ratio of an inverter driven

by another inverter
Let an inverter driven by another similar inverter.

In order to cascade the inverter without degradation of the voltage levels, the required
𝑉𝑑𝑑
condition is 𝑽𝒐𝒖𝒕 = 𝑽𝒊𝒏 = 𝑽𝒊𝒏𝒗 . At 𝑉𝑖𝑛𝑣 = , both the transistors are in saturation and
2

current flowing is equal in both transistors.

2
𝑤 (𝑉𝑔𝑠 −𝑉𝑡 )
At saturation the current is 𝐼𝑑𝑠 = 𝑘 ( )
𝐿 2

𝑤 (0−𝑉𝑡𝑑 )2
For depletion mode, 𝐼𝑑𝑠 = 𝑘 (
𝐿 2
) → (1)
𝑤 (𝑉𝑖𝑛 −𝑉𝑡 )2
For enhancement mode, 𝐼𝑑𝑠 = 𝑘 (
𝐿 2
) → (2)

For depletion mode transistor 𝑤 = 𝑤𝑝𝑢 , 𝐿 = 𝐿𝑝𝑢

For enhancement mode transistor 𝑤 = 𝑤𝑝𝑑 , 𝐿 = 𝐿𝑝𝑑
𝐿𝑝𝑢 𝐿𝑝𝑑
Let 𝑍𝑝𝑢 = & 𝑍𝑝𝑑 =
𝑤𝑝𝑢 𝑤𝑝𝑑

∵ Both the transistors are in saturation (1) = (2)

𝑤𝑝𝑢 (0 − 𝑉𝑡𝑑 )2 𝑤𝑝𝑑 (𝑉𝑖𝑛 − 𝑉𝑡 )2
𝑘 ( )=𝑘 ( )
𝐿𝑝𝑢 2 𝐿𝑝𝑑 2
 𝑉𝑡𝑑 2 (𝑉𝑖𝑛 − 𝑉𝑡 )2 𝒁𝒑𝒖 𝑽𝒕𝒅 𝟐
= ⟹ =
𝑍𝑝𝑢 𝑍𝑝𝑑 𝒁𝒑𝒅 (𝑽𝒊𝒏 − 𝑽𝒕 )𝟐
The typical values are 𝑉𝑡𝑑 = −0.6𝑉𝑑𝑑 , 𝑉𝑡 = 0.2𝑉𝑑𝑑 & 𝑉𝑖𝑛 = 0.5𝑉𝑑𝑑
𝑍𝑝𝑢 0.36𝑉𝑑𝑑 2 0.36
= = =4
𝑍𝑝𝑑 0.09𝑉𝑑𝑑 2 0.09
𝑍𝑝𝑢 : 𝑍𝑝𝑑 = 4: 1

𝑍𝑝𝑢 −𝑉𝑡𝑑 −𝑉𝑡𝑑

∴√ = ⟹ 𝑉𝑖𝑛 − 𝑉𝑡 =
𝑍𝑝𝑑 𝑉𝑖𝑛 − 𝑉𝑡
𝑍𝑝𝑢
√
𝑍𝑝𝑑

𝑉𝑡𝑑
𝑉𝑖𝑛 = 𝑉𝑡 −
𝑍𝑝𝑢
√
𝑍𝑝𝑑

At saturation,
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 = 𝑉𝑖𝑛𝑣
𝑽𝒕𝒅
∴ 𝑽𝒊𝒏𝒗 = 𝑽𝒕 −
𝒁𝒑𝒖
√
𝒁𝒑𝒅

PASS TRANSISTOR
The pass transistors can be used as switches by the condition of isolated nature of the
gate. When the transistor is in linear or active region, the device acts as a resistance under gate
control unit. In this mode the transistor can be used as ON or OFF switch. MOSFETs can be
used as switches in series with lines carrying logic levels as in the case of relay contacts. Such
kind of logic is known as pass transistor. Pass transistor pass the signal between the drain and
source terminals. When the MOS transistor is used as logical element & input source is placed
at the source or drain which is either ‘0’ or 𝑉𝑑𝑑 & output is taken at drain or source depending
on the control voltage at gate. They require less area and wiring and cannot pass the entire
voltage range. The MOS transistor is used as a switch which is turned OFF by setting 𝑉𝑔𝑠 = 0,
where the channel does not formed & by setting 𝑉𝑔𝑠 = 𝑉𝑑𝑑 , the switch is turned ON and
provides a path to flow a current.
The output 𝑉𝑜𝑢𝑡 is maintained at its previous logic value when the switch is open or its
capacitance C is charged to 𝑉𝑖𝑛 if the gate voltage allows the transistor to be closed forcing a
current for a short period of time. The transistor used with this behaviour is called pass
transistor. The transferring of charge from input to output through the pass transistor is called
charge steering. When a N-Mos transistor is used as pass transistor it does not produce strong
‘1’. When a P-Mos transistor is used as pass transistor it does not produce strong ‘0’. NMOS
is preferred for these applications since the larger electron mobility implies faster switching
than the PMOS.

Determination of Pull up to Pull down ratio of an N-Mos inverter

driven by one or more Pass Transistor
The input of an inverter may come from the output of an inverter after passing through
the series of pass transistors.

In this condition, the connection of pass transistors in series may degrade the logic
levels before reaching the inverter. The reduction of voltage 𝑉𝑡𝑝 , where 𝑉𝑡𝑝 is the threshold
voltage of pass transistor. So, the input to the inverter 2 is 𝑉𝑑𝑑 − 𝑉𝑡𝑝 .
When the input to inverter1 is 𝑉𝑑𝑑 , then the transistor which is enhancement mode (pull
down) is conducting and it is in resistive region of operation. Depletion mode transistor is in
saturation region and can be represented by constant current source. The inverter 1 is
represented as
 𝑉𝑜𝑢𝑡1 = 𝐼𝑑𝑠1 𝑅
𝑤𝑝𝑢1 (−𝑉𝑡𝑑 )2
𝐼𝑑𝑠1 =𝑘 → (1)
𝐿𝑝𝑢1 2
The current through the enhancement mode transistor is

𝑤𝑝𝑑 𝑉𝑑𝑠1 2
𝐼𝑑𝑠(𝑒𝑛ℎ) =𝑘 ((𝑉𝑑𝑑 − 𝑉𝑡 )𝑉𝑑𝑠1 − )
𝐿𝑝𝑑 2

𝑉𝑑𝑠1 𝑉𝑑𝑠1
The resistance R is 𝑅 = = 2
𝐼𝑑𝑠(𝑒𝑛ℎ) 𝑤𝑝𝑑 𝑉
𝑘 ((𝑉𝑑𝑑 −𝑉𝑡 )𝑉𝑑𝑠1 − 𝑑𝑠1 )
𝐿𝑝𝑑 2

1
𝑅=
𝑤𝑝𝑑 𝑉
𝑘 ((𝑉𝑑𝑑 − 𝑉𝑡 ) − 𝑑𝑠1 )
𝐿𝑝𝑑 2
𝑉𝑑𝑠 𝑍𝑝𝑑
Since 𝑉𝑑𝑠 is very small, is negligible. The resistance 𝑅 =
2 𝑘((𝑉𝑑𝑑 −𝑉𝑡 ))

𝑤𝑝𝑢1 (−𝑉𝑡𝑑 )2 𝑍𝑝𝑑 1 𝑍𝑝𝑑 (𝑉𝑡𝑑 )2

𝑉𝑜𝑢𝑡1 = 𝐼𝑑𝑠1 𝑅 = 𝑘 × =
𝐿𝑝𝑢1 2 𝑘((𝑉𝑑𝑑 − 𝑉𝑡 )) 2 𝑍𝑝𝑢 𝑉𝑑𝑑 − 𝑉𝑡
→ (2)
Similarly for inverter 2 is, 𝑉𝑜𝑢𝑡2 = 𝐼𝑑𝑠2 × 𝑅
𝑤𝑝𝑢2 (−𝑉𝑡𝑑 )2
𝐼𝑑𝑠2 =𝑘
𝐿𝑝𝑢2 2
1
𝑅= 𝑤𝑝𝑑2
𝑘 − 𝑉𝑡𝑝 ) − 𝑉𝑡 )
𝐿𝑝𝑑2 ((𝑉𝑑𝑑
𝑤𝑝𝑢2 (−𝑉𝑡𝑑 )2 1
𝑉𝑜𝑢𝑡2 = 𝐼𝑑𝑠2 𝑅 = 𝑘 × 𝑤
𝐿𝑝𝑢2 2 𝑘
𝑝𝑑2
− 𝑉𝑡𝑝 ) − 𝑉𝑡 )
𝐿𝑝𝑑2 ((𝑉𝑑𝑑
1 𝑍𝑝𝑑2 (𝑉𝑡𝑑 )2
= → (3)
2 𝑍𝑝𝑢2 (𝑉𝑑𝑑 − 𝑉𝑡𝑝 ) − 𝑉𝑡
On equating (2) &(3),
1 𝑍𝑝𝑑1 (𝑉𝑡𝑑 )2 1 𝑍𝑝𝑑2 (𝑉𝑡𝑑 )2
=
2 𝑍𝑝𝑢1 𝑉𝑑𝑑 − 𝑉𝑡 2 𝑍𝑝𝑢2 (𝑉𝑑𝑑 − 𝑉𝑡𝑝 ) − 𝑉𝑡
𝑍𝑝𝑢2 𝑍𝑝𝑢1 𝑉𝑑𝑑 − 𝑉𝑡
= ×
𝑍𝑝𝑑2 𝑍𝑝𝑑1 (𝑉𝑑𝑑 − 𝑉𝑡𝑝 ) − 𝑉𝑡
The typical values are 𝑉𝑡 = 0.2𝑉𝑑𝑑 & 𝑉𝑡𝑝 = 0.3𝑉𝑑𝑑
 𝑍𝑝𝑢2 𝑍𝑝𝑢1 𝑉𝑑𝑑 − 0.2𝑉𝑑𝑑
= ×
𝑍𝑝𝑑2 𝑍𝑝𝑑1 (𝑉𝑑𝑑 − 0.3𝑉𝑑𝑑 ) − 0.2𝑉𝑑𝑑
𝑍𝑝𝑢2 𝑍𝑝𝑢1 0.8𝑉𝑑𝑑
= ×
𝑍𝑝𝑑2 𝑍𝑝𝑑1 0.5𝑉𝑑𝑑
𝑍𝑝𝑢2 𝑍𝑝𝑢1
= × 1.6
𝑍𝑝𝑑2 𝑍𝑝𝑑1
𝑍𝑝𝑢2 𝑍𝑝𝑢1
On normalization, = ×2
𝑍𝑝𝑑2 𝑍𝑝𝑑1

𝑍𝑝𝑢1
∵ =4
𝑍𝑝𝑑1
𝑍𝑝𝑢2
∴ =2×4
𝑍𝑝𝑑2
𝒁𝒑𝒖𝟐 : 𝒁𝒑𝒅𝟐 = 𝟖: 𝟏

Bi-CMOS INVERTER
To design a Bi-CMOS Inverter the basic approach requires the full use of advantages,
characteristics of Bi-polar and CMOS technologies. In this approach, the MOS transistors are
used to perform the logic function & the bipolar transistors are placed to drive the output loads.
A simple Bi-CMOS Inverter is designed by using two bipolar transistors in totem pole
configuration and the MOS transistors in enhancement mode are used at the input.

A simple Bi-CMOS inverter as shown in figure. It consists of two bipolar transistors

T1 and T2 with one NMOS transistor T3, and one PMOS transistor T4.
If Vin is at logic ‘0’,
The transistor T3 is OFF which makes the transistor T1 will be non-conducting since
no base current flows. The transistor T4 is ON which supplies current to base of T2 which will
conduct and act as a current source to charge the load capacitance 𝐶𝐿 towards +5 Volts.
If Vin =+5 Volts
The transistor T4 is OFF which makes the transistor T2 will be non-conducting since
no base current flows. The transistor T3 is ON which supplies current to base of T1 which will
conduct and act as a current sink from the load capacitance to discharge 𝐶𝐿 to 0 volts.
Since the BJT has low output impedance the charging & discharging of load
capacitance is very fast.
The advantages are
• The output logic levels will be good.
• The inverter has a high input impedance.
• The inverter has a low output impedance.
• The inverter has a high current drive capability
• The inverter has high noise margins.
In the above inverter circuit, there is no discharge path for the base currents when the
corresponding BJT is in OFF condition. Because of this, the performance of inverter circuit
decreases. So, an alternative improved Bi-CMOS inverter with base current discharge is
designed as shown below:

An improved Bi-CMOS inverter with base current discharge

When the input is either logic 0 or logic 1 , the transistor 𝑇5 & 𝑇6 are providing the
discharge path for the base currents when the transistors 𝑇1 & 𝑇2 are in OFF condition. The
transistors 𝑇5 & 𝑇6 are turned ON respectively to provide the discharge path i.e when 𝑇1 is
turned OFF 𝑇6 provides a discharge path and 𝑇2 is OFF then 𝑇5 provides the discharge path for
the base currents. These Bi-CMOS inverters are suitable where high current sourcing & sinking
is required.

LATCH-UP in CMOS Circuits

In a bulk CMOS structure, a pair of parasitic bipolar transistors are formed. The collector of
each BJT is connected to the base of other (BJT) in a positive feedback structure.
Because of this, the phenomena called latch-up occurs when
• Both the BJT’s are conducting and provides a low resistance path between 𝑉𝑑𝑑 &
ground.
• The product of gains of each transistor in the feedback loops is greater than 1.
• The result of latch-up is a circuit gets malfunctioned or the device gets damaged.

Equivalent circuit of latch-up condition

The latch-up effect begins when the output voltage drops below the ground due to noise
& improper connections. If the sufficient current flows through the 𝑅𝑠𝑢𝑏 which turns NPN
transistor ON and draw a current through the resistance of N-well. This current produces a
voltage drop which turns the PNP transistor to ON thereby a low resistance path between the
power supply and ground is formed. Once latch-up occurs, the only way to reduce the effect is
to reduce the current below a critical level.
To prevent the latch-up in CMOS circuits the steps required in manufacturing are
• The higher substrate doping levels.
• A low resistance contact to the ground.
• A higher doping level for N-well & P-Well.
• To reduce the latch-up the product gain should be reduced in the loop of
parasitic BI-Polar transistors.

ALTERNATE FORMS OF PULL-UP LOADS

Generally, the inverter circuit will have a depletion mode pull-up transistor as its load. But
there are also other configurations. Let us consider four such arrangements.
(i). Load resistance RL: This arrangement consists of a load resistor as a pull-up as shown in
the diagram below.

But it is not widely used because of the large space requirements of resistors produced in a
silicon substrate
ii)N-MOS depletion mode transistor pull-up :
This arrangement consists of a depletion mode transistor as pull-up. The arrangement
and the transfer characteristic are shown below.
In this type of arrangement, we observe
(a) Dissipation is high, since rail to rail current flows when Vin = logical 1.
(b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-down device.
(c) When switching the output from 1 to 0, the pull-up device is non-saturated initially and
this presents lower resistance through which to charge capacitive loads.
iii)N-MOS enhancement mode transistor pull-up :
This arrangement consists of a n-MOS enhancement mode transistor as pull-up. The
arrangement and the transfer characteristic are shown below.

The important features of this arrangement are

(a) Dissipation is high since current flows when Vin =logical 1 (VGG is returned to VDD).
(b) Vout can never reach VDD (logical I) if VGG = VDD as is normally the case.
(c) VGG may be derived from a switching source, for example, one phase of a clock, so that
dissipation can be greatly reduced.
If VGG is higher than VDD then an extra supply rail is required.
iv) Complementary transistor pull-up (CMOS) :
This arrangement consists of a C-MOS arrangement as pull-up. The arrangement and
the transfer characteristic are shown below.

The salient features of this arrangement are

(a) No current flows either for logical 0 or for logical 1 input.
(b) Full logical 1 and 0 levels are presented at the output.
(c) For devices of similar dimensions, the p-channel is slower than the n-channel device.
 CMOS INVERTER
C-Mos inverter is designed by using P-Mos & N-Mos transistors in a complimentary behavior
as shown below:

The operation of C-MOS inverter with respect to logic’0’ and logic’1’ can be explained in two
different cases.
Case-i:-
When the input voltage 𝑉𝑖𝑛 = 0 or 𝑙𝑜𝑔𝑖𝑐 ′0′ , the P-Mos gate terminal is at 𝑉𝑑𝑑 below
the source potential i.e 𝑉𝑔𝑠 = −𝑉𝑑𝑑 . This turns the P-Mos transistor to ON condition which
offers a low resistance path to the load capacitance which is charged up to 𝑉𝑑𝑑 . The N-Mos
transistor is in OFF condition where no current flows.
Case-ii:-
When the input voltage 𝑉𝑖𝑛 = 1 or 𝑙𝑜𝑔𝑖𝑐 ′1′ , the N-Mos transistor is turned ON and
provides a low resistance path to the output. So the load capacitance is discharged to 0v. The
P-Mos transistor is in OFF condition.
Note: In any logic, there is no current from Vdd to ground it consumes a very low power.

The C-MOS inverter will operate in 5 regions with respect to input voltage levels as
shown below:
Region 1 (𝟎 < 𝑽𝒊𝒏 < 𝑽𝒕 ):- In this region the P-Mos transistor is completely ON & N-Mos
transistor is completely OFF. So no current flows through the inverter circuit and the output is
connected to 𝑽𝒅𝒅 .
Region 5 (𝑽𝒅𝒔 − 𝑽𝒕 < 𝑽𝒊𝒏 < 𝑽𝒅𝒅 ):- In this region the N-Mos transistor is completely ON &
P-Mos transistor is completely OFF. So, no current flows through the inverter circuit and the
output are discharged to 0𝑣.
𝑽𝒅𝒅
Region 2 (𝑽𝒕 < 𝑽𝒊𝒏 < ):- In this region the input voltage is increased to a level just above
𝟐

the threshold voltage of N-Mos transistor. The N-Mos transistor conducts and has a large
voltage difference between drain and source & operates in saturation region. The P-Mos
transistor is also conducting but voltage difference is small & operating in non-saturation
region. In this region the inverter circuit draw a small amount of current from 𝑽𝒅𝒅 .
𝑽𝒅𝒅
Region 4 ( < 𝑽𝒊𝒏 < 𝑽𝒅𝒔 − 𝑽𝒕 ):- In this region the conditions are similar to region 2 but
𝟐

the operating regions are reversed. P-Mos transistor has large voltage drop so it operates in
saturation region and the N-Mos transistor has small voltage drop which operates in linear
region. The current flowing from 𝑽𝒅𝒅 to ground is small.
𝑽𝒅𝒅
Region 3 (𝑽𝒊𝒏 = ):- For any circuit most of the energy consumption occurs during
𝟐

switching from one logic to other logic. This region is very unstable where logic levels are
changed very rapidly. This is the region where the inverter exhibits gain & both the devices are
in saturation. The current flow through both the devices is equal and a large amount of current
flows from 𝑉𝑑𝑑 to ground. This region occurs when 𝐼𝑑𝑠𝑛 = −𝐼𝑑𝑠𝑝 . The voltage corresponds to
change from logic ‘1’ to logic ‘0’ corresponds to
𝑽𝒊𝒏 = 𝑽𝒐𝒖𝒕 = 𝟎. 𝟓𝑽𝒅𝒅