MOSFET (I): Fundamentals

⚫ I - V Characteristics
⚫ Cutoff Region
⚫ Linear Region
⚫ Saturation Region (pinch-off region)
⚫ Switch model of nMOSFETs
Reading: Chapter 3.3
Gary Chun Zhao, PhD
Chun.Zhao@xjtlu.edu.cn

Apr 2023
https://www.xjtlu.edu.cn/en/departments/academic-departments/electrical-and-electronic-engineering/staff/chun-zhao
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Ec(O) and electric field direction

SiO2
e SiO2
e
V V
x x
-qV =Ec(O) -qV =Ec(O)
x x

Ec
e Ec
e
EF
EF
3
Energy band diagram: Vg>Vm
Inversion:
Vg Qinv Minority carriers

Vg

+++++++

p-Si

4
Energy band diagram: Vg>Vm
Qm Inversion:
Vg Qinv Minority carriers
QSD x

Qinv

Vg
+++++++

p-Si

5
Energy band diagram: Vg>Vm
Qm Inversion:
Vg Qinv Minority carriers
QSD x
Vg

Qinv +++++++

xd

Ei p-Si
EFM qn EFS
qF
qs
6
 Energy band diagram: Vg>Vm
Qm Inversion:
Vg Qinv Minority carriers
QSD x
As Vg>Vm, EFS Vg
is at the up-half
of the bandgap Qinv +++++++

xd

At the interface
Ei p-Si
EFS Ec EFS
EFM qn
Ei
qF
Ev qs
7
 Energy band diagram: Vg>Vm
Qm Inversion:
Vg Qinv Minority carriers

C/cm2 QSD x
Vg

Qinv +++++++
 ( EF − Ei , surf )  t t
ns = ni exp  
 kT  xd
xd
electrons/cm3

Qinv = q ns t Ei p-Si
EFM qn EFS
qF
qs
8
 Inversion
➢ Weak Inversion: 0<n<F (F < S < 2F)
➢ Strong Inversion: n≥F (S ≥ 2F), electron density at the
interface ≥ hole density in Si bulk.
➢ Vg for strong inversion: VT ‘threshold voltage’.
Vg = VT → s = 2F → n = F → ns = pb
 ( E F − Ei , su rf ) 
ns = ni exp  
 kT 
 − ( E F − Ei ,b u lk ) 
pb = ni exp  
 kT  xd
= NA
 s = F + n
ps  n / ns
2
i

nb = ni2 / p b qn EFS

EFM
Vg>0 qs
qF
9
Voltage drops in a MOS system

VG = VFB + Vox + s

Vg=VT → VT = VFB + Vox + 2F

s = 2F

2qN Ae Si (2F )
Vox = + for p-Si sub.
Cox

2qN De Si 2F for n-Si sub.

Vox = −
Cox
10
 • NMOS: N-channel Metal
nMOSFET Oxide Semiconductor

• L = channel length
W
GATE • W = channel width

“Metal” (heavily
doped poly-Si) DRAIN

SOURCE
• A GATE electrode is placed above (electrically insulated
from) the silicon surface, and is used to control the
resistance between the SOURCE and DRAIN regions
11
 Gate oxide
Consider the current IG (flowing into G) versus VGS :
IG
G D
S
VDS
oxide
VGS +
− +
−
semiconductor

IG
The gate is insulated from
the semiconductor, so there
always zero! is no significant (steady)
VGS gate current.

12
 OUTLINE

⚫ I - V Characteristics
⚫ Cutoff Region
⚫ Linear Region
⚫ Saturation Region (pinch-off region)
⚫ Switch model of nMOSFETs
nMOSFET: VGS<VT

Under zero bias, two back-to-back pn-junctions create a very

high resistive path between source and drain.
Appling a positive bias (VGS) to the gate, creates a depletion
region under the gate (repels mobile holes). The depletion
region is same as the one occurring in a MOS Capacitor.
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 OUTLINE

⚫ I - V Characteristics
⚫ Cutoff Region
⚫ Linear Region
⚫ Saturation Region (pinch-off region)
⚫ Switch model of nMOSFETs
 nMOSFET: VGS>VT

Inversion layer charge expressions are (the surface potential s is 2F ):

Inversion layer charge Qinv = −Cox (VG − VT )
VG Qinv
2qN Ae Si (2F )
Threshold voltage VT = VFB + 2F +
Cox
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 Qinv × W × L = q × n × t × W × L
Inversion layer → Qinv = q n t

⚫ Without gate bias, MOSFET is off because two diodes are

"back-to-back". One of them will be reversely biased. To switch
on, the interfacial region is inverted by applying a gate bias.

⚫ Above a certain gate-to-source voltage (threshold voltage VT),

a conducting layer of mobile electrons is formed at the Si
surface beneath the oxide. These electrons can carry current
between the source and drain.

ID VDS
VG VD _ +
W
n+ n+ t
n-channel
n-channel
p-Si
L
RDS 17
 Electrical Resistance
I V
+ _
W
t
n-channel

V L rL  r  L  (Unit: ohms)
Resistance R  = r = =   
I A tW  t  W 
where r is the resistivity (W•cm)
RS
Lecture 4 Page 35 Negatively

Electrical Conductivity s
charged electron
Direction of
electron drift

When an electric field is applied, current flows due to drift

of mobile electrons and holes:

electron current density: J n = ( − q ) nve = qn n E

hole current density: J p = (+ q ) pvh = qp p E

E
total current density: J = J n + J p = (qn n + qp p ) E
J = sE
conductivity s  qn n + qp p Units: (W•cm)-1
19
Lecture 4 Page 36

Electrical Resistivity r

1 1
r =
s qn n + qp p
1
r for n-type material
qn n
1
r for p-type material
qp p
(Units: ohm•cm)

20
Inversion layer as a resistor
Consider an n-channel:
VDS
ID _
+
W
t
RDS =RS(L/W)
n-channel

L
Qinv
r 1 1 1 VG
Rs = = = = Rs
t st q n ns t  nQinv
where Qinv is the charge per unit area. r  1 = 1
Qinv = q ns t
s qn n + qp p
21
 nMOSFET ID vs. VDS Characteristics
Next consider ID (flowing into D) versus VDS, as VGS is varied:
G ID
D
S
VDS
oxide
VGS +
− +
−
semiconductor

ID
Above “threshold” (VGS > VT):
VGS > VT “inversion layer” of electrons
appears, so conduction
zero if VGS < VT between S and D is possible
VDS Below “threshold” (VGS < VT):
no charge → no conduction
IDS = 0 if VGS < VT
“Cutoff” region: VGS < VT
22
 The MOSFET as a Controlled Resistor
⚫ The MOSFET behaves as a resistor when VDS is low:
➢ Drain current ID increases linearly with VDS
➢ Resistance RDS between SOURCE & DRAIN depends on VGS
▪ RDS is lowered as VGS increases above VT
VDS
ID _
NMOSFET Example: +
VDS
ID =
RDS W
t
VGS = 2 V
VGS =1V>V
} T
RDS=RS(L/W)

L
VDS
VG Rs
Linear or Resistive or ohmic or “Triode” Region: 0 < VDS < VGS − VT

23
 MOSFET as a Controlled Resistor (cont’d)
ID
VDS
Let’s deduce ID from RDS
W
t

V L /W L /W
I D = DS & RDS = Rs ( L / W ) = =
RDS nQinv  C (V − V − VDS )
n ox GS T
2

W VDS average value

ID =  nCox (VGS − VT − )VDS of V(x)
L 2
1
We can make RDS low by
Rs =
• applying a large “gate drive” (VGS − VT) nQinv
• making W large and/or L small
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 OUTLINE

⚫ I - V Characteristics
⚫ Cutoff Region
⚫ Linear Region
⚫ Saturation Region (pinch-off region)
⚫ Switch model of nMOSFETs
 MOSFET as a Controlled Resistor (cont’d)

ID = Cox(W/L)[(VGS - VT)VDS-VDS2/2] (1) for a given VGS

it applies only for the condition VDS<(VGS - VT) (This is called

the ‘below pinch-off condition.’)
ID _V ohmic
DS + ID
non-physical
W
t
ID,sat
n-channel

L
dID/dVDS =Cox (W/L) [(VGS-VT) -VDS]=0
so that VDS,sat = VGS - VT
nCOx W VDS,sat VDS
I D ,sat = (VGS − VT )
2
(2)
2 L
26
 MOSFET as a Controlled Resistor (cont’d)

nCOx W
ID =
2 L
(2(V G − VT )VDS − VDS .
2
) (1) for a given VGS

Note for VDS  VG − VT = VDS ,sat , result is non - p hy sical.

At VDS ,sat , n s,x =L = 0
ohmic
assume that channel curr. ID
is const for VDS  VDS ,sat
ID,sat
nCOx W
I D ,sat = (VGS − VT )2 (2)
2 L
which is called the ‘above pinch-off equation’.
saturated

VDS,sat VDS
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 What is “Pinch off” ?
⚫ For a given VGS, you have a maximum amount of current
you can flow through the channel (regardless of VDS).
⚫ When VDS = VGS - VT the channel is flowing as much
current as it can so we call it pinched off (even though
current continues to flow).
VGS

VDS > VGS - VT

G

D
S

n+ -
VGS - VT
+
n+ Below pinch-off
VDS < VGS - VT

p-Si
28
 What is “Pinch off” ?
⚫ For a given VGS, you have a maximum amount of current
you can flow through the channel (regardless of VDS).
⚫ When VDS = VGS - VT the channel is flowing as much
current as it can so we call it pinched off (even though
current continues to flow).
VGS

VDS > VGS - VT

G

D
S

n+ -
VGS - VT
+
n+ pinch-off point
VDS = VGS - VT

p-Si
29
 What is “Pinch off” ?
⚫ For a given VGS, you have a maximum amount of current
you can flow through the channel (regardless of VDS).
⚫ When VDS = VGS - VT the channel is flowing as much
current as it can so we call it pinched off (even though
current continues to flow).
VGS

VDS > VGS - VT (above pinch-off)

G

D
S

n+ -
VGS - VT
+
n+ pinch-off region

p-Si
30
 What is “Pinch off” ?
⚫ For a given VGS, you have a maximum amount of current
you can flow through the channel (regardless of VDS).
⚫ When VDS = VGS - VT the channel is flowing as much
current as it can so we call it pinched off (even though
current continues to flow).
VGS
ohmic
ID
non-physical
VDS > VGS - VT
G
ID,sat
D
S

- +
n+ VGS - VT n+

p-Si
VDS,sat VDS
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Why “Pinch off” ?
• As VDS increases, the inversion-layer charge density at the drain end
of the channel is reduced; therefore, ID does not increase linearly
with VDS.
• When VDS reaches VGS − VT, the channel is “pinched off” at the drain
end, and ID saturates (i.e. it does not increase with further increases
in VDS).
• In the pinched-off region: Qinv(x) = -Cox[VGS – VT – VDS,sat] = 0
VGS

+
VDS > VGS - VT
– G
I D,sat = nCox
W
(VGS − VT )2
2L
D
S

n+ -
VGS - VT
+
n+ pinch-off region

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 ID vs. VDS or VGS Characteristics
 nCOx W
ID =
2 L
(2(V GS − VT )VDS − VDS
2
). (1) IID
For VDS  VDS ,sat
VGS
nCOx W
I D ,sat = (VGS − VT )2 ( 2)
2 L
The graphs shows ideal charactersitics. The
top graph is the output characteristic, the I V
VDDS
I D
lower one is the transfer characteristic.
Equations (1) and (2) are the simple form
of the design equations. V
VDS
D
The quantity Cox (W/L) =  is the device
constant. The designer can only vary W/L
VVG
so as to change . Other values are fixed VT GS

during the process development.

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 OUTLINE

⚫ I - V Characteristics
⚫ Cutoff Region
⚫ Linear Region
⚫ Saturation Region (pinch-off region)
⚫ Switch model of nMOSFETs
Switch Model of nMOS Transistor
| VGS | Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)

R = VDS / ID

VGS < VT VGS > VT

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 Transistor in Linear Mode VD

Assuming VGS > VT VG

VGS
VDS
S G VS
ID ID
D

n+ - V(x) + n+

x
0 VGS-VT VDS
B
When VDS  VGS – VT : ID = 0 W/L [(VGS – VT)VDS – VDS2/2]
0 = nCox
R = VDS / ID
36
 Transistor in Saturation Mode
Assuming VGS > VT
VGS VDS > VGS - VT
VDS
S G
ID
D ID

n+ - V -V + n+
GS T

Pinch-off
0 VGS-VT VDS
B

When VDS  VGS – VT : ID = (0/2) W/L [(VGS – VT) 2]

The current remains constant (saturates).

R = VDS / ID =?
37
nMOSIC - MOST as a Linear RDS
When VDS  VGS – VT ID

ID = 0 W/L [(VGS – VT)VDS – VDS2/2]

For small VDS, there is a linear

dependence between VDS and ID,
hence 0 VGS-VT VDS

1/RDS = ID/VDS VD
= 0 W/L [(VGS – VT) – VDS/2]
≈ 0 W/L (VGS – VT) RDS
VG

VS
38
 nMOSIC - MOST as a Load
⚫ The use
When V of aload
V resistor
– V (an
: ID
DSlayer)GS
implanted T rather
leads to
0/2) W/L [(VGS – VT) ]
IDlarge
= (structures. 2
⚫ The need to minimise the area of
silicon involved is paramount
(see 1st Lecture). VT
⚫ One method is to use a MOST
( frequently called a MOSFET) VDS-VT VDS
as a load.
⚫ In this case the gate and the drain 0 VGS-VT VDS
are connected together so that
VGS=VDS. The pinch off point
VD
coincides with VGS-VT=VDS-VT.
⚫ The characteristic of the load is
shown. It extends along the drain RDS
axis by an amount VT. S
G

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 nMOSIC - The MOST as a Load
⚫ Problem
Calculate the resistance of a load MOST with an aspect ratio
of 1 when the mobility of the electrons is 1000cm2V-1sec-1 and
the gate capacitance per unit area is 10-2Fm-2. The drain
voltage is VD=5V and the threshold voltage VT= 0.5V.

⚫ Solution
The drain current is
VD
ID = n (W/L) Cox (VG -VT )2/2.

but VG=VD so that

R=VD/ID=…

⚫ R=100W
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nMOSIC - The MOST as a Load
⚫ Problem
Calculate the resistance of a load MOST with an aspect ratio
of 1 when the mobility of the electrons is 1000cm2V-1sec-1
and the gate capacitance per unit area is 10-2Fm-2. The drain
voltage is VD=5V and the threshold voltage VT= 0.5V.

⚫ Solution
The drain current is the same as at the pinch-off point where
ID =(W/2L) Cox (VG -VT)2. VD
but VG=VD so that
ID =(W/2L) Cox (VD -VT)2
ID/VD=1/R= (W/2L) Cox (VD -VT)2/VD
= 0.1*0.5*10-2*4.52/5=0.2025*10-2,
⚫ R=500W

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