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CO&MP UNIT 2 PPT Part 1
CO&MP UNIT 2 PPT Part 1
15 0
3 4095
4
STORED PROGRAM ORGANIZATION
INSTRUCTIONS
Instruction Format
• A computer instruction is often divided into two parts
• Program
– An opcode (Operation Code) that specifies the operation for that
– A sequence of (machine) instructions instruction
• (Machine) Instruction – An address that specifies the registers and/or locations in memory
– A group of bits that tell the computer to perform a specific to use for that operation
operation (a sequence of micro-operation) • In the Basic Computer, since the memory contains 4096 (= 2 12)
• The instructions of a program, along with any words, we needs 12 bit to specify which memory address this
needed data are stored in memory instruction will use
• The CPU reads the next instruction from memory • In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• It is placed in an Instruction Register (IR)
• Since the memory words, and hence the instructions, are 16 bits
• Control circuitry in control unit then translates the long, that leaves 3 bits for the instruction’s opcode
instruction into the sequence of microoperations Instruction Format
necessary to implement it
15 14 12 11 0
I Opcode Address
5
6
Addressing
mode
COMPUTER REGISTERS
ADDRESSING MODES
Registers in the Basic Computer
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the 11 0
address of the operand), (or) PC
Memory
– Indirect address: the address in memory of the address in memory 11 0
4096 x 16
of the data to use AR
Direct addressing Indirect addressing 15 0
0 ADD 457 35 1 ADD 300 IR
22 CPU
15 0 15 0
300 1350
TR DR
457 Operand
7 0 7 0 15 0
1350 Operand
OUTR INPR AC
+ + List of BC Registers
AC AC
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
• Effective Address (EA) AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
– The address, that can be directly used without modification to PC 12 Program Counter Holds address of instruction
access an operand for a computation-type instruction, or as the TR 16 Temporary Register Holds temporary data
target address for a branch-type instruction 7 INPR 8 Input Register Holds input character
8
OUTR 8 Output Register Holds output character
COMMON BUS SYSTEM
COMMON BUS SYSTEM S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
LD INR CLR
using a bus PC 2
LD INR CLR
DR 3
• This gives a savings in circuitry over complete LD INR CLR
LD INR CLR
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
9 Clock
LD 10
16-bit common bus
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto
Input-Output Instructions (OP-code =111, I = 1)
the bus in the high order 4 bit positions
15
1 1 1 1 12 11 I/O operation 0
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus
11 12
BASIC COMPUTER INSTRUCTIONS INSTRUCTION SET COMPLETENESS
Hex Code A computer should have a set of instructions so that the user can
Symbol I=0 I= 1 Description construct machine language programs to evaluate any function that is
AND 0xxx 8xxx AND memory word to AC known to be computable.
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory Instruction Types
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address Functional Instructions:
ISZ 6xxx Exxx Increment and skip if zero
- Arithmetic, logic, and shift instructions
CLA 7800 Clear AC - ADD, CMA, INC, CIR, CIL, AND, CLA
CLE 7400 Clear E
CMA 7200 Complement AC Transfer Instructions:
CME 7100 Complement E
CIR 7080 Circulate right AC and E -Data transfers between the main memory and the processor registers
CIL 7040 Circulate left AC and E
INC 7020 Increment AC - LDA, STA
SPA
SNA
7010
7008
Skip next instr. if AC is positive
Skip next instr. if AC is negative
Control Instructions:
SZA
SZE
7004
7002
Skip next instr. if AC is zero
Skip next instr. if E is zero
- Program sequencing and control
HLT 7001 Halt computer - BUN, BSA, ISZ
INP F800 Input character to AC Input / Output Instructions:
OUT F400 Output character from AC
SKI F200 Skip on input flag - Input and output
SKO F100 Skip on output flag
ION F080 Interrupt on - INP, OUT
IOF F040 Interrupt off 13 14
CONTROL UNIT
• Control unit (CU) of a processor translates from machine
TIMING AND CONTROL
instructions to the control signals for the microoperations Control unit of Basic Computer
that implement them
Instruction register (IR)
• Control units are implemented in one of two ways 15 14 13 12 11 - 0 Other inputs
• Hardwired Control
– CU is made up of sequential and combinational circuits to generate 3x8
decoder
the control signals 7 6543 210
D0
I Combinational
D7 Control Control
T15
– A control memory on the processor contains microprograms that T0
activate the necessary control signals
15 14 . . . . 2 1 0
4 x 16
decoder
• We will consider a hardwired implementation of the control
4-bit
unit for the Basic Computer sequence
counter
Increment (INR)
Clear (CLR)
(SC)
Clock
15
16
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
INSTRUCTION CYCLE
- The SC can be incremented or cleared.
• In Basic Computer, a machine instruction is executed in the
-- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is following cycle:
active. 1. Fetch an instruction from memory
D3T4: SC 0
T0 T1 T2 T3 T4 T0
2. Decode the instruction
Clock
3. Read the effective address from memory if the instruction
T0
has an indirect address
T1
4. Execute the instruction
T2 • After an instruction is executed, the cycle starts again at
T3 step 1, for the next instruction
T4
D3
• Note: Every different processor has its own (different)
instruction cycle
CLR
SC
18
17
T1
IR M[AR], PC PC + 1
T1 S2
T2
T0 S1 Bus Decode Opcode in IR(12-14),
AR IR(0-11), I IR(15)
S0
AR 1 T3 T3 T3 T3
Execute Execute AR M[AR] Nothing
LD input-output register-reference
instruction instruction
PC 2 SC 0 SC 0 Execute T4
memory-reference
instruction
INR
SC 0
IR 5
D'7IT 3: AR M[AR]
LD Clock D'7I'T 3: Nothing
Common bus
19 D7I'T 3: Execute a register-reference instr. 20
D7IT 3: Execute an input-output instr.
REGISTER REFERENCE INSTRUCTIONS MEMORY REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when Symbol Operation
Decoder Symbolic Description
- D7 = 1, I = 0 AND D0 AC AC M[AR]
- Register Ref. Instr. is specified in b0 -- b11 of IR ADD D1 AC AC + M[AR], E Cout
- Execution starts with timing signal T 3 LDA D2 AC M[AR]
r = D7 IT 3 => Register Reference Instruction STA D3 M[AR] AC
Bi = IR(i) , i=0,1,2,...,11 BUN D4 PC AR
BSA D5 M[AR] PC, PC AR + 1
r: SC 0 ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
CLA rB 11: AC 0
CLE rB 10: E0 - The effective address of the instruction is in AR and was placed there during
CMA rB 9: AC AC’ timing signal T 2 when I = 0, or during timing signal T 3 when I = 1
CME rB 8: E E’ - Memory cycle is assumed to be short enough to complete in a CPU cycle
CIR rB 7: AC shr AC, AC(15) E, E AC(0) - The execution of MR instruction starts with T 4
CIL rB 6: AC shl AC, AC(0) E, E AC(15)
INC rB 5: AC AC + 1 AND to AC
SPA rB 4: if (AC(15) = 0) then (PC PC+1) D 0T4: DR M[AR] Read operand
SNA rB 3: if (AC(15) = 1) then (PC PC+1) D 0T5: AC AC DR, SC 0 AND with AC
SZA rB 2: if (AC = 0) then (PC PC+1)
ADD to AC
SZE rB 1: if (E = 0) then (PC PC+1)
D 1T4: DR M[AR] Read operand
HLT rB 0: S 0 (S is a start-stop flip-flop)
D 1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E
21 22
21
AR = 135 135
Subroutine Subroutine
136 PC = 136
D 0T 5 D 1T 5 D 2T 5 AC
AC AC DR AC AC + DR AC DR
SC 0 E Cout SC 0 Transmitter
Keyboard interface INPR FGI
SC 0 INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
BUN BSA ISZ
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
D 4T 4 D 5T 4 D 6T 4
IEN Interrupt enable - 1 bit
PC AR M[AR] PC DR M[ AR]
SC 0 AR AR + 1 - The terminal sends and receives serial information
D 5T 5 D 6T 5
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
PC AR DR DR + 1
SC 0
- INPR and OUTR communicate with the terminal
D 6T 6
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
M[AR] DR
If (DR = 0) difference between I/O device and the computer
25 26
then (PC PC + 1)
SC 0
yes More
Character yes More
Character
no
END no 27 28
END
INTERRUPT INITIATED INPUT/OUTPUT FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt f/f
-Open communication only when some data has to be passed Instruction cycle =0 R =1 Interrupt cycle
Execute IEN =0
- When the interface founds that the I/O device is ready for data instructions
=1 Branch to location 1
PC 1
transfer, it generates an interrupt request to the CPU. =1
FGI
=0
IEN 0
- Upon detecting an interrupt, the CPU stops momentarily the task it is =1
FGO R 0
=0
doing, branches to the service routine to process the data transfer, R1
and then returns to the task it was performing.
- The interrupt cycle is a HW implementation of a branch
* IEN (Interrupt-enable flip-flop) and save return address operation.
- can be set and cleared by instructions - At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- when cleared, the computer cannot be interrupted - At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
29 - The instruction that returns the control to the original
program is "indirect BUN 0" 30
1120 1120
I/O I/O
Program Program
1 BUN 0 1 BUN 0