Design of a Low-Power 12-bit SAR ADC

Mikhail M. Pilipko1, Mikhail E. Manokhin

Peter the Great St.Petersburg Polytechnic University
St. Petersburg, Russia
1
pilipko_mm@spbstu.ru

Abstract—In this paper a 12-bit successive approximation
analog-to-digital converter (ADC) is presented. The circuit is
realized in a standard 1.8 V 180 nm CMOS technology. To avoid
using of an operational amplifier, a passive sample-and-hold
circuit is applied. A capacitor-based digital-to-analog converter
allows for power saving. The ADC has conversion rate of 1 MSps
and the signal-to-noise-and-distortion ratio of 52.1 dB with power
consumption of 53 microwatt. Digital calibration and correction
help to further improve the ADC characteristics.
DAC reset. The sample-and-hold circuit is built of a large
capacitor and a bootstrapped switch [8, 9] that ensures a wide
input range. The circuit of the clocked comparator is realized
similarly to [10]. It contains both n-MOS and p-MOS
differential pairs and a decision circuit, thus being able to
operate with a rail-to-rail input.

Keywords— analog-digital conversion; CMOS technology;

integrated circuit testing; error correction

I. INTRODUCTION
The widespread application of sensor networks and the
transition to the Internet of Things determine increased
requirements to the power consumption of autonomous
sensors. One of the blocks of the sensor structure is an analog-
to-digital converter (ADC). Different types of ADCs are
known [1-4], each being most suitable for certain conversion
Fig. 1. The structure of the SAR ADC.
rates and resolutions. But their power dissipation is highly
dependent on the ADC structure. A comparison of ADCs of For power saving reasons, capacitor-based DACs are
different types [5, 6] shows that successive approximation widely used in the design of SAR ADCs. A binary-weighted
(SAR) ADCs are the most promising type by the criterion of capacitor array occupies a significant chip area. Therefore for
energy efficiency. Design of ADCs with medium resolution structures with resolution of more than 10 bits it is common to
(10-12 bits) and moderate performance (about 1MSps) is an utilize a bridge circuit with two capacitor arrays (Fig. 2) [11].
area of high interest. Most efforts are aimed at ensuring a wide The capacitor array controlled by the more significant bits is
input signal range and the linearity of the transfer function. connected directly to the output node of the DAC. The array
Saving the chip area is also an important design issue. This controlled by the less significant bits is separated from the
paper presents the design of a 12-bit SAR ADC as well as the output node by a bridge capacitor (CB in Fig. 2). The value of
obtained experimental results. the bridge capacitor must be realized very precisely, otherwise
II. THE CIRCUIT OF THE SAR ADC the proportion of one array relative to the other will be broken.
Special placement methods of capacitor array elements exist
The structure of the SAR ADC traditionally contains such which improve the precision of the bridge structure.
blocks as a sample-and-hold circuit, a comparator, a digital-to-
analog converter (DAC), and a digital control circuit (Fig. 1)
[7]. Besides a successive approximation register, the control
circuit includes output buffers that provide the proper circuit
loadability. At each conversion cycle the control circuit seeks
such a code that the output voltage of the DAC is the closest to
the voltage fixed by the sample-and-hold circuit. The DAC
capacitances corresponding to the two most significant bits are
the largest and demand longest time for charging. Giving two
clock periods for determining each of those two bits relaxes the
time requirements and allows increasing the clock rate which
leads to shorter conversion time. Thus in this design, the
conversion cycle takes 16 clock periods: first one for sampling
the input, four for two most significant bits, ten for the rest 10
bits, and the last one for producing the output code and for the Fig. 2. The structure of the 12-bit DAC.

129 978-1-7281-0339-6/19/$31.00 ©2019 IEEE

 Fig. 3. The layout of the ADC core

III. THE LAYOUT OF THE SAR ADC consists of standard ESD components supplied by the foundry.
The ADC was implemented using Cadence Design Systems The input pad is situated as close as possible to the input of the
tools and UMC 180nm 1P6M MM/RF 1.8V CMOS sample-and hold circuit. Digital and analog parts of the circuit
technology. The layout of the 12-bit SAR ADC core is shown are separated by guard rings to suppress the interference of the
in Fig. 3. Capacitor arrays consist of unit capacitors with a digital noise with analog signals.
nominal value of 125fF. The arrays are surrounded by dummy IV. EXPERIMENTAL RESULTS
elements to compensate for the edge effects. The capacitance
corresponding to the k-th and (k+6)-th significant digit consists The ADC die was bonded on a test board (Fig. 5). For
of 4×2k unit capacitors, where k = 0..5. Fig. 4 shows the dynamic measurements, the following equipment was used.
placement of the elements in a quarter of the less significant The input signal was supplied from the Agilent 81150A
array of capacitors, with 0..5 being the corresponding bits, X generator, the clock signal was generated by Agilent 81130A,
being the grounded capacitor (CX in Fig. 2), and D being the output code was acquired by the Agilent 16802A logic
dummy elements. This arrangement of elements allows to analyzer. Measurements were performed at room temperature.
partially compensate for the effect of the systematic error The results were processed in MATLAB. The output spectrum
gradient along the DAC layout. is shown in Fig. 6 (a) for a 1 MHz clock signal and a 13 kHz
1.6 Vpp input signal. Unfortunately, the nonlinearity of the
D D D D D D D D D DAC led to the appearance of a large number of harmonics in
D 4 5 4 5 4 5 4 5 the spectrum and to the degradation of the ADC characteristics.
D 5 2 5 3 5 2 5 3 To improve the performance of the ADC, calibration and
D 4 5 4 5 4 5 1 5 correction were applied. Samples of the output code were
collected while feeding a 1.9 Vpp input sine signal which is
D 5 3 5 0 5 3 5 4 larger than the input range of the ADC. After that, using the
D 4 5 4 5 X 5 4 5 histogram method [12], a lookup table (LUT) was created.
D 5 2 5 3 5 2 5 3 Fig. 6 (b) shows the output spectrum of the ADC after applying
the LUT to the output samples of the 1.6 Vpp sine. Both signal-
D 4 5 1 5 4 5 4 5
to-noise-and-distortion ratio (SNDR) and spur-free dynamic
D 5 3 5 4 5 3 5 4 range (SFDR) were improved by about 4 dB. Such a correction
Fig. 4. A quarter of the less significant array of capacitors. can be realized with the help of an FPGA.

Fig. 3 does not show bondpads and the electrostatic

discharge (ESD) ring surrounding the ADC core. The ring

130

Fig. 5. The test board with the ADC die.
(a)
(b)
Fig. 6. Output spectrum (a) without correction, (b) with LUT correction.
Table I summarizes main characteristics of the designed
chip. Both cases (without correction and with LUT correction)
are listed for comparison. Figure-of-merit (FOM) parameter
characterizes the energy efficiency, i.e. the ratio of power
consumption to clock frequency and to effective resolution, and
appears to be competitive compared to other designs [5, 6].
131
TABLE I. PERFORMANCE SUMMARY OF THE ADC
Parameter Value
Technology 1P6M 180 nm CMOS
Supply voltage 1.8 V
Core size / Chip
0.64 mm × 0.40 mm / 1.17 mm × 0.92 mm
size
Power dissipation 53 μW
Output rate 1 MSps
52.1 dB (no 56.3 dB (LUT
SNDR
correction) correction)
61.2 dB (no 64.9 dB (LUT
SFDR
correction) correction)
FOM 161 fJ 99 fJ
V. CONCLUSION
This paper presents the design of a 12-bit SAR ADC with
a rail-to-rail input range. The ADC was implemented using
a standard 1.8 V 180 nm CMOS technology. A passive sample-
and-hold and a capacitive DAC were utilized for power saving.
The DAC was realized as a bridge structure to save chip area
and to lower the DAC output capacitance. A sample-and-hold
with a bootstrapped switch and a rail-to-rail comparator ensure
a wide input range. The consumed power is 53 μW at a clock
frequency of 1 MHz. The SNDR is 52.1 dB without correction
and 56.3 dB with LUT correction. Thanks to low power
consumption the ADC is suitable for wireless sensor networks.
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