Device Configuration Pins

Table 13–10. Dedicated Cyclone Device Configuration Pins (Part 3 of 3)

User Configuration
Pin Name Pin Type Description
Mode Scheme
DCLK – PS Input (PS) In PS configuration, the clock input clocks data from
AS Output (AS) an external source into the target device. Data is
latched into the FPGA on the rising edge of DCLK. In
AS configuration, DCLK is an output from the Cyclone
FPGA that provides timing for the configuration
interface. After configuration, the logic levels on this
pin do not affect the Cyclone FPGA. This pin uses
Schmitt trigger input buffers
ASDO I/O in PS AS Output Control signal from the Cyclone FPGA to the serial
mode, configuration device in AS mode used to read out
N/A in AS configuration data.
mode
nCSO I/O in PS AS Output Output control signal from the Cyclone FPGA to the
mode, serial configuration device in AS mode that enables
N/A in AS the configuration device.
mode
nCE – All Input Active-low chip enable. The nCE pin activates the
device with a low signal to allow configuration. The
nCE pin must be held low during configuration,
initialization, and user mode. In single device
configuration, tie the nCE pin low. In multi-device
configuration, the first device’s nCE pin is tied low
while its nCEO pin is connected to nCE of the next
device in the chain. Hold the nCE pin low for
programming the FPGA via JTAG. This pin uses
Schmitt trigger input buffers
nCEO – All Output Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds
the next device's nCE pin. The nCEO of the last
device in the chain is left floating.
DATA0 – All Input Data input. In serial configuration mode, bit-wide
configuration data is presented to the target device on
the DATA0 pin. Toggling DATA0 after configuration
does not affect the configured device. This pin uses
Schmitt trigger input buffers

13–48 Altera Corporation

Cyclone Device Handbook, Volume 1 May 2008
 Configuring Cyclone FPGAs

Table 13–11 describes the optional configuration pins. If these optional

configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-ups.

Table 13–11. Optional Cyclone Device Configuration Pins

Pin Name User Mode Pin Type Description

CLKUSR N/A if option is Input Optional user-supplied clock input. Synchronizes the
on, I/O if option is initialization of one or more devices. This pin is enabled by
off turning on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software.
INIT_DONE N/A if option is Output Status pin. Can be used to indicate when the device has
on, I/O if option is open-drain initialized and is in user mode. The INIT_DONE pin must be
off pulled to VCC with a 10-kΩ resistor. The INIT_DONE pin drives
low during configuration. Before and after configuration, the
INIT_DONE pin is released and is pulled to VCC by an external
pull-up resistor. Because INIT_DONE is tri-stated before
configuration, it is pulled high by the external pull-up resistor.
Thus, the monitoring circuitry must be able to detect a low-to-
high transition. This pin is enabled by turning on the Enable
INIT_DONE output option in the Quartus II software.
DEV_OE N/A if the option Input Optional pin that allows the user to override all tri-states on the
is on, I/O if the device. When this pin is driven low, all I/O pins are tri-stated;
option is off. when this pin is driven high, all I/O pins behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
DEV_CLRn N/A if the option Input Optional pin that allows you to override all clears on all device
is on, I/O if the registers. When this pin is driven low, all registers are cleared;
option is off. when this pin is driven high, all registers behave as programmed.
This pin is enabled by turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II software.

Altera Corporation 13–49

May 2008 Cyclone Device Handbook, Volume 1
Referenced Documents

Table 13–12 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions.

Table 13–12. Dedicated JTAG Pins

User
Pin Name Pin Type Description
Mode
TDI N/A Input Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to VC C . This pin
uses Schmitt trigger input buffers
TDO N/A Output Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by leaving this pin unconnected.
TMS N/A Input Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS
is evaluated on the rising edge of TCK. If the JTAG interface is not required on
the board, the JTAG circuitry can be disabled by connecting this pin to VC C . This
pin uses Schmitt trigger input buffers
TCK N/A Input The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to ground. This
pin uses Schmitt trigger input buffers

Referenced This chapter references the following documents:

Documents ■ AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices

■ AN 418: SRunner: An Embedded Solution for Serial Configuration Device
Programming
■ AN 423: Configuring the MicroBlaster Passive Serial Software Driver
■ ByteBlaster II Download Cable User Guide
■ ByteBlasterMV Download Cable User Guide
■ Cyclone FPGA Family Data Sheet section of the Cyclone Device
Handbook
■ DC and Switching Characteristics chapter in the Cyclone Device
Handbook
■ Design Debugging Using the SignalTap II Embedded Logic Analyzer
chapter in volume 3 of the Quartus II Handbook
■ MasterBlaster Serial/USB Communications Cable User Guide
■ Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and
EPCS128) Data Sheet
■ Software Settings section in volume 2 of the Configuration Handbook

13–50 Altera Corporation

Cyclone Device Handbook, Volume 1 May 2008
 Configuring Cyclone FPGAs

Document Table 13–13 shows the revision history for this chapter.

Revision History

Table 13–13. Document Revision History

Date and
Document Changes Made Summary of Changes
Version
May 2008 Minor textual and style changes. Added “Referenced —
v1.8 Documents” section.
January 2007 ● Added document revision history. —
v1.7 ● Removed a note from Table 13–2.
● Updated Figure 13–1.
● Updated Table 13–3.
● Updated feetpara note in “Active Serial Configuration (Serial
Configuration Devices)” section.
● Updated feetpara note on page 13–18.
● Updated Note (2) in Figure 13–11.
● Updated Note (4) in Figure 13–12.
● Updated Note (2) in Figure 13–19.
July 2006 Updated Figure 13–19. —
v1.6
August 2005 ● Updated tables. —
v1.5 ● Minor text updates.
March 2005 ● Updated Figure 13–1. —
v1.4 ● Updated Figure 13–10.
February 2005 Updated Figure 13–13. —
v1.3
August 2004 ● Deleted sections: Programming Configuration Devices, —
v1.2 Connecting the JTAG Chain, Passive Serial and JTAG,
Device Options, Device Configuration Files, Configuration
Reliability, and Board Layout Tips.
● Deleted figures: Embedded System Block Diagram,
Combining PS & JTAG Configuration, Configuration Options
Dialog Box.
● Deleted table: Cyclone Configuration Option Bits.
● Added: USB Blaster to cable list; new Figure 13–13; text on
pages 13-14, 13-29, and 13-30, and information to
Table 13–6.
● Changes to Figures 13–14 to 13–16, 13–19, 13–20, 13–25;
numbers changed in EP1C4 row of Table 13–3.
● Added extensive descriptions of configuration methods under
the “Configuring Multiple Devices with the Same Data”
section.
July 2003 v1.1 Updated .rbf sizes. Minor updates throughout the document. —
May 2003 v1.0 Added document to Cyclone Device Handbook. —

Altera Corporation 13–51

May 2008 Cyclone Device Handbook, Volume 1
Document Revision History

13–52 Altera Corporation

Cyclone Device Handbook, Volume 1 May 2008