October University for Modern Sciences and Arts (MSA)

October University for Modern Sciences & Arts

Final Exam
(Model Answer)

Faculty Engineering
Department Electrical Communication and Electronics
Module Code ECE 445/ ECE 561
Module Title VLSI Design
Semester Spring 2022
Time Allowed 3 hours
Total Mark 40
No. of Pages Seven (including the cover page)
Material provided None
Equipment permitted Non Programmable Calculator
Additional Instructions All Answers must be in English otherwise it will not be
considered.

No books, paper or electronic devices are permitted to be brought into the

examination room other than those specified above.

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Faculty of Engineering
Module Code: ECE 445/ ECE 561
Module Title: VLSI Design
Semester: Spring 2022
Answer the following questions (Four Questions):

Question 1: (LOs: 1, and 2) (8 Marks)

A Choose the Correct Answer
1. ____________ of CMOS transistors allows for their very high integration
0.5 pts
density in VLSI circuits.
(a) Low power (b) Small Size (c) High Performance (d) All of them
2. The number of gates in a MSI integration level are _______ 0.5 pts
(a) 100 (b) 1000 (c) >10,000 (d) None of them
3. Scaling down of the transistor dimensions in VLSI circuits _________
(a) Increases the packaging density (b) Decreases the switching speed 0.5 pts
(c) Increases the power consumption (d) All of them
4. To design high-volume products such as memory chips, and high-performance
microprocessors, the preferred design style is ______
(a) ASIC (b) FPGA (c) PAL (d) CPLD 0.5 pts
5. To add two 3-bits values from ports A and B and send to the result to external
5-bits port ALU_Out, which VHDL statement is true:______ 0.5 pts
(a) ALU_Out <= '0' & (A + B); (b) ALU_Out <= A + B;
(c) ALU_Out <= ('00'&A) + B; (d) ALU_Out <= ('0'&A) + B;
6. One of the simple programmable logic devices that has a fixed AND plane
and a programmable OR plane is ______
0.5 pts
(b) PLA (b) ROM (c) PAL (d) RAM

B Library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 5 pts
use IEEE.STD_LOGIC_UNSIGNED.ALL; 0.5 pts

Entity Clock_DIV is
PORT ( CLK, SEL : IN STD_LOGIC ; 1 pts
CDIV : OUT STD_LOGIC );
end Clock_DIV;

architecture Behavioral of Clock_DIV is

signal T: STD_LOGIC; 0.5 pts

Begin
Process (CLK)
variable I : integer := 0 ; 1 pts

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begin
I := I+1;
IF (( (I = 2) and (SEL = '1') ) OR ( (I = 3) and (SEL = '0')) ) THEN 1.5 pts
T <= NOT (T) ;
I := 0 ;
END IF;
END PROCESS;
DIV <= T ; 0.5 pts
END Behavioral;

Question 2: (LOs: 1, and 2) (13 Marks)

A 8 pts

2 pts

VHDL Code for the Soda Machine

1 pts

1 pts

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0.5 pts

2.5 pts

0.5 pts

2.5 pts

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B library ieee; 5 pts

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity RAM is
port( Clk, RE , WE, RST : in std_logic;
RAM_IN_Out: inout std_logic_vector (7 downto 0);
1 pts
RAM_ADD: in std_logic_vector(6 downto 0));
end RAM;

Architecture behav of RAM is

type ram_type is array (0 to 127) of std_logic_vector (7 downto 0);
signal tmp_ram: ram_type; 0.5 pts
Begin

X <= RE&WE ; 1 pts

Process(Clk , RST)
begin
IF( RST = '1') then
For I in 0 to 127 loop
tmp_ram (i) <= (others => ‘0’) ;
End loop ; 1 pts
Elseif rising_edge (Clk) then
Case X IS
WHEN "00" =>
RAM_in_out <= tmp_ram(conv_integer(RAM_ADD));
WHEN "11" =>
tmp_ram(conv_integer(RAM_ADD)) <= RAM_IN_Out; 1.5 pts
RAM_in_out <= (RAM_out'range => 'Z');
WHEN OTHERS =>
RAM_in_out <= (RAM_out'range => 'Z');
END Case;
end if;
end process;
end behav;

Question 3: (LOs: 1, and 2) (11 Marks)

A Expected no. of bits that represent the integer part of the output = 6 bits 6 pts

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 0.5 pts
USE IEEE.STD_LOGIC_SIGNED.ALL;

entity FIR_TEST is
PORT ( D : IN std_logic_vectore (3 DOWNTO 0);
RST , CLK : IN STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)); 1 pts
end FIR_TEST;

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Architecture Behavioral of FIR_TEST is

TYPE SHIFT IS ARRAY (1 TO 3) OF STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL Z : SHIFT; 0.5 pts
Begin
PROCESS ( RST, CLK ) 0.5 pts
BEGIN
IF RST = '0' THEN
FOR J IN 3 DOWNTO 1 LOOP
Z(J) <= (OTHERS => '0'); 1 pts
END LOOP;
FIR_OUT <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
FOR J IN 3 DOWNTO 1 LOOP
IF J = 1 THEN
Z(J) <= D; 1 pts
ELSE
Z(J)<= Z(J-1);
END IF ;
END LOOP;

FIR_OUT <= (D(3)&D(3)&D&”000”) +

(Z(1)(3)&Z(1)&”0000”) + (Z(1)(3)&Z(1)(3)&Z(1)&”000”)
- (Z(3)(3)&Z(3)(3)&Z(3)(3)&Z(3)(3)&Z(3)&”0”); 1.5 pts

END IF;
END PROCESS;
End Behavioral ;

B - External Interface (2 pts) 5 pts

- Each component interfacing (1.5 pts)
- Component interconnections (1.5 pts)

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Question 4: (LOs: 1, and 2) (8 Marks)

A . )
i 2 pts

ii 3 pts

iii 8 transistors are required 1 pts

C The logic function equivalent to the stick diagram is 3-Input NAND gate 2 pts

The End, best wishes, Dr. Hatem Zakaria

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