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Final Exam - VLSI - Fall2018 - Answer
Final Exam - VLSI - Fall2018 - Answer
Final Exam
(Model Answer)
Faculty Engineering
Department Electrical Communication and Electronics
Module Code ECE 445/ ECE 561
Module Title VLSI Design
Semester Fall 2018
Time Allowed 3 hours
Total Mark 40
No. of Pages Six (including the cover page)
Material provided None
Equipment permitted Non programmable calculator
Additional Instructions All Answers must be in English otherwise it will not be
considered.
Page 1 of 6
October University for Modern Sciences and Arts (MSA)
Faculty of Engineering
Module Code: ECE 445/ ECE 561
Module Title: VLSI Design
Semester: Fall 2018
Model Answer:
BEGIN
SEL <= PO&PU ; 1 pts
PROCESS ( CLK )
BEGIN
IF RISING_EDGE(CLK) THEN 0.5 pts
CASE SEL IS
WHEN "10" => A (CONV_INTEGER(SADD +1)) <= SIN;
SADD <= SADD +1;
SOUT <= (OTHERS => 'Z');
1.5 pts
WHEN "01" => SOUT <= A(CONV_INTEGER(SADD));
SADD <= SADD-1;
WHEN OTHERS => SOUT <= (OTHERS=>'X');
END CASE;
END IF;
END PROCESS;
END STACK;
Page 2 of 6
October University for Modern Sciences and Arts (MSA)
Entity C_DIV is
PORT ( CLK, SEL : IN STD_LOGIC ; 1 pts
DIV : OUT STD_LOGIC );
end C_DIV;
Question 2: (7 Marks)
Din + 0.625 DINZ-2- 0.283 DinZ-4
0.283 ≈ ¼ + 1/32 = Z-2 + Z-5 1 pts
-4
0.625 ≈ 1/16 Z
Expected no. of bits that represent the integer part of the output = 6 bits
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 0.5 pts
USE IEEE.STD_LOGIC_SIGNED.ALL;
entity FIR_TEST is
PORT ( D : IN std_logic_vector ( 3 DOWNTO 0);
RST , CLK : IN STD_LOGIC;
1 pts
F : OUT STD_LOGIC_VECTOR (12 DOWNTO 0));
end FIR_TEST;
Page 3 of 6
October University for Modern Sciences and Arts (MSA)
Begin
PROCESS ( RST, CLK ) 0.5 pts
BEGIN
IF RST = '1' THEN
FOR J IN 4 DOWNTO 1 LOOP
Z(J) <= (OTHERS => '0'); 1 pts
END LOOP;
FIR_OUT <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
FOR J IN 4 DOWNTO 1 LOOP
IF J = 1 THEN
Z(J) <= DIN; 1 pts
ELSE
Z(J)<= Z(J-1);
END IF ;
END LOOP;
END IF;
END PROCESS;
End Behavioral ;
entity TOP is
PORT ( ADD : IN OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
DATA : IN OUT STD_LOGIC_VECTOR ( 5 DOWNTO 0 ); 2 pts
POP , PUSH , MCLK , RESET : IN STD_LOGIC
TOP_O1 , TOP_O2 : OUT STD_LOGIC_VECTOR ( 12 DOWNTO 0 ) );
end TOP;
COMPONENT FIR
PORT ( D : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0); 1 pts
CLK , RST: IN STD_LOGIC ;
F: OUT STD_LOGIC_VECTOR ( 12 DOWNTO 0));
END COMPONENT;
Page 4 of 6
October University for Modern Sciences and Arts (MSA)
COMPONENT STACK
PORT ( SADD : INOUT STD_LOGIC_VECTOR (4 downto 0); 1 pts
SIN : in STD_LOGIC_VECTOR (12 downto 0);
SOUT : out unsigned ( 12 downto 0);
PO , PU , CLK : in std_logic );
end COMPONENT;
COMPONENT C_DIV
PORT ( CLK, SEL : IN STD_LOGIC ; 1 pts
CDIV : OUT STD_LOGIC );
end COMPONENT ;
Begin
TOP_O2 <= X ;
END TOP;
Question 4: (10 Marks)
A i 2 pts
ii 2 pts
Page 5 of 6
October University for Modern Sciences and Arts (MSA)
B 3 pts
C 2 pts
The logic Function is
– = + + .
Page 6 of 6