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Tps 54227
Tps 54227
TPS54227
SLVSAU2C – MAY 2011 – REVISED DECEMBER 2015
– High-Definition Blu-ray Disc™ Players (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Networking Home Terminals
– Digital Set Top Boxes (STB)
Simplified Schematic TPS54227 Transient Response
Iout (1 A/div)
100 ms/div
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54227
SLVSAU2C – MAY 2011 – REVISED DECEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 1 8 Application and Implementation ........................ 11
3 Description ............................................................. 1 8.1 Application Information............................................ 11
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 11
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 15
6 Specifications......................................................... 4 10 Layout................................................................... 15
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 15
6.2 ESD Ratings.............................................................. 4 10.2 Layout Examples................................................... 15
6.3 Recommended Operating Conditions....................... 4 10.3 Thermal Considerations ........................................ 16
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 17
6.5 Electrical Characteristics........................................... 5 11.1 Documentation Support ........................................ 17
6.6 Typical Characteristics .............................................. 6 11.2 Community Resources.......................................... 17
7 Detailed Description .............................................. 8 11.3 Trademarks ........................................................... 17
7.1 Overview ................................................................... 8 11.4 Electrostatic Discharge Caution ............................ 17
7.2 Functional Block Diagram ......................................... 8 11.5 Glossary ................................................................ 17
7.3 Feature Description................................................... 8 12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DDA Package
8-Pin HSOP DRC Package
Top View 10-Pin VSON
Top View
1 EN VIN 8 EN 1 10 VIN
4 SS GND 5
Pin Functions
PIN
I/O DESCRIPTION
NAME DDA DRC
EN 1 1 I Enable input control. EN is active high and must be pulled up to enable the device.
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must
Exposed —
be connected to GND.
Thermal G
Pad Thermal pad of the package. PGND power ground return of internal low-side FET. Must
—
be soldered to achieve appropriate dissipation.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB
GND 5 5 G
returns to GND at a single point.
SS 4 4 O Soft-start control. An external capacitor should be connected to GND.
SW 6 6, 7 O Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between
VBST 7 8 I
VBST and SW pins. An internal diode is connected between VREG5 and VBST.
VFB 2 2 I Converter feedback input. Connect to output voltage with feedback resistor divider.
VIN 8 9, 10 P Input voltage supply pin.
5.5-V power supply output. A capacitor (typical 1 µF) should be connected to GND.
VREG5 3 3 O
VREG5 is not active when EN is low.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, EN –0.3 20 V
VBST –0.3 26 V
VBST (10-ns transient) –0.3 28 V
Input voltage VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5 V
SW –2 20 V
SW (10-ns transient) –3 22 V
VREG5 –0.3 6.5 V
Output voltage
GND –0.3 0.3 V
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
1200 14
12
1000
10
800
VIN = 12 V
8
600
6
400
4
200
2
0 0
-50 0 50 100 150 -50 0 50 100 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
70
80
VO = 2.5 V
Efficiency - %
60 VO = 1.8 V
50 70
40 VIN = 18 V
60
30
20
50
10
0 40
0 5 10 15 20 0 0.5 1 1.5 2
VI - Input Voltage - V IO - Output Current - A
850 850
VO = 2.5 V
fsw - Switching Frequency - kHz
VO = 3.3 V VO = 1.8 V
750 750 VO = 3.3 V
700 700
650 650
450 450
400 400
0 5 10 15 20 0 0.5 1 1.5 2
VI - Input Voltage - V IO - Output Current - A
0.775
0.765
0.760
0.755
0.750
-50 0 50 100 150
o
TJ - Junction Temperature - C
7 Detailed Description
7.1 Overview
The TPS54227 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
EN EN VIN
1
Logic
VIN
8
VREG5
VBST
Control Logic 7
Ref +
SS + PWM
1 shot
VFB SW VO
2 - 6
XCON
ON
VREG5
VREG5 Ceramic
3 Capacitor
SGND
SS SS 5
4 Softstart
GND
PGND
SGND
+ SW
OCP
- PGND
VIN
REF Ref
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
U1
TPS54227DDA
(1) Optional
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
V V - VOUT
I = OUT x IN(max)
IPP V L x f
IN(max) O SW (4)
I
lpp
I =I +
Ipeak O 2 (5)
2 1 2
I = I + I
Lo(RMS) O 12 IPP (6)
For this design example, the calculated peak current is 2.311 A and the calculated RMS current is 2.008 A. The
inductor used is a TDK CLF7045T-2R2M with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54227 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
VOUT x (VIN - VOUT )
I =
Co(RMS) 12 x VIN x LO x fSW
(7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.18 A and each output capacitor is rated for 4A.
1.1 1.08
VI = 1.8 V
1.075 VI = 1.2 V 1.07
VO - Output Voltage - V
VO - Output Voltage - V
IO = 0 A
1.05 1.06
VI = 5 V
IO = 1 A
1.025 1.05
1.04
1
0 5 10 15 20
0 0.5 1 1.5 2
IO - Output Current - A VI - Input Voltage - V
Figure 9. 1.05-V Output Voltage vs Output Current Figure 10. 1.05-V Output Voltage vs Input Voltage
EN (10 V/div)
Vout (50 mV/div)
VREG5 (5 V/div)
Iout (1 A/div)
VO = 1.05 V VO = 1.05 V
SW (5 V/div) SW (5 V/div)
100 100
90 90
80 80
70 70
Efficiency - %
Efficiency - %
60 60
50 50
40 40
30 30
20 20
10 VIN = 5 V 10 VIN = 5 V
VIN = 12 V VIN = 12 V
0 0
0 0.5 1 1.5 2 0.01 0.1 1 10
Output Current - A D001
Output Current - A D001
Figure 15. TPS54227EVM-686 Efficiency Figure 16. TPS54227EVM-686 Light Load Efficiency
10 Layout
VIN VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
FEEDBACK CAPACITOR
RESISTORS
TO ENABLE
CONTROL EN VIN
BOOST
VFB VBST CAPACITOR
VREG5 SW
BIAS SS GND
OUTPUT
INDUCTOR
VOUT
CAP
SLOW
START
CAP
EXPOSED
THERMAL PAD
Connection to
AREA OUTPUT
POWER GROUND FILTER
on internal or CAPACITOR
bottom layer
ANALOG
GROUND
TRACE
POWER GROUND
VIN VIN
INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
HIGH FREQENCY
RESISTORS BYPASS
TO ENABLE
CONTROL EN VIN CAPACITOR
VFB VIN
VREG5 VBST
BOOST
CAPACITOR
BIAS
CAP SS SW VOUT
SLOW
START GND SW OUTPUT
CAP
INDUCTOR
EXPOSED OUTPUT
THERMAL PAD FILTER
AREA
ANALOG
Connection to
CAPACITOR
GROUND
TRACE POWER GROUND
on internal or
bottom layer
POWER GROUND
11.3 Trademarks
D-CAP2, WEBENCH, PowerPAD, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS54227DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54227
TPS54227DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54227
TPS54227DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 54227
TPS54227DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 54227
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2023
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2023
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2023
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
3 x 3, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
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PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
1.0 C
0.8
SEATING PLANE
0.05
0.00 0.08 C
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD
5 6
2X 11 SYMM
2
2.4 0.1
10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
SYMM (2.4)
(3.4)
(0.95)
8X (0.5)
5 6
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP
10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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