DIGITAL SYSTEMS

QUIZ
50 minutes
Grade:
Name : ............................................................... Student ID : .............................

1. The 1’s complement (4-bit) representation of 010 is?

A. 0000 C. A and B are correct
B. 1111 D. A and B are not correct
2. Using 5 bits to represent each number, the representations of 13 and -13 in signed 2's
complement integers:
A. 01101 & 11101 C. 01101 & 10011
B. 01101 & 10010 D. None of above
3. Sign extension from 5 bits to 8 bits represent -13 in signed 2's complement integers of the
above question:
A. 00011101 C. 00010011
B. 11110010 D. None of above
4. The range of signed decimal numbers that can be represented by 6-bit 1’s complement form is:
A. -31 to +31 C. -64 to +63
B. -63 to +64 D. -32 to +31
5. The two numbers represented in signed 2’s complement form are P = 11101101 and Q =
11100110. If Q is subtracted from P, the value obtained in signed 2’s complement form is:
A. 100000111 C. 11111001
B. 00000111 D. 111111001
6. How many AND, OR and EX-OR gates are requires for the configuration of full adder?
A. 1, 2, 2 C. 3, 1, 2
B. 2, 1, 2 D. 4, 0 ,1
7. Half-adders have a major limitation in that they cannot:
A. Accept a carry from a present stage
B. Accept a carry bit from a next stage
C. Accept a carry bit from a previous stage
D. Accept a carry bit from the following stages
8. The difference output of a full subtractor is same as:
A. Half Adder C. Half Subtractor
B. Full Adder D. None of above
9. What is the result of the following multiplication (unsigned binary numbers): 010012 x 010112?
A. 001100011 C. 010100110
B. 110011100 D. 101010111
10. What is quotient and remainder of the following division (unsigned binary numbers): 1111012 ÷
10012?
A. 0111 & 0110 C. 0110 & 1100
B. 1010 & 0111 D. 0110 & 0111
11. One of the advantages of the fast carry or look-ahead carry circuits found in most 4-bit parallel-
adder circuits?
A. Add a 1 to complemented inputs C. Determine sign and magnitude
B. Increase ripple delay D. Reduce propagation delay
12. The carry generate (CG) and carry propagate (CP) function of the Carry Look-Ahead adder is?
A. CG = A or B, CP = A xor B C. CG = A and B, CP = A xor B
B. CG = A xor B, CP = A or B D. CG = A and B, CP = A or B
13. A register is defined as:
A. The group of latches for storing one bit of information
B. The group of latches for storing n-bit of information
C. The group of flip-flops suitable for storing one bit of information
D. The group of flip-flops suitable for storing binary information
14. A shift register is defined as:
A. The register capable of shifting information to another register
B. The register capable of shifting information either to the right or to the left
C. The register capable of shifting information to the right only
D. The register capable of shifting information to the left only
15. The full form of SIPO is:
A. Serial-in Parallel-out C. Serial-in Serial-out
B. Parallel-in Serial-out D. Serial-in Peripheral-out
16. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift
register with an initial state 01110. After three clock pulses, the register contains:
A. 01110 C. 00101
B. 00001 D. 00110
17. With a 200 KHz clock frequency, eight bits can be serially entered into a shift register in:
A. 4 μs B. 40 μs C. 400 μs D. 40 ms
18. Ripple counter’s speed is limited by the propagation delay of:
A. Each flip-flop C. The flip-flops only with gates
B. All flip-flops and gates D. Only circuit gates
19. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is:
A. 20% B. 50% C. 10% D. 50%
20. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation
delay:
A. 12 ms B. 24 ns C. 48 ns D. 60 ns
21. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the
sixth clock pulse, the sequence is:
A. Q0 = 1, Q1 = 0, Q2 = 0, and Q3 = 0 C. Q0 = 0, Q1 = 0, Q2 = 1, and Q3 = 1
B. Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0 D. Q0 = 0, Q1 = 0, Q2 = 0, and Q3 = 1
22. What is the difference between a ring shift counter and a Johnson shift counter:
A. There is no difference C. The feedback is reversed
B. A ring is faster D. The Johnson is faster
23. In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns:
A. 2 B. 6 C. 12 D. 24
24. A MOD-12 ring counter requires a minimum of;
A. 10 Flip-flops C. 6 Flip-flops
B. 12 Flip-flops D. 2 Flip-flops
25. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock
pulses?
A. 10002 C. 10112
B. 10102 D. 11012
26. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input
clock frequency is 60 MHz:
A. 500 kHz C. 6 MHz
B. 1500 kHz D. 5 MHz
27. Most demultiplexers facilitate which of the following?
A. multiple inputs, single output C. odd parity to even parity
B. single input, multiple outputs D. decimal to hexadecimal
28. A MSI combinational circuit which is used to change a decimal number into an equivalent BCD
number is:
A. Multiplexer C. Decoder
B. Demultiplexer D. Encoder
29. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A. 4 B. 7 C. 8 D. 16
30. A decoder can be used as a Demultiplexer by:
A. tying all enable pins LOW
B. tying all data-select lines LOW
C. tying all data-select lines HIGH
D. using the input lines for data selection and an enable line for data input
31. A data selector is also called a
A. Multiplexer C. Priority encoder
B. De-multiplexer D. Decoder
32. Which Boolean expression has the same functionality as output f(cba) of the following MUX?

A. abc + ab′ 0
f
1
B. b+ c 0
C. a′b + bc c
a
MUX
D. b b
33. Which of the following statements is false?
A. A binary decoder has n inputs and 2n outputs.
B. A binary encoder has 2n inputs and n outputs.
C. A 74138 is a 3-to-8 decoder
D. A demultiplexer is the same circuit as an encoder.
34. What is the function of this circuit:
A. f(x,y,z) = ∑(2, 3, 4, 7)
B. f(x,y,z) = ∑(1, 2, 4, 7)
C. f(x,y,z) = ∑(1, 3, 4, 7)
D. f(x,y,z) = ∑(1, 3, 5, 6)

35. What are the outputs of a 7485 four- bit magnitude comparator when the inputs are A = 0001 and B =
0100?

A. A<B is 0, A=B is 1, A>B is 1 B. A<B is 0, A=B is 1, A>B is 0

 C. A<B is 1, A=B is 0, A>B is 0 D. A<B is 0, A=B is 0, A>B is 1

36. How is the number five (5) indicated on the outputs of a 7447 BCD- to- seven- segment code
converter?

A. Segments a, c, d, f, and g active.

B. Segments a, c, d, e, f, and g are active.
C. Segments a, b, d, e, f, and g are active.
D. Segments a, c, d, and g are active.

37. List which pins need to be connected together on two 74293 to make a MOD-60 counter?

38. Design a synchronous counter for the following sequence using D Flip-Flops.

39. Given F(A,B,C,D)=  m (0, 1, 3, 4, 8, 9, 15); D = LSB. Implement F using one Multiplexer 8-to-1

40. The circuit below is made from two D-type flip-flops with an asynchronous CLR input. Assume that A
and B are both low initially. Sketch a timing diagram showing the waveforms of CLK, A and B for the
next six clock pulses.

D A D B
CLK

A B
CLR CLR